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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / net / sky2.h
blob7bb3ba9bcbd8519ea58804dba861e1b6e2001b79
1 /*
2 * Definitions for the new Marvell Yukon 2 driver.
3 */
4 #ifndef _SKY2_H
5 #define _SKY2_H
6
7 #define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */
8
9 /* PCI config registers */
10 enum {
11 PCI_DEV_REG1 = 0x40,
12 PCI_DEV_REG2 = 0x44,
13 PCI_DEV_STATUS = 0x7c,
14 PCI_DEV_REG3 = 0x80,
15 PCI_DEV_REG4 = 0x84,
16 PCI_DEV_REG5 = 0x88,
17 PCI_CFG_REG_0 = 0x90,
18 PCI_CFG_REG_1 = 0x94,
19 };
20
21 /* Yukon-2 */
22 enum pci_dev_reg_1 {
23 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
24 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
25 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
26 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
27 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
28 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
29 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
30 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
31 };
32
33 enum pci_dev_reg_2 {
34 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
35 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
36 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
37
38 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
39 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
40 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
41 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
42
43 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
44 };
45
46 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
47 enum pci_dev_reg_4 {
48 /* (Link Training & Status State Machine) */
49 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
50 /* (Active State Power Management) */
51 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
52 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
53 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
54 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
55
56 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
57 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
58 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
59 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
60 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
61 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
62 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
63 };
64
65 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
66 enum pci_dev_reg_5 {
67 /* Bit 31..27: for A3 & later */
68 P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */
69 P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
70 P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
71 P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
72 /* Bit 26..16: Release Clock on Event */
73 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
74 P_REL_GPHY_REC_PACKET = 1<<25, /* GPHY Received Packet */
75 P_REL_INT_FIFO_N_EMPTY = 1<<24, /* Internal FIFO Not Empty */
76 P_REL_MAIN_PWR_AVAIL = 1<<23, /* Main Power Available */
77 P_REL_CLKRUN_REQ_REL = 1<<22, /* CLKRUN Request Release */
78 P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */
79 P_REL_PME_ASSERTED = 1<<20, /* PME Asserted */
80 P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */
81 P_REL_LOADER_NOT_FIN = 1<<18, /* EPROM Loader Not Finished */
82 P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */
83 P_REL_GPHY_LINK_UP = 1<<16, /* GPHY Link Up */
84
85 /* Bit 10.. 0: Mask for Gate Clock */
86 P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */
87 P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */
88 P_GAT_INT_FIFO_EMPTY = 1<<8, /* Internal FIFO Empty */
89 P_GAT_MAIN_PWR_N_AVAIL = 1<<7, /* Main Power Not Available */
90 P_GAT_CLKRUN_REQ_REL = 1<<6, /* CLKRUN Not Requested */
91 P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */
92 P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */
93 P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */
94 P_GAT_LOADER_FINISHED = 1<<2, /* EPROM Loader Finished */
95 P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */
96 P_GAT_GPHY_LINK_DOWN = 1<<0, /* GPHY Link Down */
97
98 PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET |
99 P_REL_INT_FIFO_N_EMPTY |
100 P_REL_PCIE_EXIT_L1_ST |
101 P_REL_PCIE_RX_EX_IDLE |
102 P_GAT_GPHY_N_REC_PACKET |
103 P_GAT_INT_FIFO_EMPTY |
104 P_GAT_PCIE_ENTER_L1_ST |
105 P_GAT_PCIE_RX_EL_IDLE,
106 };
107
108 #/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
109 enum pci_cfg_reg1 {
110 P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */
111 /* Bit 23..21: Release Clock on Event */
112 P_CF1_REL_LDR_NOT_FIN = 1<<23, /* EEPROM Loader Not Finished */
113 P_CF1_REL_VMAIN_AVLBL = 1<<22, /* Vmain available */
114 P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */
115 /* Bit 20..18: Gate Clock on Event */
116 P_CF1_GAT_LDR_NOT_FIN = 1<<20, /* EEPROM Loader Finished */
117 P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */
118 P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */
119 P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
120 P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */
121
122 P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */
123
124 P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */
125 P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */
126
127 PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST |
128 P_CF1_REL_LDR_NOT_FIN |
129 P_CF1_REL_VMAIN_AVLBL |
130 P_CF1_REL_PCIE_RESET |
131 P_CF1_GAT_LDR_NOT_FIN |
132 P_CF1_GAT_PCIE_RESET |
133 P_CF1_PRST_PHY_CLKREQ |
134 P_CF1_ENA_CFG_LDR_DONE |
135 P_CF1_ENA_TXBMU_RD_IDLE |
136 P_CF1_ENA_TXBMU_WR_IDLE,
137 };
138
139
140 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
141 PCI_STATUS_SIG_SYSTEM_ERROR | \
142 PCI_STATUS_REC_MASTER_ABORT | \
143 PCI_STATUS_REC_TARGET_ABORT | \
144 PCI_STATUS_PARITY)
145
146 enum csr_regs {
147 B0_RAP = 0x0000,
148 B0_CTST = 0x0004,
149 B0_Y2LED = 0x0005,
150 B0_POWER_CTRL = 0x0007,
151 B0_ISRC = 0x0008,
152 B0_IMSK = 0x000c,
153 B0_HWE_ISRC = 0x0010,
154 B0_HWE_IMSK = 0x0014,
155
156 /* Special ISR registers (Yukon-2 only) */
157 B0_Y2_SP_ISRC2 = 0x001c,
158 B0_Y2_SP_ISRC3 = 0x0020,
159 B0_Y2_SP_EISR = 0x0024,
160 B0_Y2_SP_LISR = 0x0028,
161 B0_Y2_SP_ICR = 0x002c,
162
163 B2_MAC_1 = 0x0100,
164 B2_MAC_2 = 0x0108,
165 B2_MAC_3 = 0x0110,
166 B2_CONN_TYP = 0x0118,
167 B2_PMD_TYP = 0x0119,
168 B2_MAC_CFG = 0x011a,
169 B2_CHIP_ID = 0x011b,
170 B2_E_0 = 0x011c,
171
172 B2_Y2_CLK_GATE = 0x011d,
173 B2_Y2_HW_RES = 0x011e,
174 B2_E_3 = 0x011f,
175 B2_Y2_CLK_CTRL = 0x0120,
176
177 B2_TI_INI = 0x0130,
178 B2_TI_VAL = 0x0134,
179 B2_TI_CTRL = 0x0138,
180 B2_TI_TEST = 0x0139,
181
182 B2_TST_CTRL1 = 0x0158,
183 B2_TST_CTRL2 = 0x0159,
184 B2_GP_IO = 0x015c,
185
186 B2_I2C_CTRL = 0x0160,
187 B2_I2C_DATA = 0x0164,
188 B2_I2C_IRQ = 0x0168,
189 B2_I2C_SW = 0x016c,
190
191 B3_RAM_ADDR = 0x0180,
192 B3_RAM_DATA_LO = 0x0184,
193 B3_RAM_DATA_HI = 0x0188,
194
195 /* RAM Interface Registers */
196 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
197 /*
198 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
199 * not usable in SW. Please notice these are NOT real timeouts, these are
200 * the number of qWords transferred continuously.
201 */
202 #define RAM_BUFFER(port, reg) (reg | (port <<6))
203
204 B3_RI_WTO_R1 = 0x0190,
205 B3_RI_WTO_XA1 = 0x0191,
206 B3_RI_WTO_XS1 = 0x0192,
207 B3_RI_RTO_R1 = 0x0193,
208 B3_RI_RTO_XA1 = 0x0194,
209 B3_RI_RTO_XS1 = 0x0195,
210 B3_RI_WTO_R2 = 0x0196,
211 B3_RI_WTO_XA2 = 0x0197,
212 B3_RI_WTO_XS2 = 0x0198,
213 B3_RI_RTO_R2 = 0x0199,
214 B3_RI_RTO_XA2 = 0x019a,
215 B3_RI_RTO_XS2 = 0x019b,
216 B3_RI_TO_VAL = 0x019c,
217 B3_RI_CTRL = 0x01a0,
218 B3_RI_TEST = 0x01a2,
219 B3_MA_TOINI_RX1 = 0x01b0,
220 B3_MA_TOINI_RX2 = 0x01b1,
221 B3_MA_TOINI_TX1 = 0x01b2,
222 B3_MA_TOINI_TX2 = 0x01b3,
223 B3_MA_TOVAL_RX1 = 0x01b4,
224 B3_MA_TOVAL_RX2 = 0x01b5,
225 B3_MA_TOVAL_TX1 = 0x01b6,
226 B3_MA_TOVAL_TX2 = 0x01b7,
227 B3_MA_TO_CTRL = 0x01b8,
228 B3_MA_TO_TEST = 0x01ba,
229 B3_MA_RCINI_RX1 = 0x01c0,
230 B3_MA_RCINI_RX2 = 0x01c1,
231 B3_MA_RCINI_TX1 = 0x01c2,
232 B3_MA_RCINI_TX2 = 0x01c3,
233 B3_MA_RCVAL_RX1 = 0x01c4,
234 B3_MA_RCVAL_RX2 = 0x01c5,
235 B3_MA_RCVAL_TX1 = 0x01c6,
236 B3_MA_RCVAL_TX2 = 0x01c7,
237 B3_MA_RC_CTRL = 0x01c8,
238 B3_MA_RC_TEST = 0x01ca,
239 B3_PA_TOINI_RX1 = 0x01d0,
240 B3_PA_TOINI_RX2 = 0x01d4,
241 B3_PA_TOINI_TX1 = 0x01d8,
242 B3_PA_TOINI_TX2 = 0x01dc,
243 B3_PA_TOVAL_RX1 = 0x01e0,
244 B3_PA_TOVAL_RX2 = 0x01e4,
245 B3_PA_TOVAL_TX1 = 0x01e8,
246 B3_PA_TOVAL_TX2 = 0x01ec,
247 B3_PA_CTRL = 0x01f0,
248 B3_PA_TEST = 0x01f2,
249
250 Y2_CFG_SPC = 0x1c00, /* PCI config space region */
251 Y2_CFG_AER = 0x1d00, /* PCI Advanced Error Report region */
252 };
253
254 /* B0_CTST 16 bit Control/Status register */
255 enum {
256 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
257 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
258 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
259 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
260 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
261 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
262 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
263 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
264 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
265 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
266
267 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
268 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
269 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
270 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
271 CS_MRST_CLR = 1<<3, /* Clear Master reset */
272 CS_MRST_SET = 1<<2, /* Set Master reset */
273 CS_RST_CLR = 1<<1, /* Clear Software reset */
274 CS_RST_SET = 1, /* Set Software reset */
275 };
276
277 /* B0_LED 8 Bit LED register */
278 enum {
279 /* Bit 7.. 2: reserved */
280 LED_STAT_ON = 1<<1, /* Status LED on */
281 LED_STAT_OFF = 1, /* Status LED off */
282 };
283
284 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
285 enum {
286 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
287 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
288 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
289 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
290 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
291 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
292 PC_VCC_ON = 1<<1, /* Switch VCC On */
293 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
294 };
295
296 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
297
298 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
299 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
300 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
301 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
302 enum {
303 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
304 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
305 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
306
307 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
308 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
309 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
310 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
311
312 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
313 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
314 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
315 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
316 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
317
318 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
319 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
320 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
321 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
322 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
323
324 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
325 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
326 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
327 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
328 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
329 Y2_IS_ERROR = Y2_IS_HW_ERR |
330 Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 |
331 Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
332 };
333
334 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
335 enum {
336 IS_ERR_MSK = 0x00003fff,/* All Error bits */
337
338 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
339 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
340 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
341 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
342 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
343 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
344 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
345 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
346 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
347 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
348 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
349 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
350 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
351 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
352 };
353
354 /* Hardware error interrupt mask for Yukon 2 */
355 enum {
356 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
357 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
358 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
359 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
360 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
361 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
362 /* Link 2 */
363 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
364 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
365 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
366 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
367 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
368 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
369 /* Link 1 */
370 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
371 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
372 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
373 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
374 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
375 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
376
377 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
378 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
379 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
380 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
381
382 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
383 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
384 };
385
386 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
387 enum {
388 DPT_START = 1<<1,
389 DPT_STOP = 1<<0,
390 };
391
392 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
393 enum {
394 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
395 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
396 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
397 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
398 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
399 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
400 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
401 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
402 };
403
404 /* B2_GPIO */
405 enum {
406 GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */
407 GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
408
409 GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
410 GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
411 GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */
412 GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */
413 GLB_GPIO_TEST_SEL_BASE = 1<<11,
414 GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */
415 GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */
416 };
417
418 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
419 enum {
420 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
421 /* Bit 3.. 2: reserved */
422 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
423 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
424 };
425
426 /* B2_CHIP_ID 8 bit Chip Identification Number */
427 enum {
428 CHIP_ID_YUKON_XL = 0xb3, /* YUKON-2 XL */
429 CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */
430 CHIP_ID_YUKON_EX = 0xb5, /* YUKON-2 Extreme */
431 CHIP_ID_YUKON_EC = 0xb6, /* YUKON-2 EC */
432 CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */
433 CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
434 CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
435 };
436 enum yukon_ec_rev {
437 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
438 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
439 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
440 };
441 enum yukon_ec_u_rev {
442 CHIP_REV_YU_EC_U_A0 = 1,
443 CHIP_REV_YU_EC_U_A1 = 2,
444 CHIP_REV_YU_EC_U_B0 = 3,
445 };
446 enum yukon_fe_rev {
447 CHIP_REV_YU_FE_A1 = 1,
448 CHIP_REV_YU_FE_A2 = 2,
449 };
450 enum yukon_fe_p_rev {
451 CHIP_REV_YU_FE2_A0 = 0,
452 };
453 enum yukon_ex_rev {
454 CHIP_REV_YU_EX_A0 = 1,
455 CHIP_REV_YU_EX_B0 = 2,
456 };
457
458
459 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
460 enum {
461 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
462 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
463 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
464 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
465 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
466 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
467 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
468 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
469 };
470
471 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
472 enum {
473 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
474 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
475 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
476 };
477 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
478 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
479
480
481 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
482 enum {
483 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
484 #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
485 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
486 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
487 #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
488 #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
489 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
490 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
491 };
492
493 /* B2_TI_CTRL 8 bit Timer control */
494 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
495 enum {
496 TIM_START = 1<<2, /* Start Timer */
497 TIM_STOP = 1<<1, /* Stop Timer */
498 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
499 };
500
501 /* B2_TI_TEST 8 Bit Timer Test */
502 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
503 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
504 enum {
505 TIM_T_ON = 1<<2, /* Test mode on */
506 TIM_T_OFF = 1<<1, /* Test mode off */
507 TIM_T_STEP = 1<<0, /* Test step */
508 };
509
510 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
511 /* Bit 31..19: reserved */
512 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
513 /* RAM Interface Registers */
514
515 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
516 enum {
517 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
518 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
519
520 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
521 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
522 };
523
524 #define SK_RI_TO_53 36 /* RAM interface timeout */
525
526
527 /* Port related registers FIFO, and Arbiter */
528 #define SK_REG(port,reg) (((port)<<7)+(reg))
529
530 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
531 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
532 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
533 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
534 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
535
536 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
537
538 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
539 enum {
540 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
541 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
542 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
543 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
544 TXA_START_RC = 1<<3, /* Start sync Rate Control */
545 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
546 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
547 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
548 };
549
550 /*
551 * Bank 4 - 5
552 */
553 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
554 enum {
555 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
556 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
557 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
558 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
559 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
560 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
561 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
562 };
563
564
565 enum {
566 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
567 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
568 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
569 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
570 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
571 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
572 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
573 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
574 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
575 };
576
577 /* Queue Register Offsets, use Q_ADDR() to access */
578 enum {
579 B8_Q_REGS = 0x0400, /* base of Queue registers */
580 Q_D = 0x00, /* 8*32 bit Current Descriptor */
581 Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */
582 Q_DONE = 0x24, /* 16 bit Done Index */
583 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
584 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
585 Q_BC = 0x30, /* 32 bit Current Byte Counter */
586 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
587 Q_TEST = 0x38, /* 32 bit Test/Control Register */
588
589 /* Yukon-2 */
590 Q_WM = 0x40, /* 16 bit FIFO Watermark */
591 Q_AL = 0x42, /* 8 bit FIFO Alignment */
592 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
593 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
594 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
595 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
596 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
597 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
598 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
599 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
600 };
601 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
602
603 /* Q_TEST 32 bit Test Register */
604 enum {
605 /* Transmit */
606 F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */
607 F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */
608
609 /* Receive */
610 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
611
612 /* Hardware testbits not used */
613 };
614
615 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
616 enum {
617 Y2_B8_PREF_REGS = 0x0450,
618
619 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
620 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
621 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
622 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
623 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
624 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
625 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
626 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
627 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
628 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
629
630 PREF_UNIT_MASK_IDX = 0x0fff,
631 };
632 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
633
634 /* RAM Buffer Register Offsets */
635 enum {
636
637 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
638 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
639 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
640 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
641 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
642 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
643 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
644 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
645 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
646 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
647 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
648 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
649 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
650 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
651 };
652
653 /* Receive and Transmit Queues */
654 enum {
655 Q_R1 = 0x0000, /* Receive Queue 1 */
656 Q_R2 = 0x0080, /* Receive Queue 2 */
657 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
658 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
659 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
660 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
661 };
662
663 /* Different PHY Types */
664 enum {
665 PHY_ADDR_MARV = 0,
666 };
667
668 #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))
669
670
671 enum {
672 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
673 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
674 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
675 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
676
677 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
678
679 /* Receive GMAC FIFO (YUKON and Yukon-2) */
680
681 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
682 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
683 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
684 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
685 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
686 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
687 RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
688 RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
689 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
690 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
691
692 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
693
694 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
695
696 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
697 };
698
699
700 /* Q_BC 32 bit Current Byte Counter */
701
702 /* BMU Control Status Registers */
703 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
704 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
705 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
706 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
707 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
708 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
709 /* Q_CSR 32 bit BMU Control/Status Register */
710
711 /* Rx BMU Control / Status Registers (Yukon-2) */
712 enum {
713 BMU_IDLE = 1<<31, /* BMU Idle State */
714 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
715 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
716
717 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
718 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
719 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
720 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
721 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
722 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
723 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
724 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
725 BMU_START = 1<<8, /* Start Rx/Tx Queue */
726 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
727 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
728 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
729 BMU_FIFO_RST = 1<<4, /* Reset FIFO */
730 BMU_OP_ON = 1<<3, /* BMU Operational On */
731 BMU_OP_OFF = 1<<2, /* BMU Operational Off */
732 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
733 BMU_RST_SET = 1<<0, /* Set BMU Reset */
734
735 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
736 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
737 BMU_FIFO_ENA | BMU_OP_ON,
738
739 BMU_WM_DEFAULT = 0x600,
740 BMU_WM_PEX = 0x80,
741 };
742
743 /* Tx BMU Control / Status Registers (Yukon-2) */
744 /* Bit 31: same as for Rx */
745 enum {
746 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
747 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
748 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
749 };
750
751 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
752 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
753 enum {
754 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
755 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
756 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
757 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
758 };
759
760 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
761 /* RB_START 32 bit RAM Buffer Start Address */
762 /* RB_END 32 bit RAM Buffer End Address */
763 /* RB_WP 32 bit RAM Buffer Write Pointer */
764 /* RB_RP 32 bit RAM Buffer Read Pointer */
765 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
766 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
767 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
768 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
769 /* RB_PC 32 bit RAM Buffer Packet Counter */
770 /* RB_LEV 32 bit RAM Buffer Level Register */
771
772 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
773 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
774 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
775
776 /* RB_CTRL 8 bit RAM Buffer Control Register */
777 enum {
778 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
779 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
780 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
781 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
782 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
783 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
784 };
785
786
787 /* Transmit GMAC FIFO (YUKON only) */
788 enum {
789 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
790 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
791 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
792
793 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
794 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
795 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
796
797 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
798 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
799 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
800
801 /* Threshold values for Yukon-EC Ultra and Extreme */
802 ECU_AE_THR = 0x0070, /* Almost Empty Threshold */
803 ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */
804 ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */
805 };
806
807 /* Descriptor Poll Timer Registers */
808 enum {
809 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
810 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
811 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
812
813 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
814 };
815
816 /* Time Stamp Timer Registers (YUKON only) */
817 enum {
818 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
819 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
820 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
821 };
822
823 /* Polling Unit Registers (Yukon-2 only) */
824 enum {
825 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
826 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
827
828 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
829 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
830 };
831
832 enum {
833 SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */
834 SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */
835 };
836
837 enum {
838 CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */
839 CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */
840 CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */
841 CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */
842 CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */
843 CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */
844 HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */
845 CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */
846 HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */
847 HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */
848 };
849
850 /* ASF Subsystem Registers (Yukon-2 only) */
851 enum {
852 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
853 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
854 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
855
856 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
857 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
858 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
859 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
860 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
861 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
862 };
863
864 /* Status BMU Registers (Yukon-2 only)*/
865 enum {
866 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
867 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
868
869 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
870 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
871 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
872 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
873 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
874 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
875 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
876 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
877
878 /* FIFO Control/Status Registers (Yukon-2 only)*/
879 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
880 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
881 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
882 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
883 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
884 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
885 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
886
887 /* Level and ISR Timer Registers (Yukon-2 only)*/
888 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
889 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
890 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
891 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
892 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
893 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
894 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
895 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
896 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
897 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
898 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
899 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
900 };
901
902 enum {
903 LINKLED_OFF = 0x01,
904 LINKLED_ON = 0x02,
905 LINKLED_LINKSYNC_OFF = 0x04,
906 LINKLED_LINKSYNC_ON = 0x08,
907 LINKLED_BLINK_OFF = 0x10,
908 LINKLED_BLINK_ON = 0x20,
909 };
910
911 /* GMAC and GPHY Control Registers (YUKON only) */
912 enum {
913 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
914 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
915 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
916 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
917 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
918
919 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
920 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
921 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
922 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
923 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
924 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
925
926 /* WOL Pattern Length Registers (YUKON only) */
927 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
928 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
929
930 /* WOL Pattern Counter Registers (YUKON only) */
931 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
932 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
933 };
934 #define WOL_REGS(port, x) (x + (port)*0x80)
935
936 enum {
937 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
938 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
939 };
940 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
941
942 enum {
943 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
944 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
945 };
946
947 /*
948 * Marvel-PHY Registers, indirect addressed over GMAC
949 */
950 enum {
951 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
952 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
953 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
954 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
955 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
956 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
957 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
958 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
959 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
960 /* Marvel-specific registers */
961 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
962 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
963 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
964 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
965 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
966 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
967 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
968 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
969 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
970 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
971 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
972 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
973 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
974 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
975 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
976 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
977 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
978 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
979
980 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
981 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
982 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
983 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
984 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
985 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
986 };
987
988 enum {
989 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
990 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
991 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
992 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
993 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
994 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
995 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
996 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
997 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
998 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
999 };
1000
1001 enum {
1002 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1003 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1004 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1005 };
1006
1007 enum {
1008 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1009
1010 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1011 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1012 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
1013 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1014 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1015 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1016 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1017 };
1018
1019 enum {
1020 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1021 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1022 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1023 };
1024
1025 /* different Marvell PHY Ids */
1026 enum {
1027 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1028
1029 PHY_BCOM_ID1_A1 = 0x6041,
1030 PHY_BCOM_ID1_B2 = 0x6043,
1031 PHY_BCOM_ID1_C0 = 0x6044,
1032 PHY_BCOM_ID1_C5 = 0x6047,
1033
1034 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1035 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1036 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1037 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1038 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
1039 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
1040 };
1041
1042 /* Advertisement register bits */
1043 enum {
1044 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1045 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1046 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1047
1048 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1049 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1050 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1051 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1052 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1053 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1054 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1055 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1056 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1057 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1058 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1059 PHY_AN_100HALF | PHY_AN_100FULL,
1060 };
1061
1062 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1063 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1064 enum {
1065 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1066 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1067 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1068 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1069 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1070 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1071 /* Bit 9..8: reserved */
1072 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1073 };
1074
1075 /** Marvell-Specific */
1076 enum {
1077 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1078 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1079 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1080
1081 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1082 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1083 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1084 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1085 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1086 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1087 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1088 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1089 };
1090
1091 /* special defines for FIBER (88E1011S only) */
1092 enum {
1093 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1094 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1095 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1096 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1097 };
1098
1099 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1100 enum {
1101 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1102 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1103 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1104 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1105 };
1106
1107 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1108 enum {
1109 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1110 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1111 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1112 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1113 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1114 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1115 };
1116
1117 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1118 enum {
1119 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1120 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1121 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1122 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1123 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1124 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1125 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1126 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1127 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1128 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1129 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1130 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1131 };
1132
1133 enum {
1134 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1135 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1136 };
1137
1138 #define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
1139
1140 enum {
1141 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1142 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1143 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1144 };
1145
1146 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1147 enum {
1148 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1149 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1150 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1151 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1152 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1153
1154 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1155 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1156
1157 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1158 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1159 };
1160
1161 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1162 enum {
1163 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1164 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1165 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1166 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1167 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1168 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1169 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1170 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1171 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1172 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1173 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1174 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1175 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1176 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1177 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1178 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1179 };
1180
1181 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1182
1183 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1184 enum {
1185 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1186 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1187 };
1188
1189 enum {
1190 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1191 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1192 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1193 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1194 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1195 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1196 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1197 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1198 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1199 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1200 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1201 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1202
1203 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1204 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1205 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1206
1207 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1208 | PHY_M_IS_DUP_CHANGE,
1209 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1210 };
1211
1212
1213 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1214 enum {
1215 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1216 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1217
1218 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1219 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1220 /* (88E1011 only) */
1221 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1222 /* (88E1011 only) */
1223 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1224 /* (88E1111 only) */
1225 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1226 /* !!! Errata in spec. (1 = disable) */
1227 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1228 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1229 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1230 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1231 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1232 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1233
1234 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
1235 /* 00=1x; 01=2x; 10=3x; 11=4x */
1236 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
1237 /* 00=dis; 01=1x; 10=2x; 11=3x */
1238 #define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)
1239 /* 000=1x; 001=2x; 010=3x; 011=4x */
1240 #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)
1241 /* 01X=0; 110=2.5; 111=25 (MHz) */
1242
1243 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1244 enum {
1245 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1246 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1247 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1248 };
1249 /* !!! Errata in spec. (1 = disable) */
1250
1251 #define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK)
1252 /* 100=5x; 101=6x; 110=7x; 111=8x */
1253 enum {
1254 MAC_TX_CLK_0_MHZ = 2,
1255 MAC_TX_CLK_2_5_MHZ = 6,
1256 MAC_TX_CLK_25_MHZ = 7,
1257 };
1258
1259 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1260 enum {
1261 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1262 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1263 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1264 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1265 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1266 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1267 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1268 /* (88E1111 only) */
1269 };
1270
1271 enum {
1272 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1273 /* (88E1011 only) */
1274 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1275 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1276 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1277 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1278 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1279 };
1280
1281 #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1282
1283 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1284 enum {
1285 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1286 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1287 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1288 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1289 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1290 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1291 };
1292
1293 #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1294 #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1295 #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1296 #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1297 #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1298 #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1299
1300 enum {
1301 PULS_NO_STR = 0,/* no pulse stretching */
1302 PULS_21MS = 1,/* 21 ms to 42 ms */
1303 PULS_42MS = 2,/* 42 ms to 84 ms */
1304 PULS_84MS = 3,/* 84 ms to 170 ms */
1305 PULS_170MS = 4,/* 170 ms to 340 ms */
1306 PULS_340MS = 5,/* 340 ms to 670 ms */
1307 PULS_670MS = 6,/* 670 ms to 1.3 s */
1308 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1309 };
1310
1311 #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1312
1313 enum {
1314 BLINK_42MS = 0,/* 42 ms */
1315 BLINK_84MS = 1,/* 84 ms */
1316 BLINK_170MS = 2,/* 170 ms */
1317 BLINK_340MS = 3,/* 340 ms */
1318 BLINK_670MS = 4,/* 670 ms */
1319 };
1320
1321 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1322 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1323
1324 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1325 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1326 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1327 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1328 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1329 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1330
1331 enum led_mode {
1332 MO_LED_NORM = 0,
1333 MO_LED_BLINK = 1,
1334 MO_LED_OFF = 2,
1335 MO_LED_ON = 3,
1336 };
1337
1338 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1339 enum {
1340 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1341 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1342 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1343 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1344 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1345 };
1346
1347 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1348 enum {
1349 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1350 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1351 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1352 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1353 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1354 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1355 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1356 /* (88E1111 only) */
1357
1358 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1359 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1360 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1361 };
1362
1363 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1364 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1365 /* Bit 15..12: reserved (used internally) */
1366 enum {
1367 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1368 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1369 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1370 };
1371
1372 #define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)
1373 #define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)
1374 #define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)
1375
1376 enum {
1377 LED_PAR_CTRL_COLX = 0x00,
1378 LED_PAR_CTRL_ERROR = 0x01,
1379 LED_PAR_CTRL_DUPLEX = 0x02,
1380 LED_PAR_CTRL_DP_COL = 0x03,
1381 LED_PAR_CTRL_SPEED = 0x04,
1382 LED_PAR_CTRL_LINK = 0x05,
1383 LED_PAR_CTRL_TX = 0x06,
1384 LED_PAR_CTRL_RX = 0x07,
1385 LED_PAR_CTRL_ACT = 0x08,
1386 LED_PAR_CTRL_LNK_RX = 0x09,
1387 LED_PAR_CTRL_LNK_AC = 0x0a,
1388 LED_PAR_CTRL_ACT_BL = 0x0b,
1389 LED_PAR_CTRL_TX_BL = 0x0c,
1390 LED_PAR_CTRL_RX_BL = 0x0d,
1391 LED_PAR_CTRL_COL_BL = 0x0e,
1392 LED_PAR_CTRL_INACT = 0x0f
1393 };
1394
1395 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1396 enum {
1397 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1398 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1399 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1400 };
1401
1402 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1403 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1404 enum {
1405 PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */
1406 PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */
1407 PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */
1408 };
1409
1410 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1411 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1412 enum {
1413 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1414 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1415 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1416 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1417 };
1418 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1419
1420 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1421 enum {
1422 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1423 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1424 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1425 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1426 };
1427
1428 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1429 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1430 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1431 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1432
1433 /* GMAC registers */
1434 /* Port Registers */
1435 enum {
1436 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1437 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1438 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1439 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1440 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1441 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1442 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1443 /* Source Address Registers */
1444 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1445 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1446 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1447 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1448 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1449 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1450
1451 /* Multicast Address Hash Registers */
1452 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1453 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1454 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1455 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1456
1457 /* Interrupt Source Registers */
1458 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1459 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1460 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1461
1462 /* Interrupt Mask Registers */
1463 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1464 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1465 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1466
1467 /* Serial Management Interface (SMI) Registers */
1468 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1469 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1470 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1471 /* MIB Counters */
1472 GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */
1473 GM_MIB_CNT_END = 0x025C, /* Last MIB counter */
1474 };
1475
1476
1477 /*
1478 * MIB Counters base address definitions (low word) -
1479 * use offset 4 for access to high word (32 bit r/o)
1480 */
1481 enum {
1482 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1483 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1484 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1485 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1486 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1487
1488 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1489 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1490 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1491 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1492 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1493 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1494 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1495 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1496 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1497 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1498 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1499 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1500 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1501 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
1502 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
1503
1504 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
1505 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
1506 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
1507 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
1508 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
1509 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
1510 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
1511 GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
1512 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1513 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1514 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1515 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1516 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1517 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1518
1519 GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */
1520 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
1521 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
1522 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
1523 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
1524 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
1525 };
1526
1527 /* GMAC Bit Definitions */
1528 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1529 enum {
1530 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1531 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1532 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1533 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1534 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1535 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1536 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1537 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1538
1539 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1540 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1541 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1542 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1543 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1544 };
1545
1546 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1547 enum {
1548 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1549 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1550 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1551 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1552 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1553 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1554 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1555 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1556 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1557 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1558 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1559 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1560 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1561 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1562 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1563 };
1564
1565 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1566 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1567
1568 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1569 enum {
1570 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1571 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1572 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1573 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1574 };
1575
1576 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1577 #define TX_COL_DEF 0x04
1578
1579 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1580 enum {
1581 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1582 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1583 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1584 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1585 };
1586
1587 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1588 enum {
1589 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1590 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1591 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1592 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1593
1594 TX_JAM_LEN_DEF = 0x03,
1595 TX_JAM_IPG_DEF = 0x0b,
1596 TX_IPG_JAM_DEF = 0x1c,
1597 TX_BOF_LIM_DEF = 0x04,
1598 };
1599
1600 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1601 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1602 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1603 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1604
1605
1606 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1607 enum {
1608 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1609 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1610 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1611 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1612 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1613 };
1614
1615 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1616 #define DATA_BLIND_DEF 0x04
1617
1618 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1619 #define IPG_DATA_DEF 0x1e
1620
1621 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1622 enum {
1623 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1624 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1625 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1626 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1627 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1628 };
1629
1630 #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
1631 #define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)
1632
1633 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1634 enum {
1635 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1636 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1637 };
1638
1639 /* Receive Frame Status Encoding */
1640 enum {
1641 GMR_FS_LEN = 0x7fff<<16, /* Bit 30..16: Rx Frame Length */
1642 GMR_FS_VLAN = 1<<13, /* VLAN Packet */
1643 GMR_FS_JABBER = 1<<12, /* Jabber Packet */
1644 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
1645 GMR_FS_MC = 1<<10, /* Multicast Packet */
1646 GMR_FS_BC = 1<<9, /* Broadcast Packet */
1647 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
1648 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1649 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1650 GMR_FS_MII_ERR = 1<<5, /* MII Error */
1651 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
1652 GMR_FS_FRAGMENT = 1<<3, /* Fragment */
1653
1654 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
1655 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
1656
1657 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1658 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1659 GMR_FS_MII_ERR | GMR_FS_BAD_FC |
1660 GMR_FS_UN_SIZE | GMR_FS_JABBER,
1661 };
1662
1663 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1664 enum {
1665 RX_TRUNC_ON = 1<<27, /* enable packet truncation */
1666 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
1667 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
1668 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
1669
1670 RX_MACSEC_FLUSH_ON = 1<<23,
1671 RX_MACSEC_FLUSH_OFF = 1<<22,
1672 RX_MACSEC_ASF_FLUSH_ON = 1<<21,
1673 RX_MACSEC_ASF_FLUSH_OFF = 1<<20,
1674
1675 GMF_RX_OVER_ON = 1<<19, /* enable flushing on receive overrun */
1676 GMF_RX_OVER_OFF = 1<<18, /* disable flushing on receive overrun */
1677 GMF_ASF_RX_OVER_ON = 1<<17, /* enable flushing of ASF when overrun */
1678 GMF_ASF_RX_OVER_OFF = 1<<16, /* disable flushing of ASF when overrun */
1679
1680 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1681 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1682 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1683
1684 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1685 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1686 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1687 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1688 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1689 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1690 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
1691
1692 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1693 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1694 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1695 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1696
1697 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1698
1699 GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
1700 };
1701
1702 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1703 enum {
1704 TX_DYN_WM_ENA = 3, /* Yukon-FE+ specific */
1705 };
1706
1707 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1708 enum {
1709 TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
1710 TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
1711
1712 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
1713 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
1714
1715 TX_JUMBO_ENA = 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
1716 TX_JUMBO_DIS = 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
1717
1718 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1719 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1720 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1721
1722 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1723 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1724 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1725 };
1726
1727 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1728 enum {
1729 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1730 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1731 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1732 };
1733
1734 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1735 enum {
1736 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
1737 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
1738 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
1739 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
1740 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
1741
1742 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
1743 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
1744 };
1745
1746 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1747 enum {
1748 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1749 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1750 };
1751 /* HCU_CCSR CPU Control and Status Register */
1752 enum {
1753 HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */
1754 HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */
1755 /* Clock Stretching Timeout */
1756 HCU_CCSR_CS_TO = 1<<25,
1757 HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */
1758
1759 HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */
1760 HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */
1761
1762 HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */
1763 HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */
1764
1765 HCU_CCSR_SET_SYNC_CPU = 1<<5,
1766 HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
1767 HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3,
1768 HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */
1769 /* Microcontroller State */
1770 HCU_CCSR_UC_STATE_MSK = 3,
1771 HCU_CCSR_UC_STATE_BASE = 1<<0,
1772 HCU_CCSR_ASF_RESET = 0,
1773 HCU_CCSR_ASF_HALTED = 1<<1,
1774 HCU_CCSR_ASF_RUNNING = 1<<0,
1775 };
1776
1777 /* HCU_HCSR Host Control and Status Register */
1778 enum {
1779 HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */
1780
1781 HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */
1782 HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */
1783 };
1784
1785 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1786 enum {
1787 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
1788 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
1789 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
1790 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
1791 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
1792 };
1793
1794 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1795 enum {
1796 GMC_SET_RST = 1<<15,/* MAC SEC RST */
1797 GMC_SEC_RST_OFF = 1<<14,/* MAC SEC RSt OFF */
1798 GMC_BYP_MACSECRX_ON = 1<<13,/* Bypass macsec RX */
1799 GMC_BYP_MACSECRX_OFF= 1<<12,/* Bypass macsec RX off */
1800 GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */
1801 GMC_BYP_MACSECTX_OFF= 1<<10,/* Bypass macsec TX off*/
1802 GMC_BYP_RETR_ON = 1<<9, /* Bypass retransmit FIFO On */
1803 GMC_BYP_RETR_OFF= 1<<8, /* Bypass retransmit FIFO Off */
1804
1805 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1806 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1807 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1808 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1809 GMC_PAUSE_ON = 1<<3, /* Pause On */
1810 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1811 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1812 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1813 };
1814
1815 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1816 enum {
1817 GPC_TX_PAUSE = 1<<30, /* Tx pause enabled (ro) */
1818 GPC_RX_PAUSE = 1<<29, /* Rx pause enabled (ro) */
1819 GPC_SPEED = 3<<27, /* PHY speed (ro) */
1820 GPC_LINK = 1<<26, /* Link up (ro) */
1821 GPC_DUPLEX = 1<<25, /* Duplex (ro) */
1822 GPC_CLOCK = 1<<24, /* 125Mhz clock stable (ro) */
1823
1824 GPC_PDOWN = 1<<23, /* Internal regulator 2.5 power down */
1825 GPC_TSTMODE = 1<<22, /* Test mode */
1826 GPC_REG18 = 1<<21, /* Reg18 Power down */
1827 GPC_REG12SEL = 3<<19, /* Reg12 power setting */
1828 GPC_REG18SEL = 3<<17, /* Reg18 power setting */
1829 GPC_SPILOCK = 1<<16, /* SPI lock (ASF) */
1830
1831 GPC_LEDMUX = 3<<14, /* LED Mux */
1832 GPC_INTPOL = 1<<13, /* Interrupt polarity */
1833 GPC_DETECT = 1<<12, /* Energy detect */
1834 GPC_1000HD = 1<<11, /* Enable 1000Mbit HD */
1835 GPC_SLAVE = 1<<10, /* Slave mode */
1836 GPC_PAUSE = 1<<9, /* Pause enable */
1837 GPC_LEDCTL = 3<<6, /* GPHY Leds */
1838
1839 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1840 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1841 };
1842
1843 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1844 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1845 enum {
1846 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1847 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1848 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1849 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1850 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1851 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1852
1853 #define GMAC_DEF_MSK GM_IS_TX_FF_UR
1854 };
1855
1856 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1857 enum { /* Bits 15.. 2: reserved */
1858 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1859 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1860 };
1861
1862
1863 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1864 enum {
1865 WOL_CTL_LINK_CHG_OCC = 1<<15,
1866 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1867 WOL_CTL_PATTERN_OCC = 1<<13,
1868 WOL_CTL_CLEAR_RESULT = 1<<12,
1869 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1870 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1871 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1872 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1873 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1874 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1875 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1876 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1877 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1878 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1879 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1880 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1881 };
1882
1883
1884 /* Control flags */
1885 enum {
1886 UDPTCP = 1<<0,
1887 CALSUM = 1<<1,
1888 WR_SUM = 1<<2,
1889 INIT_SUM= 1<<3,
1890 LOCK_SUM= 1<<4,
1891 INS_VLAN= 1<<5,
1892 EOP = 1<<7,
1893 };
1894
1895 enum {
1896 HW_OWNER = 1<<7,
1897 OP_TCPWRITE = 0x11,
1898 OP_TCPSTART = 0x12,
1899 OP_TCPINIT = 0x14,
1900 OP_TCPLCK = 0x18,
1901 OP_TCPCHKSUM = OP_TCPSTART,
1902 OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
1903 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
1904 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
1905 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
1906
1907 OP_ADDR64 = 0x21,
1908 OP_VLAN = 0x22,
1909 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
1910 OP_LRGLEN = 0x24,
1911 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
1912 OP_MSS = 0x28,
1913 OP_MSSVLAN = OP_MSS | OP_VLAN,
1914
1915 OP_BUFFER = 0x40,
1916 OP_PACKET = 0x41,
1917 OP_LARGESEND = 0x43,
1918 OP_LSOV2 = 0x45,
1919
1920 /* YUKON-2 STATUS opcodes defines */
1921 OP_RXSTAT = 0x60,
1922 OP_RXTIMESTAMP = 0x61,
1923 OP_RXVLAN = 0x62,
1924 OP_RXCHKS = 0x64,
1925 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
1926 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
1927 OP_RSS_HASH = 0x65,
1928 OP_TXINDEXLE = 0x68,
1929 OP_MACSEC = 0x6c,
1930 OP_PUTIDX = 0x70,
1931 };
1932
1933 enum status_css {
1934 CSS_TCPUDPCSOK = 1<<7, /* TCP / UDP checksum is ok */
1935 CSS_ISUDP = 1<<6, /* packet is a UDP packet */
1936 CSS_ISTCP = 1<<5, /* packet is a TCP packet */
1937 CSS_ISIPFRAG = 1<<4, /* packet is a TCP/UDP frag, CS calc not done */
1938 CSS_ISIPV6 = 1<<3, /* packet is a IPv6 packet */
1939 CSS_IPV4CSUMOK = 1<<2, /* IP v4: TCP header checksum is ok */
1940 CSS_ISIPV4 = 1<<1, /* packet is a IPv4 packet */
1941 CSS_LINK_BIT = 1<<0, /* port number (legacy) */
1942 };
1943
1944 /* Yukon 2 hardware interface */
1945 struct sky2_tx_le {
1946 __le32 addr;
1947 __le16 length; /* also vlan tag or checksum start */
1948 u8 ctrl;
1949 u8 opcode;
1950 } __attribute((packed));
1951
1952 struct sky2_rx_le {
1953 __le32 addr;
1954 __le16 length;
1955 u8 ctrl;
1956 u8 opcode;
1957 } __attribute((packed));
1958
1959 struct sky2_status_le {
1960 __le32 status; /* also checksum */
1961 __le16 length; /* also vlan tag */
1962 u8 css;
1963 u8 opcode;
1964 } __attribute((packed));
1965
1966 struct tx_ring_info {
1967 struct sk_buff *skb;
1968 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1969 DECLARE_PCI_UNMAP_ADDR(maplen);
1970 };
1971
1972 struct rx_ring_info {
1973 struct sk_buff *skb;
1974 dma_addr_t data_addr;
1975 DECLARE_PCI_UNMAP_ADDR(data_size);
1976 dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT];
1977 };
1978
1979 enum flow_control {
1980 FC_NONE = 0,
1981 FC_TX = 1,
1982 FC_RX = 2,
1983 FC_BOTH = 3,
1984 };
1985
1986 struct sky2_port {
1987 struct sky2_hw *hw;
1988 struct net_device *netdev;
1989 unsigned port;
1990 u32 msg_enable;
1991 spinlock_t phy_lock;
1992
1993 struct tx_ring_info *tx_ring;
1994 struct sky2_tx_le *tx_le;
1995 u16 tx_cons; /* next le to check */
1996 u16 tx_prod; /* next le to use */
1997 u16 tx_next; /* debug only */
1998
1999 u16 tx_pending;
2000 u16 tx_last_mss;
2001 u32 tx_tcpsum;
2002
2003 struct rx_ring_info *rx_ring ____cacheline_aligned_in_smp;
2004 struct sky2_rx_le *rx_le;
2005
2006 u16 rx_next; /* next re to check */
2007 u16 rx_put; /* next le index to use */
2008 u16 rx_pending;
2009 u16 rx_data_size;
2010 u16 rx_nfrags;
2011
2012 #ifdef SKY2_VLAN_TAG_USED
2013 u16 rx_tag;
2014 struct vlan_group *vlgrp;
2015 #endif
2016 struct {
2017 unsigned long last;
2018 u32 mac_rp;
2019 u8 mac_lev;
2020 u8 fifo_rp;
2021 u8 fifo_lev;
2022 } check;
2023
2024
2025 dma_addr_t rx_le_map;
2026 dma_addr_t tx_le_map;
2027 u16 advertising; /* ADVERTISED_ bits */
2028 u16 speed; /* SPEED_1000, SPEED_100, ... */
2029 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2030 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2031 u8 rx_csum;
2032 u8 wol;
2033 enum flow_control flow_mode;
2034 enum flow_control flow_status;
2035
2036 #ifdef CONFIG_SKY2_DEBUG
2037 struct dentry *debugfs;
2038 #endif
2039 };
2040
2041 struct sky2_hw {
2042 void __iomem *regs;
2043 struct pci_dev *pdev;
2044 struct napi_struct napi;
2045 struct net_device *dev[2];
2046 unsigned long flags;
2047 #define SKY2_HW_USE_MSI 0x00000001
2048 #define SKY2_HW_FIBRE_PHY 0x00000002
2049 #define SKY2_HW_GIGABIT 0x00000004
2050 #define SKY2_HW_NEWER_PHY 0x00000008
2051 #define SKY2_HW_RAM_BUFFER 0x00000010
2052 #define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */
2053 #define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */
2054 #define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */
2055
2056 u8 chip_id;
2057 u8 chip_rev;
2058 u8 pmd_type;
2059 u8 ports;
2060
2061 struct sky2_status_le *st_le;
2062 u32 st_idx;
2063 dma_addr_t st_dma;
2064
2065 struct timer_list watchdog_timer;
2066 struct work_struct restart_work;
2067 wait_queue_head_t msi_wait;
2068 };
2069
2070 static inline int sky2_is_copper(const struct sky2_hw *hw)
2071 {
2072 return !(hw->flags & SKY2_HW_FIBRE_PHY);
2073 }
2074
2075 /* Register accessor for memory mapped device */
2076 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
2077 {
2078 return readl(hw->regs + reg);
2079 }
2080
2081 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
2082 {
2083 return readw(hw->regs + reg);
2084 }
2085
2086 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
2087 {
2088 return readb(hw->regs + reg);
2089 }
2090
2091 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
2092 {
2093 writel(val, hw->regs + reg);
2094 }
2095
2096 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
2097 {
2098 writew(val, hw->regs + reg);
2099 }
2100
2101 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
2102 {
2103 writeb(val, hw->regs + reg);
2104 }
2105
2106 /* Yukon PHY related registers */
2107 #define SK_GMAC_REG(port,reg) \
2108 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2109 #define GM_PHY_RETRIES 100
2110
2111 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
2112 {
2113 return sky2_read16(hw, SK_GMAC_REG(port,reg));
2114 }
2115
2116 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
2117 {
2118 unsigned base = SK_GMAC_REG(port, reg);
2119 return (u32) sky2_read16(hw, base)
2120 | (u32) sky2_read16(hw, base+4) << 16;
2121 }
2122
2123 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
2124 {
2125 sky2_write16(hw, SK_GMAC_REG(port,r), v);
2126 }
2127
2128 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
2129 const u8 *addr)
2130 {
2131 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2132 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2133 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2134 }
2135
2136 /* PCI config space access */
2137 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
2138 {
2139 return sky2_read32(hw, Y2_CFG_SPC + reg);
2140 }
2141
2142 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
2143 {
2144 return sky2_read16(hw, Y2_CFG_SPC + reg);
2145 }
2146
2147 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
2148 {
2149 sky2_write32(hw, Y2_CFG_SPC + reg, val);
2150 }
2151
2152 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
2153 {
2154 sky2_write16(hw, Y2_CFG_SPC + reg, val);
2155 }
2156 #endif
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