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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / net / netxen / netxen_nic_init.c
blob45fa33e0cb9062764dc542d3c9fd428dfa6cc17f
1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to initialize the Phantom Hardware
31 *
32 */
33
34 #include <linux/netdevice.h>
35 #include <linux/delay.h>
36 #include "netxen_nic.h"
37 #include "netxen_nic_hw.h"
38 #include "netxen_nic_phan_reg.h"
39
40 struct crb_addr_pair {
41 u32 addr;
42 u32 data;
43 };
44
45 unsigned long last_schedule_time;
46
47 #define NETXEN_MAX_CRB_XFORM 60
48 static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
49 #define NETXEN_ADDR_ERROR (0xffffffff)
50
51 #define crb_addr_transform(name) \
52 crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
53 NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
54
55 #define NETXEN_NIC_XDMA_RESET 0x8000ff
56
57 static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
58 uint32_t ctx, uint32_t ringid);
59
60 #if 0
61 static void netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
62 unsigned long off, int *data)
63 {
64 void __iomem *addr = pci_base_offset(adapter, off);
65 writel(*data, addr);
66 }
67 #endif /* 0 */
68
69 static void crb_addr_transform_setup(void)
70 {
71 crb_addr_transform(XDMA);
72 crb_addr_transform(TIMR);
73 crb_addr_transform(SRE);
74 crb_addr_transform(SQN3);
75 crb_addr_transform(SQN2);
76 crb_addr_transform(SQN1);
77 crb_addr_transform(SQN0);
78 crb_addr_transform(SQS3);
79 crb_addr_transform(SQS2);
80 crb_addr_transform(SQS1);
81 crb_addr_transform(SQS0);
82 crb_addr_transform(RPMX7);
83 crb_addr_transform(RPMX6);
84 crb_addr_transform(RPMX5);
85 crb_addr_transform(RPMX4);
86 crb_addr_transform(RPMX3);
87 crb_addr_transform(RPMX2);
88 crb_addr_transform(RPMX1);
89 crb_addr_transform(RPMX0);
90 crb_addr_transform(ROMUSB);
91 crb_addr_transform(SN);
92 crb_addr_transform(QMN);
93 crb_addr_transform(QMS);
94 crb_addr_transform(PGNI);
95 crb_addr_transform(PGND);
96 crb_addr_transform(PGN3);
97 crb_addr_transform(PGN2);
98 crb_addr_transform(PGN1);
99 crb_addr_transform(PGN0);
100 crb_addr_transform(PGSI);
101 crb_addr_transform(PGSD);
102 crb_addr_transform(PGS3);
103 crb_addr_transform(PGS2);
104 crb_addr_transform(PGS1);
105 crb_addr_transform(PGS0);
106 crb_addr_transform(PS);
107 crb_addr_transform(PH);
108 crb_addr_transform(NIU);
109 crb_addr_transform(I2Q);
110 crb_addr_transform(EG);
111 crb_addr_transform(MN);
112 crb_addr_transform(MS);
113 crb_addr_transform(CAS2);
114 crb_addr_transform(CAS1);
115 crb_addr_transform(CAS0);
116 crb_addr_transform(CAM);
117 crb_addr_transform(C2C1);
118 crb_addr_transform(C2C0);
119 crb_addr_transform(SMB);
120 }
121
122 int netxen_init_firmware(struct netxen_adapter *adapter)
123 {
124 u32 state = 0, loops = 0, err = 0;
125
126 /* Window 1 call */
127 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
128
129 if (state == PHAN_INITIALIZE_ACK)
130 return 0;
131
132 while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
133 udelay(100);
134 /* Window 1 call */
135 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
136
137 loops++;
138 }
139 if (loops >= 2000) {
140 printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
141 state);
142 err = -EIO;
143 return err;
144 }
145 /* Window 1 call */
146 writel(INTR_SCHEME_PERPORT,
147 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_HOST));
148 writel(MSI_MODE_MULTIFUNC,
149 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_HOST));
150 writel(MPORT_MULTI_FUNCTION_MODE,
151 NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE));
152 writel(PHAN_INITIALIZE_ACK,
153 NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
154
155 return err;
156 }
157
158 #define NETXEN_ADDR_LIMIT 0xffffffffULL
159
160 void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
161 struct pci_dev **used_dev)
162 {
163 void *addr;
164
165 addr = pci_alloc_consistent(pdev, sz, ptr);
166 if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) {
167 *used_dev = pdev;
168 return addr;
169 }
170 pci_free_consistent(pdev, sz, addr, *ptr);
171 addr = pci_alloc_consistent(NULL, sz, ptr);
172 *used_dev = NULL;
173 return addr;
174 }
175
176 void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
177 {
178 int ctxid, ring;
179 u32 i;
180 u32 num_rx_bufs = 0;
181 struct netxen_rcv_desc_ctx *rcv_desc;
182
183 DPRINTK(INFO, "initializing some queues: %p\n", adapter);
184 for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
185 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
186 struct netxen_rx_buffer *rx_buf;
187 rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring];
188 rcv_desc->begin_alloc = 0;
189 rx_buf = rcv_desc->rx_buf_arr;
190 num_rx_bufs = rcv_desc->max_rx_desc_count;
191 /*
192 * Now go through all of them, set reference handles
193 * and put them in the queues.
194 */
195 for (i = 0; i < num_rx_bufs; i++) {
196 rx_buf->ref_handle = i;
197 rx_buf->state = NETXEN_BUFFER_FREE;
198 DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
199 "%p\n", ctxid, i, rx_buf);
200 rx_buf++;
201 }
202 }
203 }
204 }
205
206 void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
207 {
208 int ports = 0;
209 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
210
211 if (netxen_nic_get_board_info(adapter) != 0)
212 printk("%s: Error getting board config info.\n",
213 netxen_nic_driver_name);
214 get_brd_port_by_type(board_info->board_type, &ports);
215 if (ports == 0)
216 printk(KERN_ERR "%s: Unknown board type\n",
217 netxen_nic_driver_name);
218 adapter->ahw.max_ports = ports;
219 }
220
221 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
222 {
223 switch (adapter->ahw.board_type) {
224 case NETXEN_NIC_GBE:
225 adapter->enable_phy_interrupts =
226 netxen_niu_gbe_enable_phy_interrupts;
227 adapter->disable_phy_interrupts =
228 netxen_niu_gbe_disable_phy_interrupts;
229 adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
230 adapter->macaddr_set = netxen_niu_macaddr_set;
231 adapter->set_mtu = netxen_nic_set_mtu_gb;
232 adapter->set_promisc = netxen_niu_set_promiscuous_mode;
233 adapter->unset_promisc = netxen_niu_set_promiscuous_mode;
234 adapter->phy_read = netxen_niu_gbe_phy_read;
235 adapter->phy_write = netxen_niu_gbe_phy_write;
236 adapter->init_niu = netxen_nic_init_niu_gb;
237 adapter->stop_port = netxen_niu_disable_gbe_port;
238 break;
239
240 case NETXEN_NIC_XGBE:
241 adapter->enable_phy_interrupts =
242 netxen_niu_xgbe_enable_phy_interrupts;
243 adapter->disable_phy_interrupts =
244 netxen_niu_xgbe_disable_phy_interrupts;
245 adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
246 adapter->macaddr_set = netxen_niu_xg_macaddr_set;
247 adapter->set_mtu = netxen_nic_set_mtu_xgb;
248 adapter->init_port = netxen_niu_xg_init_port;
249 adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
250 adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
251 adapter->stop_port = netxen_niu_disable_xg_port;
252 break;
253
254 default:
255 break;
256 }
257 }
258
259 /*
260 * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
261 * address to external PCI CRB address.
262 */
263 static u32 netxen_decode_crb_addr(u32 addr)
264 {
265 int i;
266 u32 base_addr, offset, pci_base;
267
268 crb_addr_transform_setup();
269
270 pci_base = NETXEN_ADDR_ERROR;
271 base_addr = addr & 0xfff00000;
272 offset = addr & 0x000fffff;
273
274 for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
275 if (crb_addr_xform[i] == base_addr) {
276 pci_base = i << 20;
277 break;
278 }
279 }
280 if (pci_base == NETXEN_ADDR_ERROR)
281 return pci_base;
282 else
283 return (pci_base + offset);
284 }
285
286 static long rom_max_timeout = 100;
287 static long rom_lock_timeout = 10000;
288 static long rom_write_timeout = 700;
289
290 static int rom_lock(struct netxen_adapter *adapter)
291 {
292 int iter;
293 u32 done = 0;
294 int timeout = 0;
295
296 while (!done) {
297 /* acquire semaphore2 from PCI HW block */
298 netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
299 &done);
300 if (done == 1)
301 break;
302 if (timeout >= rom_lock_timeout)
303 return -EIO;
304
305 timeout++;
306 /*
307 * Yield CPU
308 */
309 if (!in_atomic())
310 schedule();
311 else {
312 for (iter = 0; iter < 20; iter++)
313 cpu_relax(); /*This a nop instr on i386 */
314 }
315 }
316 netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
317 return 0;
318 }
319
320 static int netxen_wait_rom_done(struct netxen_adapter *adapter)
321 {
322 long timeout = 0;
323 long done = 0;
324
325 while (done == 0) {
326 done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
327 done &= 2;
328 timeout++;
329 if (timeout >= rom_max_timeout) {
330 printk("Timeout reached waiting for rom done");
331 return -EIO;
332 }
333 }
334 return 0;
335 }
336
337 static int netxen_rom_wren(struct netxen_adapter *adapter)
338 {
339 /* Set write enable latch in ROM status register */
340 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
341 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
342 M25P_INSTR_WREN);
343 if (netxen_wait_rom_done(adapter)) {
344 return -1;
345 }
346 return 0;
347 }
348
349 static unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
350 unsigned int addr)
351 {
352 unsigned int data = 0xdeaddead;
353 data = netxen_nic_reg_read(adapter, addr);
354 return data;
355 }
356
357 static int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
358 {
359 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
360 M25P_INSTR_RDSR);
361 if (netxen_wait_rom_done(adapter)) {
362 return -1;
363 }
364 return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
365 }
366
367 static void netxen_rom_unlock(struct netxen_adapter *adapter)
368 {
369 u32 val;
370
371 /* release semaphore2 */
372 netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
373
374 }
375
376 static int netxen_rom_wip_poll(struct netxen_adapter *adapter)
377 {
378 long timeout = 0;
379 long wip = 1;
380 int val;
381 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
382 while (wip != 0) {
383 val = netxen_do_rom_rdsr(adapter);
384 wip = val & 1;
385 timeout++;
386 if (timeout > rom_max_timeout) {
387 return -1;
388 }
389 }
390 return 0;
391 }
392
393 static int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
394 int data)
395 {
396 if (netxen_rom_wren(adapter)) {
397 return -1;
398 }
399 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
400 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
401 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
402 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
403 M25P_INSTR_PP);
404 if (netxen_wait_rom_done(adapter)) {
405 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
406 return -1;
407 }
408
409 return netxen_rom_wip_poll(adapter);
410 }
411
412 static int do_rom_fast_read(struct netxen_adapter *adapter,
413 int addr, int *valp)
414 {
415 cond_resched();
416
417 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
418 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
419 udelay(100); /* prevent bursting on CRB */
420 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
421 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
422 if (netxen_wait_rom_done(adapter)) {
423 printk("Error waiting for rom done\n");
424 return -EIO;
425 }
426 /* reset abyte_cnt and dummy_byte_cnt */
427 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
428 udelay(100); /* prevent bursting on CRB */
429 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
430
431 *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
432 return 0;
433 }
434
435 static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
436 u8 *bytes, size_t size)
437 {
438 int addridx;
439 int ret = 0;
440
441 for (addridx = addr; addridx < (addr + size); addridx += 4) {
442 int v;
443 ret = do_rom_fast_read(adapter, addridx, &v);
444 if (ret != 0)
445 break;
446 *(__le32 *)bytes = cpu_to_le32(v);
447 bytes += 4;
448 }
449
450 return ret;
451 }
452
453 int
454 netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
455 u8 *bytes, size_t size)
456 {
457 int ret;
458
459 ret = rom_lock(adapter);
460 if (ret < 0)
461 return ret;
462
463 ret = do_rom_fast_read_words(adapter, addr, bytes, size);
464
465 netxen_rom_unlock(adapter);
466 return ret;
467 }
468
469 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
470 {
471 int ret;
472
473 if (rom_lock(adapter) != 0)
474 return -EIO;
475
476 ret = do_rom_fast_read(adapter, addr, valp);
477 netxen_rom_unlock(adapter);
478 return ret;
479 }
480
481 #if 0
482 int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
483 {
484 int ret = 0;
485
486 if (rom_lock(adapter) != 0) {
487 return -1;
488 }
489 ret = do_rom_fast_write(adapter, addr, data);
490 netxen_rom_unlock(adapter);
491 return ret;
492 }
493 #endif /* 0 */
494
495 static int do_rom_fast_write_words(struct netxen_adapter *adapter,
496 int addr, u8 *bytes, size_t size)
497 {
498 int addridx = addr;
499 int ret = 0;
500
501 while (addridx < (addr + size)) {
502 int last_attempt = 0;
503 int timeout = 0;
504 int data;
505
506 data = le32_to_cpu((*(__le32*)bytes));
507 ret = do_rom_fast_write(adapter, addridx, data);
508 if (ret < 0)
509 return ret;
510
511 while(1) {
512 int data1;
513
514 ret = do_rom_fast_read(adapter, addridx, &data1);
515 if (ret < 0)
516 return ret;
517
518 if (data1 == data)
519 break;
520
521 if (timeout++ >= rom_write_timeout) {
522 if (last_attempt++ < 4) {
523 ret = do_rom_fast_write(adapter,
524 addridx, data);
525 if (ret < 0)
526 return ret;
527 }
528 else {
529 printk(KERN_INFO "Data write did not "
530 "succeed at address 0x%x\n", addridx);
531 break;
532 }
533 }
534 }
535
536 bytes += 4;
537 addridx += 4;
538 }
539
540 return ret;
541 }
542
543 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
544 u8 *bytes, size_t size)
545 {
546 int ret = 0;
547
548 ret = rom_lock(adapter);
549 if (ret < 0)
550 return ret;
551
552 ret = do_rom_fast_write_words(adapter, addr, bytes, size);
553 netxen_rom_unlock(adapter);
554
555 return ret;
556 }
557
558 static int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
559 {
560 int ret;
561
562 ret = netxen_rom_wren(adapter);
563 if (ret < 0)
564 return ret;
565
566 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
567 netxen_crb_writelit_adapter(adapter,
568 NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
569
570 ret = netxen_wait_rom_done(adapter);
571 if (ret < 0)
572 return ret;
573
574 return netxen_rom_wip_poll(adapter);
575 }
576
577 static int netxen_rom_rdsr(struct netxen_adapter *adapter)
578 {
579 int ret;
580
581 ret = rom_lock(adapter);
582 if (ret < 0)
583 return ret;
584
585 ret = netxen_do_rom_rdsr(adapter);
586 netxen_rom_unlock(adapter);
587 return ret;
588 }
589
590 int netxen_backup_crbinit(struct netxen_adapter *adapter)
591 {
592 int ret = FLASH_SUCCESS;
593 int val;
594 char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL);
595
596 if (!buffer)
597 return -ENOMEM;
598 /* unlock sector 63 */
599 val = netxen_rom_rdsr(adapter);
600 val = val & 0xe3;
601 ret = netxen_rom_wrsr(adapter, val);
602 if (ret != FLASH_SUCCESS)
603 goto out_kfree;
604
605 ret = netxen_rom_wip_poll(adapter);
606 if (ret != FLASH_SUCCESS)
607 goto out_kfree;
608
609 /* copy sector 0 to sector 63 */
610 ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START,
611 buffer, NETXEN_FLASH_SECTOR_SIZE);
612 if (ret != FLASH_SUCCESS)
613 goto out_kfree;
614
615 ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START,
616 buffer, NETXEN_FLASH_SECTOR_SIZE);
617 if (ret != FLASH_SUCCESS)
618 goto out_kfree;
619
620 /* lock sector 63 */
621 val = netxen_rom_rdsr(adapter);
622 if (!(val & 0x8)) {
623 val |= (0x1 << 2);
624 /* lock sector 63 */
625 if (netxen_rom_wrsr(adapter, val) == 0) {
626 ret = netxen_rom_wip_poll(adapter);
627 if (ret != FLASH_SUCCESS)
628 goto out_kfree;
629
630 /* lock SR writes */
631 ret = netxen_rom_wip_poll(adapter);
632 if (ret != FLASH_SUCCESS)
633 goto out_kfree;
634 }
635 }
636
637 out_kfree:
638 kfree(buffer);
639 return ret;
640 }
641
642 static int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
643 {
644 netxen_rom_wren(adapter);
645 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
646 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
647 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
648 M25P_INSTR_SE);
649 if (netxen_wait_rom_done(adapter)) {
650 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
651 return -1;
652 }
653 return netxen_rom_wip_poll(adapter);
654 }
655
656 static void check_erased_flash(struct netxen_adapter *adapter, int addr)
657 {
658 int i;
659 int val;
660 int count = 0, erased_errors = 0;
661 int range;
662
663 range = (addr == NETXEN_USER_START) ?
664 NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE;
665
666 for (i = addr; i < range; i += 4) {
667 netxen_rom_fast_read(adapter, i, &val);
668 if (val != 0xffffffff)
669 erased_errors++;
670 count++;
671 }
672
673 if (erased_errors)
674 printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
675 "for sector address: %x\n", erased_errors, count, addr);
676 }
677
678 int netxen_rom_se(struct netxen_adapter *adapter, int addr)
679 {
680 int ret = 0;
681 if (rom_lock(adapter) != 0) {
682 return -1;
683 }
684 ret = netxen_do_rom_se(adapter, addr);
685 netxen_rom_unlock(adapter);
686 msleep(30);
687 check_erased_flash(adapter, addr);
688
689 return ret;
690 }
691
692 static int netxen_flash_erase_sections(struct netxen_adapter *adapter,
693 int start, int end)
694 {
695 int ret = FLASH_SUCCESS;
696 int i;
697
698 for (i = start; i < end; i++) {
699 ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE);
700 if (ret)
701 break;
702 ret = netxen_rom_wip_poll(adapter);
703 if (ret < 0)
704 return ret;
705 }
706
707 return ret;
708 }
709
710 int
711 netxen_flash_erase_secondary(struct netxen_adapter *adapter)
712 {
713 int ret = FLASH_SUCCESS;
714 int start, end;
715
716 start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
717 end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE;
718 ret = netxen_flash_erase_sections(adapter, start, end);
719
720 return ret;
721 }
722
723 int
724 netxen_flash_erase_primary(struct netxen_adapter *adapter)
725 {
726 int ret = FLASH_SUCCESS;
727 int start, end;
728
729 start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE;
730 end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
731 ret = netxen_flash_erase_sections(adapter, start, end);
732
733 return ret;
734 }
735
736 void netxen_halt_pegs(struct netxen_adapter *adapter)
737 {
738 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
739 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
740 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
741 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
742 }
743
744 int netxen_flash_unlock(struct netxen_adapter *adapter)
745 {
746 int ret = 0;
747
748 ret = netxen_rom_wrsr(adapter, 0);
749 if (ret < 0)
750 return ret;
751
752 ret = netxen_rom_wren(adapter);
753 if (ret < 0)
754 return ret;
755
756 return ret;
757 }
758
759 #define NETXEN_BOARDTYPE 0x4008
760 #define NETXEN_BOARDNUM 0x400c
761 #define NETXEN_CHIPNUM 0x4010
762 #define NETXEN_ROMBUS_RESET 0xFFFFFFFF
763 #define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL
764 #define NETXEN_ROM_FOUND_INIT 0x400
765
766 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
767 {
768 int addr, val, status;
769 int n, i;
770 int init_delay = 0;
771 struct crb_addr_pair *buf;
772 u32 off;
773
774 /* resetall */
775 status = netxen_nic_get_board_info(adapter);
776 if (status)
777 printk("%s: netxen_pinit_from_rom: Error getting board info\n",
778 netxen_nic_driver_name);
779
780 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
781 NETXEN_ROMBUS_RESET);
782
783 if (verbose) {
784 int val;
785 if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
786 printk("P2 ROM board type: 0x%08x\n", val);
787 else
788 printk("Could not read board type\n");
789 if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
790 printk("P2 ROM board num: 0x%08x\n", val);
791 else
792 printk("Could not read board number\n");
793 if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
794 printk("P2 ROM chip num: 0x%08x\n", val);
795 else
796 printk("Could not read chip number\n");
797 }
798
799 if (netxen_rom_fast_read(adapter, 0, &n) == 0
800 && (n & NETXEN_ROM_FIRST_BARRIER)) {
801 n &= ~NETXEN_ROM_ROUNDUP;
802 if (n < NETXEN_ROM_FOUND_INIT) {
803 if (verbose)
804 printk("%s: %d CRB init values found"
805 " in ROM.\n", netxen_nic_driver_name, n);
806 } else {
807 printk("%s:n=0x%x Error! NetXen card flash not"
808 " initialized.\n", __FUNCTION__, n);
809 return -EIO;
810 }
811 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
812 if (buf == NULL) {
813 printk("%s: netxen_pinit_from_rom: Unable to calloc "
814 "memory.\n", netxen_nic_driver_name);
815 return -ENOMEM;
816 }
817 for (i = 0; i < n; i++) {
818 if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0
819 || netxen_rom_fast_read(adapter, 8 * i + 8,
820 &addr) != 0)
821 return -EIO;
822
823 buf[i].addr = addr;
824 buf[i].data = val;
825
826 if (verbose)
827 printk("%s: PCI: 0x%08x == 0x%08x\n",
828 netxen_nic_driver_name, (unsigned int)
829 netxen_decode_crb_addr(addr), val);
830 }
831 for (i = 0; i < n; i++) {
832
833 off = netxen_decode_crb_addr(buf[i].addr);
834 if (off == NETXEN_ADDR_ERROR) {
835 printk(KERN_ERR"CRB init value out of range %x\n",
836 buf[i].addr);
837 continue;
838 }
839 off += NETXEN_PCI_CRBSPACE;
840 /* skipping cold reboot MAGIC */
841 if (off == NETXEN_CAM_RAM(0x1fc))
842 continue;
843
844 /* After writing this register, HW needs time for CRB */
845 /* to quiet down (else crb_window returns 0xffffffff) */
846 if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
847 init_delay = 1;
848 /* hold xdma in reset also */
849 buf[i].data = NETXEN_NIC_XDMA_RESET;
850 }
851
852 if (ADDR_IN_WINDOW1(off)) {
853 writel(buf[i].data,
854 NETXEN_CRB_NORMALIZE(adapter, off));
855 } else {
856 netxen_nic_pci_change_crbwindow(adapter, 0);
857 writel(buf[i].data,
858 pci_base_offset(adapter, off));
859
860 netxen_nic_pci_change_crbwindow(adapter, 1);
861 }
862 if (init_delay == 1) {
863 msleep(2000);
864 init_delay = 0;
865 }
866 msleep(20);
867 }
868 kfree(buf);
869
870 /* disable_peg_cache_all */
871
872 /* unreset_net_cache */
873 netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
874 4);
875 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
876 (val & 0xffffff0f));
877 /* p2dn replyCount */
878 netxen_crb_writelit_adapter(adapter,
879 NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
880 /* disable_peg_cache 0 */
881 netxen_crb_writelit_adapter(adapter,
882 NETXEN_CRB_PEG_NET_D + 0x4c, 8);
883 /* disable_peg_cache 1 */
884 netxen_crb_writelit_adapter(adapter,
885 NETXEN_CRB_PEG_NET_I + 0x4c, 8);
886
887 /* peg_clr_all */
888
889 /* peg_clr 0 */
890 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8,
891 0);
892 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc,
893 0);
894 /* peg_clr 1 */
895 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8,
896 0);
897 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc,
898 0);
899 /* peg_clr 2 */
900 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8,
901 0);
902 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc,
903 0);
904 /* peg_clr 3 */
905 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8,
906 0);
907 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc,
908 0);
909 }
910 return 0;
911 }
912
913 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
914 {
915 uint64_t addr;
916 uint32_t hi;
917 uint32_t lo;
918
919 adapter->dummy_dma.addr =
920 pci_alloc_consistent(adapter->ahw.pdev,
921 NETXEN_HOST_DUMMY_DMA_SIZE,
922 &adapter->dummy_dma.phys_addr);
923 if (adapter->dummy_dma.addr == NULL) {
924 printk("%s: ERROR: Could not allocate dummy DMA memory\n",
925 __FUNCTION__);
926 return -ENOMEM;
927 }
928
929 addr = (uint64_t) adapter->dummy_dma.phys_addr;
930 hi = (addr >> 32) & 0xffffffff;
931 lo = addr & 0xffffffff;
932
933 writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI));
934 writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO));
935
936 return 0;
937 }
938
939 void netxen_free_adapter_offload(struct netxen_adapter *adapter)
940 {
941 if (adapter->dummy_dma.addr) {
942 pci_free_consistent(adapter->ahw.pdev,
943 NETXEN_HOST_DUMMY_DMA_SIZE,
944 adapter->dummy_dma.addr,
945 adapter->dummy_dma.phys_addr);
946 adapter->dummy_dma.addr = NULL;
947 }
948 }
949
950 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
951 {
952 u32 val = 0;
953 int retries = 30;
954
955 if (!pegtune_val) {
956 do {
957 val = readl(NETXEN_CRB_NORMALIZE
958 (adapter, CRB_CMDPEG_STATE));
959 pegtune_val = readl(NETXEN_CRB_NORMALIZE
960 (adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE));
961
962 if (val == PHAN_INITIALIZE_COMPLETE ||
963 val == PHAN_INITIALIZE_ACK)
964 return 0;
965
966 msleep(1000);
967 } while (--retries);
968 if (!retries) {
969 printk(KERN_WARNING "netxen_phantom_init: init failed, "
970 "pegtune_val=%x\n", pegtune_val);
971 return -1;
972 }
973 }
974
975 return 0;
976 }
977
978 static int netxen_nic_check_temp(struct netxen_adapter *adapter)
979 {
980 struct net_device *netdev = adapter->netdev;
981 uint32_t temp, temp_state, temp_val;
982 int rv = 0;
983
984 temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE));
985
986 temp_state = nx_get_temp_state(temp);
987 temp_val = nx_get_temp_val(temp);
988
989 if (temp_state == NX_TEMP_PANIC) {
990 printk(KERN_ALERT
991 "%s: Device temperature %d degrees C exceeds"
992 " maximum allowed. Hardware has been shut down.\n",
993 netxen_nic_driver_name, temp_val);
994
995 netif_carrier_off(netdev);
996 netif_stop_queue(netdev);
997 rv = 1;
998 } else if (temp_state == NX_TEMP_WARN) {
999 if (adapter->temp == NX_TEMP_NORMAL) {
1000 printk(KERN_ALERT
1001 "%s: Device temperature %d degrees C "
1002 "exceeds operating range."
1003 " Immediate action needed.\n",
1004 netxen_nic_driver_name, temp_val);
1005 }
1006 } else {
1007 if (adapter->temp == NX_TEMP_WARN) {
1008 printk(KERN_INFO
1009 "%s: Device temperature is now %d degrees C"
1010 " in normal range.\n", netxen_nic_driver_name,
1011 temp_val);
1012 }
1013 }
1014 adapter->temp = temp_state;
1015 return rv;
1016 }
1017
1018 void netxen_watchdog_task(struct work_struct *work)
1019 {
1020 struct netxen_adapter *adapter =
1021 container_of(work, struct netxen_adapter, watchdog_task);
1022
1023 if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter))
1024 return;
1025
1026 if (adapter->handle_phy_intr)
1027 adapter->handle_phy_intr(adapter);
1028
1029 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
1030 }
1031
1032 /*
1033 * netxen_process_rcv() send the received packet to the protocol stack.
1034 * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
1035 * invoke the routine to send more rx buffers to the Phantom...
1036 */
1037 static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
1038 struct status_desc *desc)
1039 {
1040 struct pci_dev *pdev = adapter->pdev;
1041 struct net_device *netdev = adapter->netdev;
1042 u64 sts_data = le64_to_cpu(desc->status_desc_data);
1043 int index = netxen_get_sts_refhandle(sts_data);
1044 struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
1045 struct netxen_rx_buffer *buffer;
1046 struct sk_buff *skb;
1047 u32 length = netxen_get_sts_totallength(sts_data);
1048 u32 desc_ctx;
1049 struct netxen_rcv_desc_ctx *rcv_desc;
1050 int ret;
1051
1052 desc_ctx = netxen_get_sts_type(sts_data);
1053 if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
1054 printk("%s: %s Bad Rcv descriptor ring\n",
1055 netxen_nic_driver_name, netdev->name);
1056 return;
1057 }
1058
1059 rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
1060 if (unlikely(index > rcv_desc->max_rx_desc_count)) {
1061 DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
1062 index, rcv_desc->max_rx_desc_count);
1063 return;
1064 }
1065 buffer = &rcv_desc->rx_buf_arr[index];
1066 if (desc_ctx == RCV_DESC_LRO_CTXID) {
1067 buffer->lro_current_frags++;
1068 if (netxen_get_sts_desc_lro_last_frag(desc)) {
1069 buffer->lro_expected_frags =
1070 netxen_get_sts_desc_lro_cnt(desc);
1071 buffer->lro_length = length;
1072 }
1073 if (buffer->lro_current_frags != buffer->lro_expected_frags) {
1074 if (buffer->lro_expected_frags != 0) {
1075 printk("LRO: (refhandle:%x) recv frag. "
1076 "wait for last. flags: %x expected:%d "
1077 "have:%d\n", index,
1078 netxen_get_sts_desc_lro_last_frag(desc),
1079 buffer->lro_expected_frags,
1080 buffer->lro_current_frags);
1081 }
1082 return;
1083 }
1084 }
1085
1086 pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
1087 PCI_DMA_FROMDEVICE);
1088
1089 skb = (struct sk_buff *)buffer->skb;
1090
1091 if (likely(adapter->rx_csum &&
1092 netxen_get_sts_status(sts_data) == STATUS_CKSUM_OK)) {
1093 adapter->stats.csummed++;
1094 skb->ip_summed = CHECKSUM_UNNECESSARY;
1095 } else
1096 skb->ip_summed = CHECKSUM_NONE;
1097
1098 skb->dev = netdev;
1099 if (desc_ctx == RCV_DESC_LRO_CTXID) {
1100 /* True length was only available on the last pkt */
1101 skb_put(skb, buffer->lro_length);
1102 } else {
1103 skb_put(skb, length);
1104 }
1105
1106 skb->protocol = eth_type_trans(skb, netdev);
1107
1108 ret = netif_receive_skb(skb);
1109 netdev->last_rx = jiffies;
1110
1111 rcv_desc->rcv_pending--;
1112
1113 /*
1114 * We just consumed one buffer so post a buffer.
1115 */
1116 buffer->skb = NULL;
1117 buffer->state = NETXEN_BUFFER_FREE;
1118 buffer->lro_current_frags = 0;
1119 buffer->lro_expected_frags = 0;
1120
1121 adapter->stats.no_rcv++;
1122 adapter->stats.rxbytes += length;
1123 }
1124
1125 /* Process Receive status ring */
1126 u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
1127 {
1128 struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
1129 struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
1130 struct status_desc *desc; /* used to read status desc here */
1131 u32 consumer = recv_ctx->status_rx_consumer;
1132 u32 producer = 0;
1133 int count = 0, ring;
1134
1135 while (count < max) {
1136 desc = &desc_head[consumer];
1137 if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
1138 DPRINTK(ERR, "desc %p ownedby %x\n", desc,
1139 netxen_get_sts_owner(desc));
1140 break;
1141 }
1142 netxen_process_rcv(adapter, ctxid, desc);
1143 netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
1144 consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
1145 count++;
1146 }
1147 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++)
1148 netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
1149
1150 /* update the consumer index in phantom */
1151 if (count) {
1152 recv_ctx->status_rx_consumer = consumer;
1153 recv_ctx->status_rx_producer = producer;
1154
1155 /* Window = 1 */
1156 writel(consumer,
1157 NETXEN_CRB_NORMALIZE(adapter,
1158 recv_crb_registers[adapter->portnum].
1159 crb_rcv_status_consumer));
1160 }
1161
1162 return count;
1163 }
1164
1165 /* Process Command status ring */
1166 int netxen_process_cmd_ring(struct netxen_adapter *adapter)
1167 {
1168 u32 last_consumer, consumer;
1169 int count = 0, i;
1170 struct netxen_cmd_buffer *buffer;
1171 struct pci_dev *pdev = adapter->pdev;
1172 struct net_device *netdev = adapter->netdev;
1173 struct netxen_skb_frag *frag;
1174 int done = 0;
1175
1176 last_consumer = adapter->last_cmd_consumer;
1177 consumer = le32_to_cpu(*(adapter->cmd_consumer));
1178
1179 while (last_consumer != consumer) {
1180 buffer = &adapter->cmd_buf_arr[last_consumer];
1181 if (buffer->skb) {
1182 frag = &buffer->frag_array[0];
1183 pci_unmap_single(pdev, frag->dma, frag->length,
1184 PCI_DMA_TODEVICE);
1185 frag->dma = 0ULL;
1186 for (i = 1; i < buffer->frag_count; i++) {
1187 frag++; /* Get the next frag */
1188 pci_unmap_page(pdev, frag->dma, frag->length,
1189 PCI_DMA_TODEVICE);
1190 frag->dma = 0ULL;
1191 }
1192
1193 adapter->stats.xmitfinished++;
1194 dev_kfree_skb_any(buffer->skb);
1195 buffer->skb = NULL;
1196 }
1197
1198 last_consumer = get_next_index(last_consumer,
1199 adapter->max_tx_desc_count);
1200 if (++count >= MAX_STATUS_HANDLE)
1201 break;
1202 }
1203
1204 if (count) {
1205 adapter->last_cmd_consumer = last_consumer;
1206 smp_mb();
1207 if (netif_queue_stopped(netdev) && netif_running(netdev)) {
1208 netif_tx_lock(netdev);
1209 netif_wake_queue(netdev);
1210 smp_mb();
1211 netif_tx_unlock(netdev);
1212 }
1213 }
1214 /*
1215 * If everything is freed up to consumer then check if the ring is full
1216 * If the ring is full then check if more needs to be freed and
1217 * schedule the call back again.
1218 *
1219 * This happens when there are 2 CPUs. One could be freeing and the
1220 * other filling it. If the ring is full when we get out of here and
1221 * the card has already interrupted the host then the host can miss the
1222 * interrupt.
1223 *
1224 * There is still a possible race condition and the host could miss an
1225 * interrupt. The card has to take care of this.
1226 */
1227 consumer = le32_to_cpu(*(adapter->cmd_consumer));
1228 done = (last_consumer == consumer);
1229
1230 return (done);
1231 }
1232
1233 /*
1234 * netxen_post_rx_buffers puts buffer in the Phantom memory
1235 */
1236 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
1237 {
1238 struct pci_dev *pdev = adapter->ahw.pdev;
1239 struct sk_buff *skb;
1240 struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
1241 struct netxen_rcv_desc_ctx *rcv_desc = NULL;
1242 uint producer;
1243 struct rcv_desc *pdesc;
1244 struct netxen_rx_buffer *buffer;
1245 int count = 0;
1246 int index = 0;
1247 netxen_ctx_msg msg = 0;
1248 dma_addr_t dma;
1249
1250 rcv_desc = &recv_ctx->rcv_desc[ringid];
1251
1252 producer = rcv_desc->producer;
1253 index = rcv_desc->begin_alloc;
1254 buffer = &rcv_desc->rx_buf_arr[index];
1255 /* We can start writing rx descriptors into the phantom memory. */
1256 while (buffer->state == NETXEN_BUFFER_FREE) {
1257 skb = dev_alloc_skb(rcv_desc->skb_size);
1258 if (unlikely(!skb)) {
1259 /*
1260 * TODO
1261 * We need to schedule the posting of buffers to the pegs.
1262 */
1263 rcv_desc->begin_alloc = index;
1264 DPRINTK(ERR, "netxen_post_rx_buffers: "
1265 " allocated only %d buffers\n", count);
1266 break;
1267 }
1268
1269 count++; /* now there should be no failure */
1270 pdesc = &rcv_desc->desc_head[producer];
1271
1272 #if defined(XGB_DEBUG)
1273 *(unsigned long *)(skb->head) = 0xc0debabe;
1274 if (skb_is_nonlinear(skb)) {
1275 printk("Allocated SKB @%p is nonlinear\n");
1276 }
1277 #endif
1278 skb_reserve(skb, 2);
1279 /* This will be setup when we receive the
1280 * buffer after it has been filled FSL TBD TBD
1281 * skb->dev = netdev;
1282 */
1283 dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
1284 PCI_DMA_FROMDEVICE);
1285 pdesc->addr_buffer = cpu_to_le64(dma);
1286 buffer->skb = skb;
1287 buffer->state = NETXEN_BUFFER_BUSY;
1288 buffer->dma = dma;
1289 /* make a rcv descriptor */
1290 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
1291 pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
1292 DPRINTK(INFO, "done writing descripter\n");
1293 producer =
1294 get_next_index(producer, rcv_desc->max_rx_desc_count);
1295 index = get_next_index(index, rcv_desc->max_rx_desc_count);
1296 buffer = &rcv_desc->rx_buf_arr[index];
1297 }
1298 /* if we did allocate buffers, then write the count to Phantom */
1299 if (count) {
1300 rcv_desc->begin_alloc = index;
1301 rcv_desc->rcv_pending += count;
1302 rcv_desc->producer = producer;
1303 /* Window = 1 */
1304 writel((producer - 1) &
1305 (rcv_desc->max_rx_desc_count - 1),
1306 NETXEN_CRB_NORMALIZE(adapter,
1307 recv_crb_registers[
1308 adapter->portnum].
1309 rcv_desc_crb[ringid].
1310 crb_rcv_producer_offset));
1311 /*
1312 * Write a doorbell msg to tell phanmon of change in
1313 * receive ring producer
1314 */
1315 netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
1316 netxen_set_msg_privid(msg);
1317 netxen_set_msg_count(msg,
1318 ((producer -
1319 1) & (rcv_desc->
1320 max_rx_desc_count - 1)));
1321 netxen_set_msg_ctxid(msg, adapter->portnum);
1322 netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
1323 writel(msg,
1324 DB_NORMALIZE(adapter,
1325 NETXEN_RCV_PRODUCER_OFFSET));
1326 }
1327 }
1328
1329 static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1330 uint32_t ctx, uint32_t ringid)
1331 {
1332 struct pci_dev *pdev = adapter->ahw.pdev;
1333 struct sk_buff *skb;
1334 struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
1335 struct netxen_rcv_desc_ctx *rcv_desc = NULL;
1336 u32 producer;
1337 struct rcv_desc *pdesc;
1338 struct netxen_rx_buffer *buffer;
1339 int count = 0;
1340 int index = 0;
1341
1342 rcv_desc = &recv_ctx->rcv_desc[ringid];
1343
1344 producer = rcv_desc->producer;
1345 index = rcv_desc->begin_alloc;
1346 buffer = &rcv_desc->rx_buf_arr[index];
1347 /* We can start writing rx descriptors into the phantom memory. */
1348 while (buffer->state == NETXEN_BUFFER_FREE) {
1349 skb = dev_alloc_skb(rcv_desc->skb_size);
1350 if (unlikely(!skb)) {
1351 /*
1352 * We need to schedule the posting of buffers to the pegs.
1353 */
1354 rcv_desc->begin_alloc = index;
1355 DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
1356 " allocated only %d buffers\n", count);
1357 break;
1358 }
1359 count++; /* now there should be no failure */
1360 pdesc = &rcv_desc->desc_head[producer];
1361 skb_reserve(skb, 2);
1362 /*
1363 * This will be setup when we receive the
1364 * buffer after it has been filled
1365 * skb->dev = netdev;
1366 */
1367 buffer->skb = skb;
1368 buffer->state = NETXEN_BUFFER_BUSY;
1369 buffer->dma = pci_map_single(pdev, skb->data,
1370 rcv_desc->dma_size,
1371 PCI_DMA_FROMDEVICE);
1372
1373 /* make a rcv descriptor */
1374 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
1375 pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
1376 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
1377 DPRINTK(INFO, "done writing descripter\n");
1378 producer =
1379 get_next_index(producer, rcv_desc->max_rx_desc_count);
1380 index = get_next_index(index, rcv_desc->max_rx_desc_count);
1381 buffer = &rcv_desc->rx_buf_arr[index];
1382 }
1383
1384 /* if we did allocate buffers, then write the count to Phantom */
1385 if (count) {
1386 rcv_desc->begin_alloc = index;
1387 rcv_desc->rcv_pending += count;
1388 rcv_desc->producer = producer;
1389 /* Window = 1 */
1390 writel((producer - 1) &
1391 (rcv_desc->max_rx_desc_count - 1),
1392 NETXEN_CRB_NORMALIZE(adapter,
1393 recv_crb_registers[
1394 adapter->portnum].
1395 rcv_desc_crb[ringid].
1396 crb_rcv_producer_offset));
1397 wmb();
1398 }
1399 }
1400
1401 void netxen_nic_clear_stats(struct netxen_adapter *adapter)
1402 {
1403 memset(&adapter->stats, 0, sizeof(adapter->stats));
1404 return;
1405 }
1406
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