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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / net / netxen / netxen_nic_hw.c
blob05748ca6f216831543574dda76d0778883365865
1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #include "netxen_nic_phan_reg.h"
37
38
39 #include <net/ip.h>
40
41 struct netxen_recv_crb recv_crb_registers[] = {
42 /*
43 * Instance 0.
44 */
45 {
46 /* rcv_desc_crb: */
47 {
48 {
49 /* crb_rcv_producer_offset: */
50 NETXEN_NIC_REG(0x100),
51 /* crb_rcv_consumer_offset: */
52 NETXEN_NIC_REG(0x104),
53 /* crb_gloablrcv_ring: */
54 NETXEN_NIC_REG(0x108),
55 /* crb_rcv_ring_size */
56 NETXEN_NIC_REG(0x10c),
57
58 },
59 /* Jumbo frames */
60 {
61 /* crb_rcv_producer_offset: */
62 NETXEN_NIC_REG(0x110),
63 /* crb_rcv_consumer_offset: */
64 NETXEN_NIC_REG(0x114),
65 /* crb_gloablrcv_ring: */
66 NETXEN_NIC_REG(0x118),
67 /* crb_rcv_ring_size */
68 NETXEN_NIC_REG(0x11c),
69 },
70 /* LRO */
71 {
72 /* crb_rcv_producer_offset: */
73 NETXEN_NIC_REG(0x120),
74 /* crb_rcv_consumer_offset: */
75 NETXEN_NIC_REG(0x124),
76 /* crb_gloablrcv_ring: */
77 NETXEN_NIC_REG(0x128),
78 /* crb_rcv_ring_size */
79 NETXEN_NIC_REG(0x12c),
80 }
81 },
82 /* crb_rcvstatus_ring: */
83 NETXEN_NIC_REG(0x130),
84 /* crb_rcv_status_producer: */
85 NETXEN_NIC_REG(0x134),
86 /* crb_rcv_status_consumer: */
87 NETXEN_NIC_REG(0x138),
88 /* crb_rcvpeg_state: */
89 NETXEN_NIC_REG(0x13c),
90 /* crb_status_ring_size */
91 NETXEN_NIC_REG(0x140),
92
93 },
94 /*
95 * Instance 1,
96 */
97 {
98 /* rcv_desc_crb: */
99 {
100 {
101 /* crb_rcv_producer_offset: */
102 NETXEN_NIC_REG(0x144),
103 /* crb_rcv_consumer_offset: */
104 NETXEN_NIC_REG(0x148),
105 /* crb_globalrcv_ring: */
106 NETXEN_NIC_REG(0x14c),
107 /* crb_rcv_ring_size */
108 NETXEN_NIC_REG(0x150),
109
110 },
111 /* Jumbo frames */
112 {
113 /* crb_rcv_producer_offset: */
114 NETXEN_NIC_REG(0x154),
115 /* crb_rcv_consumer_offset: */
116 NETXEN_NIC_REG(0x158),
117 /* crb_globalrcv_ring: */
118 NETXEN_NIC_REG(0x15c),
119 /* crb_rcv_ring_size */
120 NETXEN_NIC_REG(0x160),
121 },
122 /* LRO */
123 {
124 /* crb_rcv_producer_offset: */
125 NETXEN_NIC_REG(0x164),
126 /* crb_rcv_consumer_offset: */
127 NETXEN_NIC_REG(0x168),
128 /* crb_globalrcv_ring: */
129 NETXEN_NIC_REG(0x16c),
130 /* crb_rcv_ring_size */
131 NETXEN_NIC_REG(0x170),
132 }
133
134 },
135 /* crb_rcvstatus_ring: */
136 NETXEN_NIC_REG(0x174),
137 /* crb_rcv_status_producer: */
138 NETXEN_NIC_REG(0x178),
139 /* crb_rcv_status_consumer: */
140 NETXEN_NIC_REG(0x17c),
141 /* crb_rcvpeg_state: */
142 NETXEN_NIC_REG(0x180),
143 /* crb_status_ring_size */
144 NETXEN_NIC_REG(0x184),
145 },
146 /*
147 * Instance 2,
148 */
149 {
150 {
151 {
152 /* crb_rcv_producer_offset: */
153 NETXEN_NIC_REG(0x1d8),
154 /* crb_rcv_consumer_offset: */
155 NETXEN_NIC_REG(0x1dc),
156 /* crb_gloablrcv_ring: */
157 NETXEN_NIC_REG(0x1f0),
158 /* crb_rcv_ring_size */
159 NETXEN_NIC_REG(0x1f4),
160 },
161 /* Jumbo frames */
162 {
163 /* crb_rcv_producer_offset: */
164 NETXEN_NIC_REG(0x1f8),
165 /* crb_rcv_consumer_offset: */
166 NETXEN_NIC_REG(0x1fc),
167 /* crb_gloablrcv_ring: */
168 NETXEN_NIC_REG(0x200),
169 /* crb_rcv_ring_size */
170 NETXEN_NIC_REG(0x204),
171 },
172 /* LRO */
173 {
174 /* crb_rcv_producer_offset: */
175 NETXEN_NIC_REG(0x208),
176 /* crb_rcv_consumer_offset: */
177 NETXEN_NIC_REG(0x20c),
178 /* crb_gloablrcv_ring: */
179 NETXEN_NIC_REG(0x210),
180 /* crb_rcv_ring_size */
181 NETXEN_NIC_REG(0x214),
182 }
183 },
184 /* crb_rcvstatus_ring: */
185 NETXEN_NIC_REG(0x218),
186 /* crb_rcv_status_producer: */
187 NETXEN_NIC_REG(0x21c),
188 /* crb_rcv_status_consumer: */
189 NETXEN_NIC_REG(0x220),
190 /* crb_rcvpeg_state: */
191 NETXEN_NIC_REG(0x224),
192 /* crb_status_ring_size */
193 NETXEN_NIC_REG(0x228),
194 },
195 /*
196 * Instance 3,
197 */
198 {
199 {
200 {
201 /* crb_rcv_producer_offset: */
202 NETXEN_NIC_REG(0x22c),
203 /* crb_rcv_consumer_offset: */
204 NETXEN_NIC_REG(0x230),
205 /* crb_gloablrcv_ring: */
206 NETXEN_NIC_REG(0x234),
207 /* crb_rcv_ring_size */
208 NETXEN_NIC_REG(0x238),
209 },
210 /* Jumbo frames */
211 {
212 /* crb_rcv_producer_offset: */
213 NETXEN_NIC_REG(0x23c),
214 /* crb_rcv_consumer_offset: */
215 NETXEN_NIC_REG(0x240),
216 /* crb_gloablrcv_ring: */
217 NETXEN_NIC_REG(0x244),
218 /* crb_rcv_ring_size */
219 NETXEN_NIC_REG(0x248),
220 },
221 /* LRO */
222 {
223 /* crb_rcv_producer_offset: */
224 NETXEN_NIC_REG(0x24c),
225 /* crb_rcv_consumer_offset: */
226 NETXEN_NIC_REG(0x250),
227 /* crb_gloablrcv_ring: */
228 NETXEN_NIC_REG(0x254),
229 /* crb_rcv_ring_size */
230 NETXEN_NIC_REG(0x258),
231 }
232 },
233 /* crb_rcvstatus_ring: */
234 NETXEN_NIC_REG(0x25c),
235 /* crb_rcv_status_producer: */
236 NETXEN_NIC_REG(0x260),
237 /* crb_rcv_status_consumer: */
238 NETXEN_NIC_REG(0x264),
239 /* crb_rcvpeg_state: */
240 NETXEN_NIC_REG(0x268),
241 /* crb_status_ring_size */
242 NETXEN_NIC_REG(0x26c),
243 },
244 };
245
246 static u64 ctx_addr_sig_regs[][3] = {
247 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
248 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
249 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
250 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
251 };
252 #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
253 #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
254 #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
255
256
257 /* PCI Windowing for DDR regions. */
258
259 #define ADDR_IN_RANGE(addr, low, high) \
260 (((addr) <= (high)) && ((addr) >= (low)))
261
262 #define NETXEN_FLASH_BASE (NETXEN_BOOTLD_START)
263 #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
264 #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
265 #define NETXEN_MIN_MTU 64
266 #define NETXEN_ETH_FCS_SIZE 4
267 #define NETXEN_ENET_HEADER_SIZE 14
268 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
269 #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
270 #define NETXEN_NIU_HDRSIZE (0x1 << 6)
271 #define NETXEN_NIU_TLRSIZE (0x1 << 5)
272
273 #define lower32(x) ((u32)((x) & 0xffffffff))
274 #define upper32(x) \
275 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
276
277 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
278 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
279 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
280 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
281
282 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
283
284 static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
285 unsigned long long addr);
286 void netxen_free_hw_resources(struct netxen_adapter *adapter);
287
288 int netxen_nic_set_mac(struct net_device *netdev, void *p)
289 {
290 struct netxen_adapter *adapter = netdev_priv(netdev);
291 struct sockaddr *addr = p;
292
293 if (netif_running(netdev))
294 return -EBUSY;
295
296 if (!is_valid_ether_addr(addr->sa_data))
297 return -EADDRNOTAVAIL;
298
299 DPRINTK(INFO, "valid ether addr\n");
300 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
301
302 if (adapter->macaddr_set)
303 adapter->macaddr_set(adapter, addr->sa_data);
304
305 return 0;
306 }
307
308 /*
309 * netxen_nic_set_multi - Multicast
310 */
311 void netxen_nic_set_multi(struct net_device *netdev)
312 {
313 struct netxen_adapter *adapter = netdev_priv(netdev);
314 struct dev_mc_list *mc_ptr;
315
316 mc_ptr = netdev->mc_list;
317 if (netdev->flags & IFF_PROMISC) {
318 if (adapter->set_promisc)
319 adapter->set_promisc(adapter,
320 NETXEN_NIU_PROMISC_MODE);
321 } else {
322 if (adapter->unset_promisc)
323 adapter->unset_promisc(adapter,
324 NETXEN_NIU_NON_PROMISC_MODE);
325 }
326 }
327
328 /*
329 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
330 * @returns 0 on success, negative on failure
331 */
332 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
333 {
334 struct netxen_adapter *adapter = netdev_priv(netdev);
335 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
336
337 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
338 printk(KERN_ERR "%s: %s %d is not supported.\n",
339 netxen_nic_driver_name, netdev->name, mtu);
340 return -EINVAL;
341 }
342
343 if (adapter->set_mtu)
344 adapter->set_mtu(adapter, mtu);
345 netdev->mtu = mtu;
346
347 return 0;
348 }
349
350 /*
351 * check if the firmware has been downloaded and ready to run and
352 * setup the address for the descriptors in the adapter
353 */
354 int netxen_nic_hw_resources(struct netxen_adapter *adapter)
355 {
356 struct netxen_hardware_context *hw = &adapter->ahw;
357 u32 state = 0;
358 void *addr;
359 int loops = 0, err = 0;
360 int ctx, ring;
361 struct netxen_recv_context *recv_ctx;
362 struct netxen_rcv_desc_ctx *rcv_desc;
363 int func_id = adapter->portnum;
364
365 DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
366 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
367 DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
368 pci_base_offset(adapter, NETXEN_CRB_CAM));
369 DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
370 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
371
372
373 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
374 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
375 loops = 0;
376 state = 0;
377 /* Window 1 call */
378 state = readl(NETXEN_CRB_NORMALIZE(adapter,
379 recv_crb_registers[ctx].
380 crb_rcvpeg_state));
381 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
382 msleep(1);
383 /* Window 1 call */
384 state = readl(NETXEN_CRB_NORMALIZE(adapter,
385 recv_crb_registers
386 [ctx].
387 crb_rcvpeg_state));
388 loops++;
389 }
390 if (loops >= 20) {
391 printk(KERN_ERR "Rcv Peg initialization not complete:"
392 "%x.\n", state);
393 err = -EIO;
394 return err;
395 }
396 }
397 adapter->intr_scheme = readl(
398 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW));
399 printk(KERN_NOTICE "%s: FW capabilities:0x%x\n", netxen_nic_driver_name,
400 adapter->intr_scheme);
401 adapter->msi_mode = readl(
402 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW));
403 DPRINTK(INFO, "Receive Peg ready too. starting stuff\n");
404
405 addr = netxen_alloc(adapter->ahw.pdev,
406 sizeof(struct netxen_ring_ctx) +
407 sizeof(uint32_t),
408 (dma_addr_t *) & adapter->ctx_desc_phys_addr,
409 &adapter->ctx_desc_pdev);
410
411 printk(KERN_INFO "ctx_desc_phys_addr: 0x%llx\n",
412 (unsigned long long) adapter->ctx_desc_phys_addr);
413 if (addr == NULL) {
414 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
415 err = -ENOMEM;
416 return err;
417 }
418 memset(addr, 0, sizeof(struct netxen_ring_ctx));
419 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
420 adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
421 adapter->ctx_desc->cmd_consumer_offset =
422 cpu_to_le64(adapter->ctx_desc_phys_addr +
423 sizeof(struct netxen_ring_ctx));
424 adapter->cmd_consumer = (__le32 *) (((char *)addr) +
425 sizeof(struct netxen_ring_ctx));
426
427 addr = netxen_alloc(adapter->ahw.pdev,
428 sizeof(struct cmd_desc_type0) *
429 adapter->max_tx_desc_count,
430 (dma_addr_t *) & hw->cmd_desc_phys_addr,
431 &adapter->ahw.cmd_desc_pdev);
432 printk(KERN_INFO "cmd_desc_phys_addr: 0x%llx\n",
433 (unsigned long long) hw->cmd_desc_phys_addr);
434
435 if (addr == NULL) {
436 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
437 netxen_free_hw_resources(adapter);
438 return -ENOMEM;
439 }
440
441 adapter->ctx_desc->cmd_ring_addr =
442 cpu_to_le64(hw->cmd_desc_phys_addr);
443 adapter->ctx_desc->cmd_ring_size =
444 cpu_to_le32(adapter->max_tx_desc_count);
445
446 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
447
448 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
449 recv_ctx = &adapter->recv_ctx[ctx];
450
451 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
452 rcv_desc = &recv_ctx->rcv_desc[ring];
453 addr = netxen_alloc(adapter->ahw.pdev,
454 RCV_DESC_RINGSIZE,
455 &rcv_desc->phys_addr,
456 &rcv_desc->phys_pdev);
457 if (addr == NULL) {
458 DPRINTK(ERR, "bad return from "
459 "pci_alloc_consistent\n");
460 netxen_free_hw_resources(adapter);
461 err = -ENOMEM;
462 return err;
463 }
464 rcv_desc->desc_head = (struct rcv_desc *)addr;
465 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
466 cpu_to_le64(rcv_desc->phys_addr);
467 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
468 cpu_to_le32(rcv_desc->max_rx_desc_count);
469 }
470
471 addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
472 &recv_ctx->rcv_status_desc_phys_addr,
473 &recv_ctx->rcv_status_desc_pdev);
474 if (addr == NULL) {
475 DPRINTK(ERR, "bad return from"
476 " pci_alloc_consistent\n");
477 netxen_free_hw_resources(adapter);
478 err = -ENOMEM;
479 return err;
480 }
481 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
482 adapter->ctx_desc->sts_ring_addr =
483 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
484 adapter->ctx_desc->sts_ring_size =
485 cpu_to_le32(adapter->max_rx_desc_count);
486
487 }
488 /* Window = 1 */
489
490 writel(lower32(adapter->ctx_desc_phys_addr),
491 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id)));
492 writel(upper32(adapter->ctx_desc_phys_addr),
493 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id)));
494 writel(NETXEN_CTX_SIGNATURE | func_id,
495 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id)));
496 return err;
497 }
498
499 void netxen_free_hw_resources(struct netxen_adapter *adapter)
500 {
501 struct netxen_recv_context *recv_ctx;
502 struct netxen_rcv_desc_ctx *rcv_desc;
503 int ctx, ring;
504
505 if (adapter->ctx_desc != NULL) {
506 pci_free_consistent(adapter->ctx_desc_pdev,
507 sizeof(struct netxen_ring_ctx) +
508 sizeof(uint32_t),
509 adapter->ctx_desc,
510 adapter->ctx_desc_phys_addr);
511 adapter->ctx_desc = NULL;
512 }
513
514 if (adapter->ahw.cmd_desc_head != NULL) {
515 pci_free_consistent(adapter->ahw.cmd_desc_pdev,
516 sizeof(struct cmd_desc_type0) *
517 adapter->max_tx_desc_count,
518 adapter->ahw.cmd_desc_head,
519 adapter->ahw.cmd_desc_phys_addr);
520 adapter->ahw.cmd_desc_head = NULL;
521 }
522
523 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
524 recv_ctx = &adapter->recv_ctx[ctx];
525 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
526 rcv_desc = &recv_ctx->rcv_desc[ring];
527
528 if (rcv_desc->desc_head != NULL) {
529 pci_free_consistent(rcv_desc->phys_pdev,
530 RCV_DESC_RINGSIZE,
531 rcv_desc->desc_head,
532 rcv_desc->phys_addr);
533 rcv_desc->desc_head = NULL;
534 }
535 }
536
537 if (recv_ctx->rcv_status_desc_head != NULL) {
538 pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
539 STATUS_DESC_RINGSIZE,
540 recv_ctx->rcv_status_desc_head,
541 recv_ctx->
542 rcv_status_desc_phys_addr);
543 recv_ctx->rcv_status_desc_head = NULL;
544 }
545 }
546 }
547
548 void netxen_tso_check(struct netxen_adapter *adapter,
549 struct cmd_desc_type0 *desc, struct sk_buff *skb)
550 {
551 if (desc->mss) {
552 desc->total_hdr_length = (sizeof(struct ethhdr) +
553 ip_hdrlen(skb) + tcp_hdrlen(skb));
554 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
555 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
556 if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
557 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
558 } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
559 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
560 } else {
561 return;
562 }
563 }
564 desc->tcp_hdr_offset = skb_transport_offset(skb);
565 desc->ip_hdr_offset = skb_network_offset(skb);
566 }
567
568 int netxen_is_flash_supported(struct netxen_adapter *adapter)
569 {
570 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
571 int addr, val01, val02, i, j;
572
573 /* if the flash size less than 4Mb, make huge war cry and die */
574 for (j = 1; j < 4; j++) {
575 addr = j * NETXEN_NIC_WINDOW_MARGIN;
576 for (i = 0; i < ARRAY_SIZE(locs); i++) {
577 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
578 && netxen_rom_fast_read(adapter, (addr + locs[i]),
579 &val02) == 0) {
580 if (val01 == val02)
581 return -1;
582 } else
583 return -1;
584 }
585 }
586
587 return 0;
588 }
589
590 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
591 int size, __le32 * buf)
592 {
593 int i, addr;
594 __le32 *ptr32;
595 u32 v;
596
597 addr = base;
598 ptr32 = buf;
599 for (i = 0; i < size / sizeof(u32); i++) {
600 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
601 return -1;
602 *ptr32 = cpu_to_le32(v);
603 ptr32++;
604 addr += sizeof(u32);
605 }
606 if ((char *)buf + size > (char *)ptr32) {
607 __le32 local;
608 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
609 return -1;
610 local = cpu_to_le32(v);
611 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
612 }
613
614 return 0;
615 }
616
617 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
618 {
619 __le32 *pmac = (__le32 *) & mac[0];
620
621 if (netxen_get_flash_block(adapter,
622 NETXEN_USER_START +
623 offsetof(struct netxen_new_user_info,
624 mac_addr),
625 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
626 return -1;
627 }
628 if (*mac == cpu_to_le64(~0ULL)) {
629 if (netxen_get_flash_block(adapter,
630 NETXEN_USER_START_OLD +
631 offsetof(struct netxen_user_old_info,
632 mac_addr),
633 FLASH_NUM_PORTS * sizeof(u64),
634 pmac) == -1)
635 return -1;
636 if (*mac == cpu_to_le64(~0ULL))
637 return -1;
638 }
639 return 0;
640 }
641
642 /*
643 * Changes the CRB window to the specified window.
644 */
645 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
646 {
647 void __iomem *offset;
648 u32 tmp;
649 int count = 0;
650
651 if (adapter->curr_window == wndw)
652 return;
653 switch(adapter->ahw.pci_func) {
654 case 0:
655 offset = PCI_OFFSET_SECOND_RANGE(adapter,
656 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
657 break;
658 case 1:
659 offset = PCI_OFFSET_SECOND_RANGE(adapter,
660 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1));
661 break;
662 case 2:
663 offset = PCI_OFFSET_SECOND_RANGE(adapter,
664 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2));
665 break;
666 case 3:
667 offset = PCI_OFFSET_SECOND_RANGE(adapter,
668 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3));
669 break;
670 default:
671 printk(KERN_INFO "Changing the window for PCI function "
672 "%d\n", adapter->ahw.pci_func);
673 offset = PCI_OFFSET_SECOND_RANGE(adapter,
674 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
675 break;
676 }
677 /*
678 * Move the CRB window.
679 * We need to write to the "direct access" region of PCI
680 * to avoid a race condition where the window register has
681 * not been successfully written across CRB before the target
682 * register address is received by PCI. The direct region bypasses
683 * the CRB bus.
684 */
685
686 if (wndw & 0x1)
687 wndw = NETXEN_WINDOW_ONE;
688
689 writel(wndw, offset);
690
691 /* MUST make sure window is set before we forge on... */
692 while ((tmp = readl(offset)) != wndw) {
693 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
694 "registered properly: 0x%08x.\n",
695 netxen_nic_driver_name, __FUNCTION__, tmp);
696 mdelay(1);
697 if (count >= 10)
698 break;
699 count++;
700 }
701
702 if (wndw == NETXEN_WINDOW_ONE)
703 adapter->curr_window = 1;
704 else
705 adapter->curr_window = 0;
706 }
707
708 int netxen_load_firmware(struct netxen_adapter *adapter)
709 {
710 int i;
711 u32 data, size = 0;
712 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
713 u64 off;
714 void __iomem *addr;
715
716 size = NETXEN_FIRMWARE_LEN;
717 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
718
719 for (i = 0; i < size; i++) {
720 int retries = 10;
721 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
722 return -EIO;
723
724 off = netxen_nic_pci_set_window(adapter, memaddr);
725 addr = pci_base_offset(adapter, off);
726 writel(data, addr);
727 do {
728 if (readl(addr) == data)
729 break;
730 msleep(100);
731 writel(data, addr);
732 } while (--retries);
733 if (!retries) {
734 printk(KERN_ERR "%s: firmware load aborted, write failed at 0x%x\n",
735 netxen_nic_driver_name, memaddr);
736 return -EIO;
737 }
738 flashaddr += 4;
739 memaddr += 4;
740 }
741 udelay(100);
742 /* make sure Casper is powered on */
743 writel(0x3fff,
744 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
745 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
746
747 return 0;
748 }
749
750 int
751 netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
752 int len)
753 {
754 void __iomem *addr;
755
756 if (ADDR_IN_WINDOW1(off)) {
757 addr = NETXEN_CRB_NORMALIZE(adapter, off);
758 } else { /* Window 0 */
759 addr = pci_base_offset(adapter, off);
760 netxen_nic_pci_change_crbwindow(adapter, 0);
761 }
762
763 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
764 " data %llx len %d\n",
765 pci_base(adapter, off), off, addr,
766 *(unsigned long long *)data, len);
767 if (!addr) {
768 netxen_nic_pci_change_crbwindow(adapter, 1);
769 return 1;
770 }
771
772 switch (len) {
773 case 1:
774 writeb(*(u8 *) data, addr);
775 break;
776 case 2:
777 writew(*(u16 *) data, addr);
778 break;
779 case 4:
780 writel(*(u32 *) data, addr);
781 break;
782 case 8:
783 writeq(*(u64 *) data, addr);
784 break;
785 default:
786 DPRINTK(INFO,
787 "writing data %lx to offset %llx, num words=%d\n",
788 *(unsigned long *)data, off, (len >> 3));
789
790 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
791 (len >> 3));
792 break;
793 }
794 if (!ADDR_IN_WINDOW1(off))
795 netxen_nic_pci_change_crbwindow(adapter, 1);
796
797 return 0;
798 }
799
800 int
801 netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
802 int len)
803 {
804 void __iomem *addr;
805
806 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
807 addr = NETXEN_CRB_NORMALIZE(adapter, off);
808 } else { /* Window 0 */
809 addr = pci_base_offset(adapter, off);
810 netxen_nic_pci_change_crbwindow(adapter, 0);
811 }
812
813 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
814 pci_base(adapter, off), off, addr);
815 if (!addr) {
816 netxen_nic_pci_change_crbwindow(adapter, 1);
817 return 1;
818 }
819 switch (len) {
820 case 1:
821 *(u8 *) data = readb(addr);
822 break;
823 case 2:
824 *(u16 *) data = readw(addr);
825 break;
826 case 4:
827 *(u32 *) data = readl(addr);
828 break;
829 case 8:
830 *(u64 *) data = readq(addr);
831 break;
832 default:
833 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
834 (len >> 3));
835 break;
836 }
837 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
838
839 if (!ADDR_IN_WINDOW1(off))
840 netxen_nic_pci_change_crbwindow(adapter, 1);
841
842 return 0;
843 }
844
845 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
846 { /* Only for window 1 */
847 void __iomem *addr;
848
849 addr = NETXEN_CRB_NORMALIZE(adapter, off);
850 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
851 pci_base(adapter, off), off, addr, val);
852 writel(val, addr);
853
854 }
855
856 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
857 { /* Only for window 1 */
858 void __iomem *addr;
859 int val;
860
861 addr = NETXEN_CRB_NORMALIZE(adapter, off);
862 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
863 pci_base(adapter, off), off, addr);
864 val = readl(addr);
865 writel(val, addr);
866
867 return val;
868 }
869
870 /* Change the window to 0, write and change back to window 1. */
871 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
872 {
873 void __iomem *addr;
874
875 netxen_nic_pci_change_crbwindow(adapter, 0);
876 addr = pci_base_offset(adapter, index);
877 writel(value, addr);
878 netxen_nic_pci_change_crbwindow(adapter, 1);
879 }
880
881 /* Change the window to 0, read and change back to window 1. */
882 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
883 {
884 void __iomem *addr;
885
886 addr = pci_base_offset(adapter, index);
887
888 netxen_nic_pci_change_crbwindow(adapter, 0);
889 *value = readl(addr);
890 netxen_nic_pci_change_crbwindow(adapter, 1);
891 }
892
893 static int netxen_pci_set_window_warning_count;
894
895 static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
896 unsigned long long addr)
897 {
898 static int ddr_mn_window = -1;
899 static int qdr_sn_window = -1;
900 int window;
901
902 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
903 /* DDR network side */
904 addr -= NETXEN_ADDR_DDR_NET;
905 window = (addr >> 25) & 0x3ff;
906 if (ddr_mn_window != window) {
907 ddr_mn_window = window;
908 writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
909 NETXEN_PCIX_PH_REG
910 (PCIX_MN_WINDOW(adapter->ahw.pci_func))));
911 /* MUST make sure window is set before we forge on... */
912 readl(PCI_OFFSET_SECOND_RANGE(adapter,
913 NETXEN_PCIX_PH_REG
914 (PCIX_MN_WINDOW(adapter->ahw.pci_func))));
915 }
916 addr -= (window * NETXEN_WINDOW_ONE);
917 addr += NETXEN_PCI_DDR_NET;
918 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
919 addr -= NETXEN_ADDR_OCM0;
920 addr += NETXEN_PCI_OCM0;
921 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
922 addr -= NETXEN_ADDR_OCM1;
923 addr += NETXEN_PCI_OCM1;
924 } else
925 if (ADDR_IN_RANGE
926 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
927 /* QDR network side */
928 addr -= NETXEN_ADDR_QDR_NET;
929 window = (addr >> 22) & 0x3f;
930 if (qdr_sn_window != window) {
931 qdr_sn_window = window;
932 writel((window << 22),
933 PCI_OFFSET_SECOND_RANGE(adapter,
934 NETXEN_PCIX_PH_REG
935 (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
936 /* MUST make sure window is set before we forge on... */
937 readl(PCI_OFFSET_SECOND_RANGE(adapter,
938 NETXEN_PCIX_PH_REG
939 (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
940 }
941 addr -= (window * 0x400000);
942 addr += NETXEN_PCI_QDR_NET;
943 } else {
944 /*
945 * peg gdb frequently accesses memory that doesn't exist,
946 * this limits the chit chat so debugging isn't slowed down.
947 */
948 if ((netxen_pci_set_window_warning_count++ < 8)
949 || (netxen_pci_set_window_warning_count % 64 == 0))
950 printk("%s: Warning:netxen_nic_pci_set_window()"
951 " Unknown address range!\n",
952 netxen_nic_driver_name);
953
954 }
955 return addr;
956 }
957
958 #if 0
959 int
960 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
961 {
962 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
963 printk(KERN_ERR "%s: erase pxe failed\n",
964 netxen_nic_driver_name);
965 return -1;
966 }
967 return 0;
968 }
969 #endif /* 0 */
970
971 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
972 {
973 int rv = 0;
974 int addr = NETXEN_BRDCFG_START;
975 struct netxen_board_info *boardinfo;
976 int index;
977 u32 *ptr32;
978
979 boardinfo = &adapter->ahw.boardcfg;
980 ptr32 = (u32 *) boardinfo;
981
982 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
983 index++) {
984 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
985 return -EIO;
986 }
987 ptr32++;
988 addr += sizeof(u32);
989 }
990 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
991 printk("%s: ERROR reading %s board config."
992 " Read %x, expected %x\n", netxen_nic_driver_name,
993 netxen_nic_driver_name,
994 boardinfo->magic, NETXEN_BDINFO_MAGIC);
995 rv = -1;
996 }
997 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
998 printk("%s: Unknown board config version."
999 " Read %x, expected %x\n", netxen_nic_driver_name,
1000 boardinfo->header_version, NETXEN_BDINFO_VERSION);
1001 rv = -1;
1002 }
1003
1004 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
1005 switch ((netxen_brdtype_t) boardinfo->board_type) {
1006 case NETXEN_BRDTYPE_P2_SB35_4G:
1007 adapter->ahw.board_type = NETXEN_NIC_GBE;
1008 break;
1009 case NETXEN_BRDTYPE_P2_SB31_10G:
1010 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1011 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1012 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1013 adapter->ahw.board_type = NETXEN_NIC_XGBE;
1014 break;
1015 case NETXEN_BRDTYPE_P1_BD:
1016 case NETXEN_BRDTYPE_P1_SB:
1017 case NETXEN_BRDTYPE_P1_SMAX:
1018 case NETXEN_BRDTYPE_P1_SOCK:
1019 adapter->ahw.board_type = NETXEN_NIC_GBE;
1020 break;
1021 default:
1022 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
1023 boardinfo->board_type);
1024 break;
1025 }
1026
1027 return rv;
1028 }
1029
1030 /* NIU access sections */
1031
1032 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1033 {
1034 netxen_nic_write_w0(adapter,
1035 NETXEN_NIU_GB_MAX_FRAME_SIZE(
1036 physical_port[adapter->portnum]), new_mtu);
1037 return 0;
1038 }
1039
1040 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1041 {
1042 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
1043 if (physical_port[adapter->portnum] == 0)
1044 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
1045 new_mtu);
1046 else
1047 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
1048 new_mtu);
1049 return 0;
1050 }
1051
1052 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
1053 {
1054 netxen_niu_gbe_init_port(adapter, physical_port[adapter->portnum]);
1055 }
1056
1057 void
1058 netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
1059 int data)
1060 {
1061 void __iomem *addr;
1062
1063 if (ADDR_IN_WINDOW1(off)) {
1064 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1065 } else {
1066 netxen_nic_pci_change_crbwindow(adapter, 0);
1067 addr = pci_base_offset(adapter, off);
1068 writel(data, addr);
1069 netxen_nic_pci_change_crbwindow(adapter, 1);
1070 }
1071 }
1072
1073 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1074 {
1075 __u32 status;
1076 __u32 autoneg;
1077 __u32 mode;
1078
1079 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
1080 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
1081 if (adapter->phy_read
1082 && adapter->
1083 phy_read(adapter,
1084 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1085 &status) == 0) {
1086 if (netxen_get_phy_link(status)) {
1087 switch (netxen_get_phy_speed(status)) {
1088 case 0:
1089 adapter->link_speed = SPEED_10;
1090 break;
1091 case 1:
1092 adapter->link_speed = SPEED_100;
1093 break;
1094 case 2:
1095 adapter->link_speed = SPEED_1000;
1096 break;
1097 default:
1098 adapter->link_speed = -1;
1099 break;
1100 }
1101 switch (netxen_get_phy_duplex(status)) {
1102 case 0:
1103 adapter->link_duplex = DUPLEX_HALF;
1104 break;
1105 case 1:
1106 adapter->link_duplex = DUPLEX_FULL;
1107 break;
1108 default:
1109 adapter->link_duplex = -1;
1110 break;
1111 }
1112 if (adapter->phy_read
1113 && adapter->
1114 phy_read(adapter,
1115 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1116 &autoneg) != 0)
1117 adapter->link_autoneg = autoneg;
1118 } else
1119 goto link_down;
1120 } else {
1121 link_down:
1122 adapter->link_speed = -1;
1123 adapter->link_duplex = -1;
1124 }
1125 }
1126 }
1127
1128 void netxen_nic_flash_print(struct netxen_adapter *adapter)
1129 {
1130 int valid = 1;
1131 u32 fw_major = 0;
1132 u32 fw_minor = 0;
1133 u32 fw_build = 0;
1134 char brd_name[NETXEN_MAX_SHORT_NAME];
1135 struct netxen_new_user_info user_info;
1136 int i, addr = NETXEN_USER_START;
1137 __le32 *ptr32;
1138
1139 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
1140 if (board_info->magic != NETXEN_BDINFO_MAGIC) {
1141 printk
1142 ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
1143 board_info->magic, NETXEN_BDINFO_MAGIC);
1144 valid = 0;
1145 }
1146 if (board_info->header_version != NETXEN_BDINFO_VERSION) {
1147 printk("NetXen Unknown board config version."
1148 " Read %x, expected %x\n",
1149 board_info->header_version, NETXEN_BDINFO_VERSION);
1150 valid = 0;
1151 }
1152 if (valid) {
1153 ptr32 = (u32 *) & user_info;
1154 for (i = 0;
1155 i < sizeof(struct netxen_new_user_info) / sizeof(u32);
1156 i++) {
1157 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1158 printk("%s: ERROR reading %s board userarea.\n",
1159 netxen_nic_driver_name,
1160 netxen_nic_driver_name);
1161 return;
1162 }
1163 ptr32++;
1164 addr += sizeof(u32);
1165 }
1166 get_brd_name_by_type(board_info->board_type, brd_name);
1167
1168 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
1169 brd_name, user_info.serial_num, board_info->chip_id);
1170
1171 printk("NetXen %s Board #%d, Chip id 0x%x\n",
1172 board_info->board_type == 0x0b ? "XGB" : "GBE",
1173 board_info->board_num, board_info->chip_id);
1174 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
1175 NETXEN_FW_VERSION_MAJOR));
1176 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
1177 NETXEN_FW_VERSION_MINOR));
1178 fw_build =
1179 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
1180
1181 printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
1182 fw_build);
1183 }
1184 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
1185 printk(KERN_ERR "The mismatch in driver version and firmware "
1186 "version major number\n"
1187 "Driver version major number = %d \t"
1188 "Firmware version major number = %d \n",
1189 _NETXEN_NIC_LINUX_MAJOR, fw_major);
1190 adapter->driver_mismatch = 1;
1191 }
1192 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
1193 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
1194 printk(KERN_ERR "The mismatch in driver version and firmware "
1195 "version minor number\n"
1196 "Driver version minor number = %d \t"
1197 "Firmware version minor number = %d \n",
1198 _NETXEN_NIC_LINUX_MINOR, fw_minor);
1199 adapter->driver_mismatch = 1;
1200 }
1201 if (adapter->driver_mismatch)
1202 printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
1203 fw_major, fw_minor);
1204 }
1205
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