?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / isdn / hisax / bkm_a8.c
blob99ef3b43fcd79ebf276dfcd6ce48c0b60f80433f
1 /* $Id: bkm_a8.c,v 1.22.2.4 2004/01/15 14:02:34 keil Exp $
2 *
3 * low level stuff for Scitel Quadro (4*S0, passive)
4 *
5 * Author Roland Klabunde
6 * Copyright by Roland Klabunde <R.Klabunde@Berkom.de>
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 */
12
13
14 #include <linux/init.h>
15 #include "hisax.h"
16 #include "isac.h"
17 #include "ipac.h"
18 #include "hscx.h"
19 #include "isdnl1.h"
20 #include <linux/pci.h>
21 #include "bkm_ax.h"
22
23 #define ATTEMPT_PCI_REMAPPING /* Required for PLX rev 1 */
24
25 extern const char *CardType[];
26
27 static const char sct_quadro_revision[] = "$Revision: 1.22.2.4 $";
28
29 static const char *sct_quadro_subtypes[] =
30 {
31 "",
32 "#1",
33 "#2",
34 "#3",
35 "#4"
36 };
37
38
39 #define wordout(addr,val) outw(val,addr)
40 #define wordin(addr) inw(addr)
41
42 static inline u_char
43 readreg(unsigned int ale, unsigned int adr, u_char off)
44 {
45 register u_char ret;
46 wordout(ale, off);
47 ret = wordin(adr) & 0xFF;
48 return (ret);
49 }
50
51 static inline void
52 readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
53 {
54 int i;
55 wordout(ale, off);
56 for (i = 0; i < size; i++)
57 data[i] = wordin(adr) & 0xFF;
58 }
59
60
61 static inline void
62 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
63 {
64 wordout(ale, off);
65 wordout(adr, data);
66 }
67
68 static inline void
69 writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
70 {
71 int i;
72 wordout(ale, off);
73 for (i = 0; i < size; i++)
74 wordout(adr, data[i]);
75 }
76
77 /* Interface functions */
78
79 static u_char
80 ReadISAC(struct IsdnCardState *cs, u_char offset)
81 {
82 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80));
83 }
84
85 static void
86 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
87 {
88 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);
89 }
90
91 static void
92 ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
93 {
94 readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
95 }
96
97 static void
98 WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
99 {
100 writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
101 }
102
103
104 static u_char
105 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
106 {
107 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0)));
108 }
109
110 static void
111 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
112 {
113 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);
114 }
115
116 /* Set the specific ipac to active */
117 static void
118 set_ipac_active(struct IsdnCardState *cs, u_int active)
119 {
120 /* set irq mask */
121 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,
122 active ? 0xc0 : 0xff);
123 }
124
125 /*
126 * fast interrupt HSCX stuff goes here
127 */
128
129 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \
130 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
131 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
132 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
133 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \
134 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
135 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base, \
136 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
137
138 #include "hscx_irq.c"
139
140 static irqreturn_t
141 bkm_interrupt_ipac(int intno, void *dev_id)
142 {
143 struct IsdnCardState *cs = dev_id;
144 u_char ista, val, icnt = 5;
145 u_long flags;
146
147 spin_lock_irqsave(&cs->lock, flags);
148 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
149 if (!(ista & 0x3f)) { /* not this IPAC */
150 spin_unlock_irqrestore(&cs->lock, flags);
151 return IRQ_NONE;
152 }
153 Start_IPAC:
154 if (cs->debug & L1_DEB_IPAC)
155 debugl1(cs, "IPAC ISTA %02X", ista);
156 if (ista & 0x0f) {
157 val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40);
158 if (ista & 0x01)
159 val |= 0x01;
160 if (ista & 0x04)
161 val |= 0x02;
162 if (ista & 0x08)
163 val |= 0x04;
164 if (val) {
165 hscx_int_main(cs, val);
166 }
167 }
168 if (ista & 0x20) {
169 val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80);
170 if (val) {
171 isac_interrupt(cs, val);
172 }
173 }
174 if (ista & 0x10) {
175 val = 0x01;
176 isac_interrupt(cs, val);
177 }
178 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
179 if ((ista & 0x3f) && icnt) {
180 icnt--;
181 goto Start_IPAC;
182 }
183 if (!icnt)
184 printk(KERN_WARNING "HiSax: %s (%s) IRQ LOOP\n",
185 CardType[cs->typ],
186 sct_quadro_subtypes[cs->subtyp]);
187 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);
188 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);
189 spin_unlock_irqrestore(&cs->lock, flags);
190 return IRQ_HANDLED;
191 }
192
193 static void
194 release_io_sct_quadro(struct IsdnCardState *cs)
195 {
196 release_region(cs->hw.ax.base & 0xffffffc0, 128);
197 if (cs->subtyp == SCT_1)
198 release_region(cs->hw.ax.plx_adr, 64);
199 }
200
201 static void
202 enable_bkm_int(struct IsdnCardState *cs, unsigned bEnable)
203 {
204 if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
205 if (bEnable)
206 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) | 0x41));
207 else
208 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) & ~0x41));
209 }
210 }
211
212 static void
213 reset_bkm(struct IsdnCardState *cs)
214 {
215 if (cs->subtyp == SCT_1) {
216 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) & ~4));
217 mdelay(10);
218 /* Remove the soft reset */
219 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) | 4));
220 mdelay(10);
221 }
222 }
223
224 static int
225 BKM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
226 {
227 u_long flags;
228
229 switch (mt) {
230 case CARD_RESET:
231 spin_lock_irqsave(&cs->lock, flags);
232 /* Disable ints */
233 set_ipac_active(cs, 0);
234 enable_bkm_int(cs, 0);
235 reset_bkm(cs);
236 spin_unlock_irqrestore(&cs->lock, flags);
237 return (0);
238 case CARD_RELEASE:
239 /* Sanity */
240 spin_lock_irqsave(&cs->lock, flags);
241 set_ipac_active(cs, 0);
242 enable_bkm_int(cs, 0);
243 spin_unlock_irqrestore(&cs->lock, flags);
244 release_io_sct_quadro(cs);
245 return (0);
246 case CARD_INIT:
247 spin_lock_irqsave(&cs->lock, flags);
248 cs->debug |= L1_DEB_IPAC;
249 set_ipac_active(cs, 1);
250 inithscxisac(cs, 3);
251 /* Enable ints */
252 enable_bkm_int(cs, 1);
253 spin_unlock_irqrestore(&cs->lock, flags);
254 return (0);
255 case CARD_TEST:
256 return (0);
257 }
258 return (0);
259 }
260
261 static int __devinit
262 sct_alloc_io(u_int adr, u_int len)
263 {
264 if (!request_region(adr, len, "scitel")) {
265 printk(KERN_WARNING
266 "HiSax: Scitel port %#x-%#x already in use\n",
267 adr, adr + len);
268 return (1);
269 }
270 return(0);
271 }
272
273 static struct pci_dev *dev_a8 __devinitdata = NULL;
274 static u16 sub_vendor_id __devinitdata = 0;
275 static u16 sub_sys_id __devinitdata = 0;
276 static u_char pci_bus __devinitdata = 0;
277 static u_char pci_device_fn __devinitdata = 0;
278 static u_char pci_irq __devinitdata = 0;
279
280 int __devinit
281 setup_sct_quadro(struct IsdnCard *card)
282 {
283 struct IsdnCardState *cs = card->cs;
284 char tmp[64];
285 u_int found = 0;
286 u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;
287
288 strcpy(tmp, sct_quadro_revision);
289 printk(KERN_INFO "HiSax: T-Berkom driver Rev. %s\n", HiSax_getrev(tmp));
290 if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
291 cs->subtyp = SCT_1; /* Preset */
292 } else
293 return (0);
294
295 /* Identify subtype by para[0] */
296 if (card->para[0] >= SCT_1 && card->para[0] <= SCT_4)
297 cs->subtyp = card->para[0];
298 else {
299 printk(KERN_WARNING "HiSax: %s: Invalid subcontroller in configuration, default to 1\n",
300 CardType[card->typ]);
301 return (0);
302 }
303 if ((cs->subtyp != SCT_1) && ((sub_sys_id != PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) ||
304 (sub_vendor_id != PCI_VENDOR_ID_BERKOM)))
305 return (0);
306 if (cs->subtyp == SCT_1) {
307 while ((dev_a8 = pci_find_device(PCI_VENDOR_ID_PLX,
308 PCI_DEVICE_ID_PLX_9050, dev_a8))) {
309
310 sub_vendor_id = dev_a8->subsystem_vendor;
311 sub_sys_id = dev_a8->subsystem_device;
312 if ((sub_sys_id == PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) &&
313 (sub_vendor_id == PCI_VENDOR_ID_BERKOM)) {
314 if (pci_enable_device(dev_a8))
315 return(0);
316 pci_ioaddr1 = pci_resource_start(dev_a8, 1);
317 pci_irq = dev_a8->irq;
318 pci_bus = dev_a8->bus->number;
319 pci_device_fn = dev_a8->devfn;
320 found = 1;
321 break;
322 }
323 }
324 if (!found) {
325 printk(KERN_WARNING "HiSax: %s (%s): Card not found\n",
326 CardType[card->typ],
327 sct_quadro_subtypes[cs->subtyp]);
328 return (0);
329 }
330 #ifdef ATTEMPT_PCI_REMAPPING
331 /* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
332 if ((pci_ioaddr1 & 0x80) && (dev_a8->revision == 1)) {
333 printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
334 CardType[card->typ],
335 sct_quadro_subtypes[cs->subtyp]);
336 /* Restart PCI negotiation */
337 pci_write_config_dword(dev_a8, PCI_BASE_ADDRESS_1, (u_int) - 1);
338 /* Move up by 0x80 byte */
339 pci_ioaddr1 += 0x80;
340 pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
341 pci_write_config_dword(dev_a8, PCI_BASE_ADDRESS_1, pci_ioaddr1);
342 dev_a8->resource[ 1].start = pci_ioaddr1;
343 }
344 #endif /* End HACK */
345 }
346 if (!pci_irq) { /* IRQ range check ?? */
347 printk(KERN_WARNING "HiSax: %s (%s): No IRQ\n",
348 CardType[card->typ],
349 sct_quadro_subtypes[cs->subtyp]);
350 return (0);
351 }
352 pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
353 pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
354 pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
355 pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
356 pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
357 if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
358 printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
359 CardType[card->typ],
360 sct_quadro_subtypes[cs->subtyp]);
361 return (0);
362 }
363 pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
364 pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
365 pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
366 pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
367 pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
368 /* Take over */
369 cs->irq = pci_irq;
370 cs->irq_flags |= IRQF_SHARED;
371 /* pci_ioaddr1 is unique to all subdevices */
372 /* pci_ioaddr2 is for the fourth subdevice only */
373 /* pci_ioaddr3 is for the third subdevice only */
374 /* pci_ioaddr4 is for the second subdevice only */
375 /* pci_ioaddr5 is for the first subdevice only */
376 cs->hw.ax.plx_adr = pci_ioaddr1;
377 /* Enter all ipac_base addresses */
378 switch(cs->subtyp) {
379 case 1:
380 cs->hw.ax.base = pci_ioaddr5 + 0x00;
381 if (sct_alloc_io(pci_ioaddr1, 128))
382 return(0);
383 if (sct_alloc_io(pci_ioaddr5, 64))
384 return(0);
385 /* disable all IPAC */
386 writereg(pci_ioaddr5, pci_ioaddr5 + 4,
387 IPAC_MASK, 0xFF);
388 writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
389 IPAC_MASK, 0xFF);
390 writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,
391 IPAC_MASK, 0xFF);
392 writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,
393 IPAC_MASK, 0xFF);
394 break;
395 case 2:
396 cs->hw.ax.base = pci_ioaddr4 + 0x08;
397 if (sct_alloc_io(pci_ioaddr4, 64))
398 return(0);
399 break;
400 case 3:
401 cs->hw.ax.base = pci_ioaddr3 + 0x10;
402 if (sct_alloc_io(pci_ioaddr3, 64))
403 return(0);
404 break;
405 case 4:
406 cs->hw.ax.base = pci_ioaddr2 + 0x20;
407 if (sct_alloc_io(pci_ioaddr2, 64))
408 return(0);
409 break;
410 }
411 /* For isac and hscx data path */
412 cs->hw.ax.data_adr = cs->hw.ax.base + 4;
413
414 printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
415 CardType[card->typ],
416 sct_quadro_subtypes[cs->subtyp],
417 cs->hw.ax.plx_adr,
418 cs->hw.ax.base,
419 cs->hw.ax.data_adr,
420 cs->irq);
421
422 test_and_set_bit(HW_IPAC, &cs->HW_Flags);
423
424 cs->readisac = &ReadISAC;
425 cs->writeisac = &WriteISAC;
426 cs->readisacfifo = &ReadISACfifo;
427 cs->writeisacfifo = &WriteISACfifo;
428
429 cs->BC_Read_Reg = &ReadHSCX;
430 cs->BC_Write_Reg = &WriteHSCX;
431 cs->BC_Send_Data = &hscx_fill_fifo;
432 cs->cardmsg = &BKM_card_msg;
433 cs->irq_func = &bkm_interrupt_ipac;
434
435 printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
436 CardType[card->typ],
437 sct_quadro_subtypes[cs->subtyp],
438 readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
439 return (1);
440 }
mah project overlay