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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / infiniband / hw / nes / nes_hw.c
blob496655e176b83f753ca1f47a488260250c4bc880
1 /*
2 * Copyright (c) 2006 - 2008 NetEffect, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/if_vlan.h>
41
42 #include "nes.h"
43
44 u32 crit_err_count = 0;
45 u32 int_mod_timer_init;
46 u32 int_mod_cq_depth_256;
47 u32 int_mod_cq_depth_128;
48 u32 int_mod_cq_depth_32;
49 u32 int_mod_cq_depth_24;
50 u32 int_mod_cq_depth_16;
51 u32 int_mod_cq_depth_4;
52 u32 int_mod_cq_depth_1;
53
54 #include "nes_cm.h"
55
56
57 #ifdef CONFIG_INFINIBAND_NES_DEBUG
58 static unsigned char *nes_iwarp_state_str[] = {
59 "Non-Existant",
60 "Idle",
61 "RTS",
62 "Closing",
63 "RSVD1",
64 "Terminate",
65 "Error",
66 "RSVD2",
67 };
68
69 static unsigned char *nes_tcp_state_str[] = {
70 "Non-Existant",
71 "Closed",
72 "Listen",
73 "SYN Sent",
74 "SYN Rcvd",
75 "Established",
76 "Close Wait",
77 "FIN Wait 1",
78 "Closing",
79 "Last Ack",
80 "FIN Wait 2",
81 "Time Wait",
82 "RSVD1",
83 "RSVD2",
84 "RSVD3",
85 "RSVD4",
86 };
87 #endif
88
89
90 /**
91 * nes_nic_init_timer_defaults
92 */
93 void nes_nic_init_timer_defaults(struct nes_device *nesdev, u8 jumbomode)
94 {
95 unsigned long flags;
96 struct nes_adapter *nesadapter = nesdev->nesadapter;
97 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
98
99 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
100
101 shared_timer->timer_in_use_min = NES_NIC_FAST_TIMER_LOW;
102 shared_timer->timer_in_use_max = NES_NIC_FAST_TIMER_HIGH;
103 if (jumbomode) {
104 shared_timer->threshold_low = DEFAULT_JUMBO_NES_QL_LOW;
105 shared_timer->threshold_target = DEFAULT_JUMBO_NES_QL_TARGET;
106 shared_timer->threshold_high = DEFAULT_JUMBO_NES_QL_HIGH;
107 } else {
108 shared_timer->threshold_low = DEFAULT_NES_QL_LOW;
109 shared_timer->threshold_target = DEFAULT_NES_QL_TARGET;
110 shared_timer->threshold_high = DEFAULT_NES_QL_HIGH;
111 }
112
113 /* todo use netdev->mtu to set thresholds */
114 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
115 }
116
117
118 /**
119 * nes_nic_init_timer
120 */
121 static void nes_nic_init_timer(struct nes_device *nesdev)
122 {
123 unsigned long flags;
124 struct nes_adapter *nesadapter = nesdev->nesadapter;
125 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
126
127 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
128
129 if (shared_timer->timer_in_use_old == 0) {
130 nesdev->deepcq_count = 0;
131 shared_timer->timer_direction_upward = 0;
132 shared_timer->timer_direction_downward = 0;
133 shared_timer->timer_in_use = NES_NIC_FAST_TIMER;
134 shared_timer->timer_in_use_old = 0;
135
136 }
137 if (shared_timer->timer_in_use != shared_timer->timer_in_use_old) {
138 shared_timer->timer_in_use_old = shared_timer->timer_in_use;
139 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL,
140 0x80000000 | ((u32)(shared_timer->timer_in_use*8)));
141 }
142 /* todo use netdev->mtu to set thresholds */
143 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
144 }
145
146
147 /**
148 * nes_nic_tune_timer
149 */
150 static void nes_nic_tune_timer(struct nes_device *nesdev)
151 {
152 unsigned long flags;
153 struct nes_adapter *nesadapter = nesdev->nesadapter;
154 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
155 u16 cq_count = nesdev->currcq_count;
156
157 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
158
159 if (shared_timer->cq_count_old <= cq_count)
160 shared_timer->cq_direction_downward = 0;
161 else
162 shared_timer->cq_direction_downward++;
163 shared_timer->cq_count_old = cq_count;
164 if (shared_timer->cq_direction_downward > NES_NIC_CQ_DOWNWARD_TREND) {
165 if (cq_count <= shared_timer->threshold_low &&
166 shared_timer->threshold_low > 4) {
167 shared_timer->threshold_low = shared_timer->threshold_low/2;
168 shared_timer->cq_direction_downward=0;
169 nesdev->currcq_count = 0;
170 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
171 return;
172 }
173 }
174
175 if (cq_count > 1) {
176 nesdev->deepcq_count += cq_count;
177 if (cq_count <= shared_timer->threshold_low) { /* increase timer gently */
178 shared_timer->timer_direction_upward++;
179 shared_timer->timer_direction_downward = 0;
180 } else if (cq_count <= shared_timer->threshold_target) { /* balanced */
181 shared_timer->timer_direction_upward = 0;
182 shared_timer->timer_direction_downward = 0;
183 } else if (cq_count <= shared_timer->threshold_high) { /* decrease timer gently */
184 shared_timer->timer_direction_downward++;
185 shared_timer->timer_direction_upward = 0;
186 } else if (cq_count <= (shared_timer->threshold_high) * 2) {
187 shared_timer->timer_in_use -= 2;
188 shared_timer->timer_direction_upward = 0;
189 shared_timer->timer_direction_downward++;
190 } else {
191 shared_timer->timer_in_use -= 4;
192 shared_timer->timer_direction_upward = 0;
193 shared_timer->timer_direction_downward++;
194 }
195
196 if (shared_timer->timer_direction_upward > 3 ) { /* using history */
197 shared_timer->timer_in_use += 3;
198 shared_timer->timer_direction_upward = 0;
199 shared_timer->timer_direction_downward = 0;
200 }
201 if (shared_timer->timer_direction_downward > 5) { /* using history */
202 shared_timer->timer_in_use -= 4 ;
203 shared_timer->timer_direction_downward = 0;
204 shared_timer->timer_direction_upward = 0;
205 }
206 }
207
208 /* boundary checking */
209 if (shared_timer->timer_in_use > NES_NIC_FAST_TIMER_HIGH)
210 shared_timer->timer_in_use = NES_NIC_FAST_TIMER_HIGH;
211 else if (shared_timer->timer_in_use < NES_NIC_FAST_TIMER_LOW) {
212 shared_timer->timer_in_use = NES_NIC_FAST_TIMER_LOW;
213 }
214
215 nesdev->currcq_count = 0;
216
217 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
218 }
219
220
221 /**
222 * nes_init_adapter - initialize adapter
223 */
224 struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
225 struct nes_adapter *nesadapter = NULL;
226 unsigned long num_pds;
227 u32 u32temp;
228 u32 port_count;
229 u16 max_rq_wrs;
230 u16 max_sq_wrs;
231 u32 max_mr;
232 u32 max_256pbl;
233 u32 max_4kpbl;
234 u32 max_qp;
235 u32 max_irrq;
236 u32 max_cq;
237 u32 hte_index_mask;
238 u32 adapter_size;
239 u32 arp_table_size;
240 u16 vendor_id;
241 u8 OneG_Mode;
242 u8 func_index;
243
244 /* search the list of existing adapters */
245 list_for_each_entry(nesadapter, &nes_adapter_list, list) {
246 nes_debug(NES_DBG_INIT, "Searching Adapter list for PCI devfn = 0x%X,"
247 " adapter PCI slot/bus = %u/%u, pci devices PCI slot/bus = %u/%u, .\n",
248 nesdev->pcidev->devfn,
249 PCI_SLOT(nesadapter->devfn),
250 nesadapter->bus_number,
251 PCI_SLOT(nesdev->pcidev->devfn),
252 nesdev->pcidev->bus->number );
253 if ((PCI_SLOT(nesadapter->devfn) == PCI_SLOT(nesdev->pcidev->devfn)) &&
254 (nesadapter->bus_number == nesdev->pcidev->bus->number)) {
255 nesadapter->ref_count++;
256 return nesadapter;
257 }
258 }
259
260 /* no adapter found */
261 num_pds = pci_resource_len(nesdev->pcidev, BAR_1) >> PAGE_SHIFT;
262 if ((hw_rev != NE020_REV) && (hw_rev != NE020_REV1)) {
263 nes_debug(NES_DBG_INIT, "NE020 driver detected unknown hardware revision 0x%x\n",
264 hw_rev);
265 return NULL;
266 }
267
268 nes_debug(NES_DBG_INIT, "Determine Soft Reset, QP_control=0x%x, CPU0=0x%x, CPU1=0x%x, CPU2=0x%x\n",
269 nes_read_indexed(nesdev, NES_IDX_QP_CONTROL + PCI_FUNC(nesdev->pcidev->devfn) * 8),
270 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS),
271 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS + 4),
272 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS + 8));
273
274 nes_debug(NES_DBG_INIT, "Reset and init NE020\n");
275
276
277 if ((port_count = nes_reset_adapter_ne020(nesdev, &OneG_Mode)) == 0)
278 return NULL;
279 if (nes_init_serdes(nesdev, hw_rev, port_count, OneG_Mode))
280 return NULL;
281 nes_init_csr_ne020(nesdev, hw_rev, port_count);
282
283 max_qp = nes_read_indexed(nesdev, NES_IDX_QP_CTX_SIZE);
284 nes_debug(NES_DBG_INIT, "QP_CTX_SIZE=%u\n", max_qp);
285
286 u32temp = nes_read_indexed(nesdev, NES_IDX_QUAD_HASH_TABLE_SIZE);
287 if (max_qp > ((u32)1 << (u32temp & 0x001f))) {
288 nes_debug(NES_DBG_INIT, "Reducing Max QPs to %u due to hash table size = 0x%08X\n",
289 max_qp, u32temp);
290 max_qp = (u32)1 << (u32temp & 0x001f);
291 }
292
293 hte_index_mask = ((u32)1 << ((u32temp & 0x001f)+1))-1;
294 nes_debug(NES_DBG_INIT, "Max QP = %u, hte_index_mask = 0x%08X.\n",
295 max_qp, hte_index_mask);
296
297 u32temp = nes_read_indexed(nesdev, NES_IDX_IRRQ_COUNT);
298
299 max_irrq = 1 << (u32temp & 0x001f);
300
301 if (max_qp > max_irrq) {
302 max_qp = max_irrq;
303 nes_debug(NES_DBG_INIT, "Reducing Max QPs to %u due to Available Q1s.\n",
304 max_qp);
305 }
306
307 /* there should be no reason to allocate more pds than qps */
308 if (num_pds > max_qp)
309 num_pds = max_qp;
310
311 u32temp = nes_read_indexed(nesdev, NES_IDX_MRT_SIZE);
312 max_mr = (u32)8192 << (u32temp & 0x7);
313
314 u32temp = nes_read_indexed(nesdev, NES_IDX_PBL_REGION_SIZE);
315 max_256pbl = (u32)1 << (u32temp & 0x0000001f);
316 max_4kpbl = (u32)1 << ((u32temp >> 16) & 0x0000001f);
317 max_cq = nes_read_indexed(nesdev, NES_IDX_CQ_CTX_SIZE);
318
319 u32temp = nes_read_indexed(nesdev, NES_IDX_ARP_CACHE_SIZE);
320 arp_table_size = 1 << u32temp;
321
322 adapter_size = (sizeof(struct nes_adapter) +
323 (sizeof(unsigned long)-1)) & (~(sizeof(unsigned long)-1));
324 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_qp);
325 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_mr);
326 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_cq);
327 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(num_pds);
328 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(arp_table_size);
329 adapter_size += sizeof(struct nes_qp **) * max_qp;
330
331 /* allocate a new adapter struct */
332 nesadapter = kzalloc(adapter_size, GFP_KERNEL);
333 if (nesadapter == NULL) {
334 return NULL;
335 }
336
337 nes_debug(NES_DBG_INIT, "Allocating new nesadapter @ %p, size = %u (actual size = %u).\n",
338 nesadapter, (u32)sizeof(struct nes_adapter), adapter_size);
339
340 /* populate the new nesadapter */
341 nesadapter->devfn = nesdev->pcidev->devfn;
342 nesadapter->bus_number = nesdev->pcidev->bus->number;
343 nesadapter->ref_count = 1;
344 nesadapter->timer_int_req = 0xffff0000;
345 nesadapter->OneG_Mode = OneG_Mode;
346 nesadapter->doorbell_start = nesdev->doorbell_region;
347
348 /* nesadapter->tick_delta = clk_divisor; */
349 nesadapter->hw_rev = hw_rev;
350 nesadapter->port_count = port_count;
351
352 nesadapter->max_qp = max_qp;
353 nesadapter->hte_index_mask = hte_index_mask;
354 nesadapter->max_irrq = max_irrq;
355 nesadapter->max_mr = max_mr;
356 nesadapter->max_256pbl = max_256pbl - 1;
357 nesadapter->max_4kpbl = max_4kpbl - 1;
358 nesadapter->max_cq = max_cq;
359 nesadapter->free_256pbl = max_256pbl - 1;
360 nesadapter->free_4kpbl = max_4kpbl - 1;
361 nesadapter->max_pd = num_pds;
362 nesadapter->arp_table_size = arp_table_size;
363
364 nesadapter->et_pkt_rate_low = NES_TIMER_ENABLE_LIMIT;
365 if (nes_drv_opt & NES_DRV_OPT_DISABLE_INT_MOD) {
366 nesadapter->et_use_adaptive_rx_coalesce = 0;
367 nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT;
368 nesadapter->et_rx_coalesce_usecs_irq = interrupt_mod_interval;
369 } else {
370 nesadapter->et_use_adaptive_rx_coalesce = 1;
371 nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT_DYNAMIC;
372 nesadapter->et_rx_coalesce_usecs_irq = 0;
373 printk(PFX "%s: Using Adaptive Interrupt Moderation\n", __FUNCTION__);
374 }
375 /* Setup and enable the periodic timer */
376 if (nesadapter->et_rx_coalesce_usecs_irq)
377 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x80000000 |
378 ((u32)(nesadapter->et_rx_coalesce_usecs_irq * 8)));
379 else
380 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x00000000);
381
382 nesadapter->base_pd = 1;
383
384 nesadapter->device_cap_flags =
385 IB_DEVICE_ZERO_STAG | IB_DEVICE_SEND_W_INV | IB_DEVICE_MEM_WINDOW;
386
387 nesadapter->allocated_qps = (unsigned long *)&(((unsigned char *)nesadapter)
388 [(sizeof(struct nes_adapter)+(sizeof(unsigned long)-1))&(~(sizeof(unsigned long)-1))]);
389 nesadapter->allocated_cqs = &nesadapter->allocated_qps[BITS_TO_LONGS(max_qp)];
390 nesadapter->allocated_mrs = &nesadapter->allocated_cqs[BITS_TO_LONGS(max_cq)];
391 nesadapter->allocated_pds = &nesadapter->allocated_mrs[BITS_TO_LONGS(max_mr)];
392 nesadapter->allocated_arps = &nesadapter->allocated_pds[BITS_TO_LONGS(num_pds)];
393 nesadapter->qp_table = (struct nes_qp **)(&nesadapter->allocated_arps[BITS_TO_LONGS(arp_table_size)]);
394
395
396 /* mark the usual suspect QPs and CQs as in use */
397 for (u32temp = 0; u32temp < NES_FIRST_QPN; u32temp++) {
398 set_bit(u32temp, nesadapter->allocated_qps);
399 set_bit(u32temp, nesadapter->allocated_cqs);
400 }
401
402 for (u32temp = 0; u32temp < 20; u32temp++)
403 set_bit(u32temp, nesadapter->allocated_pds);
404 u32temp = nes_read_indexed(nesdev, NES_IDX_QP_MAX_CFG_SIZES);
405
406 max_rq_wrs = ((u32temp >> 8) & 3);
407 switch (max_rq_wrs) {
408 case 0:
409 max_rq_wrs = 4;
410 break;
411 case 1:
412 max_rq_wrs = 16;
413 break;
414 case 2:
415 max_rq_wrs = 32;
416 break;
417 case 3:
418 max_rq_wrs = 512;
419 break;
420 }
421
422 max_sq_wrs = (u32temp & 3);
423 switch (max_sq_wrs) {
424 case 0:
425 max_sq_wrs = 4;
426 break;
427 case 1:
428 max_sq_wrs = 16;
429 break;
430 case 2:
431 max_sq_wrs = 32;
432 break;
433 case 3:
434 max_sq_wrs = 512;
435 break;
436 }
437 nesadapter->max_qp_wr = min(max_rq_wrs, max_sq_wrs);
438 nesadapter->max_irrq_wr = (u32temp >> 16) & 3;
439
440 nesadapter->max_sge = 4;
441 nesadapter->max_cqe = 32767;
442
443 if (nes_read_eeprom_values(nesdev, nesadapter)) {
444 printk(KERN_ERR PFX "Unable to read EEPROM data.\n");
445 kfree(nesadapter);
446 return NULL;
447 }
448
449 u32temp = nes_read_indexed(nesdev, NES_IDX_TCP_TIMER_CONFIG);
450 nes_write_indexed(nesdev, NES_IDX_TCP_TIMER_CONFIG,
451 (u32temp & 0xff000000) | (nesadapter->tcp_timer_core_clk_divisor & 0x00ffffff));
452
453 /* setup port configuration */
454 if (nesadapter->port_count == 1) {
455 u32temp = 0x00000000;
456 if (nes_drv_opt & NES_DRV_OPT_DUAL_LOGICAL_PORT)
457 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000002);
458 else
459 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000003);
460 } else {
461 if (nesadapter->port_count == 2)
462 u32temp = 0x00000044;
463 else
464 u32temp = 0x000000e4;
465 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000003);
466 }
467
468 nes_write_indexed(nesdev, NES_IDX_NIC_LOGPORT_TO_PHYPORT, u32temp);
469 nes_debug(NES_DBG_INIT, "Probe time, LOG2PHY=%u\n",
470 nes_read_indexed(nesdev, NES_IDX_NIC_LOGPORT_TO_PHYPORT));
471
472 spin_lock_init(&nesadapter->resource_lock);
473 spin_lock_init(&nesadapter->phy_lock);
474 spin_lock_init(&nesadapter->pbl_lock);
475 spin_lock_init(&nesadapter->periodic_timer_lock);
476
477 INIT_LIST_HEAD(&nesadapter->nesvnic_list[0]);
478 INIT_LIST_HEAD(&nesadapter->nesvnic_list[1]);
479 INIT_LIST_HEAD(&nesadapter->nesvnic_list[2]);
480 INIT_LIST_HEAD(&nesadapter->nesvnic_list[3]);
481
482 if ((!nesadapter->OneG_Mode) && (nesadapter->port_count == 2)) {
483 u32 pcs_control_status0, pcs_control_status1;
484 u32 reset_value;
485 u32 i = 0;
486 u32 int_cnt = 0;
487 u32 ext_cnt = 0;
488 unsigned long flags;
489 u32 j = 0;
490
491 pcs_control_status0 = nes_read_indexed(nesdev,
492 NES_IDX_PHY_PCS_CONTROL_STATUS0);
493 pcs_control_status1 = nes_read_indexed(nesdev,
494 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
495
496 for (i = 0; i < NES_MAX_LINK_CHECK; i++) {
497 pcs_control_status0 = nes_read_indexed(nesdev,
498 NES_IDX_PHY_PCS_CONTROL_STATUS0);
499 pcs_control_status1 = nes_read_indexed(nesdev,
500 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
501 if ((0x0F000100 == (pcs_control_status0 & 0x0F000100))
502 || (0x0F000100 == (pcs_control_status1 & 0x0F000100)))
503 int_cnt++;
504 msleep(1);
505 }
506 if (int_cnt > 1) {
507 spin_lock_irqsave(&nesadapter->phy_lock, flags);
508 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088);
509 mh_detected++;
510 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
511 reset_value |= 0x0000003d;
512 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
513
514 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
515 & 0x00000040) != 0x00000040) && (j++ < 5000));
516 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
517
518 pcs_control_status0 = nes_read_indexed(nesdev,
519 NES_IDX_PHY_PCS_CONTROL_STATUS0);
520 pcs_control_status1 = nes_read_indexed(nesdev,
521 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
522
523 for (i = 0; i < NES_MAX_LINK_CHECK; i++) {
524 pcs_control_status0 = nes_read_indexed(nesdev,
525 NES_IDX_PHY_PCS_CONTROL_STATUS0);
526 pcs_control_status1 = nes_read_indexed(nesdev,
527 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
528 if ((0x0F000100 == (pcs_control_status0 & 0x0F000100))
529 || (0x0F000100 == (pcs_control_status1 & 0x0F000100))) {
530 if (++ext_cnt > int_cnt) {
531 spin_lock_irqsave(&nesadapter->phy_lock, flags);
532 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1,
533 0x0000F0C8);
534 mh_detected++;
535 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
536 reset_value |= 0x0000003d;
537 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
538
539 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
540 & 0x00000040) != 0x00000040) && (j++ < 5000));
541 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
542 break;
543 }
544 }
545 msleep(1);
546 }
547 }
548 }
549
550 if (nesadapter->hw_rev == NE020_REV) {
551 init_timer(&nesadapter->mh_timer);
552 nesadapter->mh_timer.function = nes_mh_fix;
553 nesadapter->mh_timer.expires = jiffies + (HZ/5); /* 1 second */
554 nesadapter->mh_timer.data = (unsigned long)nesdev;
555 add_timer(&nesadapter->mh_timer);
556 } else {
557 nes_write32(nesdev->regs+NES_INTF_INT_STAT, 0x0f000000);
558 }
559
560 init_timer(&nesadapter->lc_timer);
561 nesadapter->lc_timer.function = nes_clc;
562 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
563 nesadapter->lc_timer.data = (unsigned long)nesdev;
564 add_timer(&nesadapter->lc_timer);
565
566 list_add_tail(&nesadapter->list, &nes_adapter_list);
567
568 for (func_index = 0; func_index < 8; func_index++) {
569 pci_bus_read_config_word(nesdev->pcidev->bus,
570 PCI_DEVFN(PCI_SLOT(nesdev->pcidev->devfn),
571 func_index), 0, &vendor_id);
572 if (vendor_id == 0xffff)
573 break;
574 }
575 nes_debug(NES_DBG_INIT, "%s %d functions found for %s.\n", __FUNCTION__,
576 func_index, pci_name(nesdev->pcidev));
577 nesadapter->adapter_fcn_count = func_index;
578
579 return nesadapter;
580 }
581
582
583 /**
584 * nes_reset_adapter_ne020
585 */
586 unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_Mode)
587 {
588 u32 port_count;
589 u32 u32temp;
590 u32 i;
591
592 u32temp = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
593 port_count = ((u32temp & 0x00000300) >> 8) + 1;
594 /* TODO: assuming that both SERDES are set the same for now */
595 *OneG_Mode = (u32temp & 0x00003c00) ? 0 : 1;
596 nes_debug(NES_DBG_INIT, "Initial Software Reset = 0x%08X, port_count=%u\n",
597 u32temp, port_count);
598 if (*OneG_Mode)
599 nes_debug(NES_DBG_INIT, "Running in 1G mode.\n");
600 u32temp &= 0xff00ffc0;
601 switch (port_count) {
602 case 1:
603 u32temp |= 0x00ee0000;
604 break;
605 case 2:
606 u32temp |= 0x00cc0000;
607 break;
608 case 4:
609 u32temp |= 0x00000000;
610 break;
611 default:
612 return 0;
613 break;
614 }
615
616 /* check and do full reset if needed */
617 if (nes_read_indexed(nesdev, NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8))) {
618 nes_debug(NES_DBG_INIT, "Issuing Full Soft reset = 0x%08X\n", u32temp | 0xd);
619 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, u32temp | 0xd);
620
621 i = 0;
622 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000)
623 mdelay(1);
624 if (i >= 10000) {
625 nes_debug(NES_DBG_INIT, "Did not see full soft reset done.\n");
626 return 0;
627 }
628
629 i = 0;
630 while ((nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS) != 0x80) && i++ < 10000)
631 mdelay(1);
632 if (i >= 10000) {
633 printk(KERN_ERR PFX "Internal CPU not ready, status = %02X\n",
634 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS));
635 return 0;
636 }
637 }
638
639 /* port reset */
640 switch (port_count) {
641 case 1:
642 u32temp |= 0x00ee0010;
643 break;
644 case 2:
645 u32temp |= 0x00cc0030;
646 break;
647 case 4:
648 u32temp |= 0x00000030;
649 break;
650 }
651
652 nes_debug(NES_DBG_INIT, "Issuing Port Soft reset = 0x%08X\n", u32temp | 0xd);
653 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, u32temp | 0xd);
654
655 i = 0;
656 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000)
657 mdelay(1);
658 if (i >= 10000) {
659 nes_debug(NES_DBG_INIT, "Did not see port soft reset done.\n");
660 return 0;
661 }
662
663 /* serdes 0 */
664 i = 0;
665 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0)
666 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
667 mdelay(1);
668 if (i >= 5000) {
669 nes_debug(NES_DBG_INIT, "Serdes 0 not ready, status=%x\n", u32temp);
670 return 0;
671 }
672
673 /* serdes 1 */
674 if (port_count > 1) {
675 i = 0;
676 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1)
677 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
678 mdelay(1);
679 if (i >= 5000) {
680 nes_debug(NES_DBG_INIT, "Serdes 1 not ready, status=%x\n", u32temp);
681 return 0;
682 }
683 }
684
685 return port_count;
686 }
687
688
689 /**
690 * nes_init_serdes
691 */
692 int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count, u8 OneG_Mode)
693 {
694 int i;
695 u32 u32temp;
696
697 if (hw_rev != NE020_REV) {
698 /* init serdes 0 */
699
700 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
701 if (!OneG_Mode)
702 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000);
703 if (port_count > 1) {
704 /* init serdes 1 */
705 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
706 if (!OneG_Mode)
707 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000);
708 }
709 } else {
710 /* init serdes 0 */
711 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
712 i = 0;
713 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0)
714 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
715 mdelay(1);
716 if (i >= 5000) {
717 nes_debug(NES_DBG_PHY, "Init: serdes 0 not ready, status=%x\n", u32temp);
718 return 1;
719 }
720 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
721 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
722 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
723 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
724 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
725 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
726 if (OneG_Mode)
727 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
728 else
729 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
730
731 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
732 if (port_count > 1) {
733 /* init serdes 1 */
734 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x00000048);
735 i = 0;
736 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1)
737 & 0x0000000f)) != 0x0000000f) && (i++ < 5000))
738 mdelay(1);
739 if (i >= 5000) {
740 printk("%s: Init: serdes 1 not ready, status=%x\n", __FUNCTION__, u32temp);
741 /* return 1; */
742 }
743 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x000bdef7);
744 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE1, 0x9ce73000);
745 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE1, 0x0ff00000);
746 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET1, 0x00000000);
747 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS1, 0x00000000);
748 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1, 0x00000000);
749 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL1, 0xf0002222);
750 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000ff);
751 }
752 }
753 return 0;
754 }
755
756
757 /**
758 * nes_init_csr_ne020
759 * Initialize registers for ne020 hardware
760 */
761 void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count)
762 {
763 u32 u32temp;
764
765 nes_debug(NES_DBG_INIT, "port_count=%d\n", port_count);
766
767 nes_write_indexed(nesdev, 0x000001E4, 0x00000007);
768 /* nes_write_indexed(nesdev, 0x000001E8, 0x000208C4); */
769 nes_write_indexed(nesdev, 0x000001E8, 0x00020874);
770 nes_write_indexed(nesdev, 0x000001D8, 0x00048002);
771 /* nes_write_indexed(nesdev, 0x000001D8, 0x0004B002); */
772 nes_write_indexed(nesdev, 0x000001FC, 0x00050005);
773 nes_write_indexed(nesdev, 0x00000600, 0x55555555);
774 nes_write_indexed(nesdev, 0x00000604, 0x55555555);
775
776 /* TODO: move these MAC register settings to NIC bringup */
777 nes_write_indexed(nesdev, 0x00002000, 0x00000001);
778 nes_write_indexed(nesdev, 0x00002004, 0x00000001);
779 nes_write_indexed(nesdev, 0x00002008, 0x0000FFFF);
780 nes_write_indexed(nesdev, 0x0000200C, 0x00000001);
781 nes_write_indexed(nesdev, 0x00002010, 0x000003c1);
782 nes_write_indexed(nesdev, 0x0000201C, 0x75345678);
783 if (port_count > 1) {
784 nes_write_indexed(nesdev, 0x00002200, 0x00000001);
785 nes_write_indexed(nesdev, 0x00002204, 0x00000001);
786 nes_write_indexed(nesdev, 0x00002208, 0x0000FFFF);
787 nes_write_indexed(nesdev, 0x0000220C, 0x00000001);
788 nes_write_indexed(nesdev, 0x00002210, 0x000003c1);
789 nes_write_indexed(nesdev, 0x0000221C, 0x75345678);
790 nes_write_indexed(nesdev, 0x00000908, 0x20000001);
791 }
792 if (port_count > 2) {
793 nes_write_indexed(nesdev, 0x00002400, 0x00000001);
794 nes_write_indexed(nesdev, 0x00002404, 0x00000001);
795 nes_write_indexed(nesdev, 0x00002408, 0x0000FFFF);
796 nes_write_indexed(nesdev, 0x0000240C, 0x00000001);
797 nes_write_indexed(nesdev, 0x00002410, 0x000003c1);
798 nes_write_indexed(nesdev, 0x0000241C, 0x75345678);
799 nes_write_indexed(nesdev, 0x00000910, 0x20000001);
800
801 nes_write_indexed(nesdev, 0x00002600, 0x00000001);
802 nes_write_indexed(nesdev, 0x00002604, 0x00000001);
803 nes_write_indexed(nesdev, 0x00002608, 0x0000FFFF);
804 nes_write_indexed(nesdev, 0x0000260C, 0x00000001);
805 nes_write_indexed(nesdev, 0x00002610, 0x000003c1);
806 nes_write_indexed(nesdev, 0x0000261C, 0x75345678);
807 nes_write_indexed(nesdev, 0x00000918, 0x20000001);
808 }
809
810 nes_write_indexed(nesdev, 0x00005000, 0x00018000);
811 /* nes_write_indexed(nesdev, 0x00005000, 0x00010000); */
812 nes_write_indexed(nesdev, 0x00005004, 0x00020001);
813 nes_write_indexed(nesdev, 0x00005008, 0x1F1F1F1F);
814 nes_write_indexed(nesdev, 0x00005010, 0x1F1F1F1F);
815 nes_write_indexed(nesdev, 0x00005018, 0x1F1F1F1F);
816 nes_write_indexed(nesdev, 0x00005020, 0x1F1F1F1F);
817 nes_write_indexed(nesdev, 0x00006090, 0xFFFFFFFF);
818
819 /* TODO: move this to code, get from EEPROM */
820 nes_write_indexed(nesdev, 0x00000900, 0x20000001);
821 nes_write_indexed(nesdev, 0x000060C0, 0x0000028e);
822 nes_write_indexed(nesdev, 0x000060C8, 0x00000020);
823 //
824 nes_write_indexed(nesdev, 0x000001EC, 0x7b2625a0);
825 /* nes_write_indexed(nesdev, 0x000001EC, 0x5f2625a0); */
826
827 if (hw_rev != NE020_REV) {
828 u32temp = nes_read_indexed(nesdev, 0x000008e8);
829 u32temp |= 0x80000000;
830 nes_write_indexed(nesdev, 0x000008e8, u32temp);
831 u32temp = nes_read_indexed(nesdev, 0x000021f8);
832 u32temp &= 0x7fffffff;
833 u32temp |= 0x7fff0010;
834 nes_write_indexed(nesdev, 0x000021f8, u32temp);
835 }
836 }
837
838
839 /**
840 * nes_destroy_adapter - destroy the adapter structure
841 */
842 void nes_destroy_adapter(struct nes_adapter *nesadapter)
843 {
844 struct nes_adapter *tmp_adapter;
845
846 list_for_each_entry(tmp_adapter, &nes_adapter_list, list) {
847 nes_debug(NES_DBG_SHUTDOWN, "Nes Adapter list entry = 0x%p.\n",
848 tmp_adapter);
849 }
850
851 nesadapter->ref_count--;
852 if (!nesadapter->ref_count) {
853 if (nesadapter->hw_rev == NE020_REV) {
854 del_timer(&nesadapter->mh_timer);
855 }
856 del_timer(&nesadapter->lc_timer);
857
858 list_del(&nesadapter->list);
859 kfree(nesadapter);
860 }
861 }
862
863
864 /**
865 * nes_init_cqp
866 */
867 int nes_init_cqp(struct nes_device *nesdev)
868 {
869 struct nes_adapter *nesadapter = nesdev->nesadapter;
870 struct nes_hw_cqp_qp_context *cqp_qp_context;
871 struct nes_hw_cqp_wqe *cqp_wqe;
872 struct nes_hw_ceq *ceq;
873 struct nes_hw_ceq *nic_ceq;
874 struct nes_hw_aeq *aeq;
875 void *vmem;
876 dma_addr_t pmem;
877 u32 count=0;
878 u32 cqp_head;
879 u64 u64temp;
880 u32 u32temp;
881
882 /* allocate CQP memory */
883 /* Need to add max_cq to the aeq size once cq overflow checking is added back */
884 /* SQ is 512 byte aligned, others are 256 byte aligned */
885 nesdev->cqp_mem_size = 512 +
886 (sizeof(struct nes_hw_cqp_wqe) * NES_CQP_SQ_SIZE) +
887 (sizeof(struct nes_hw_cqe) * NES_CCQ_SIZE) +
888 max(((u32)sizeof(struct nes_hw_ceqe) * NES_CCEQ_SIZE), (u32)256) +
889 max(((u32)sizeof(struct nes_hw_ceqe) * NES_NIC_CEQ_SIZE), (u32)256) +
890 (sizeof(struct nes_hw_aeqe) * nesadapter->max_qp) +
891 sizeof(struct nes_hw_cqp_qp_context);
892
893 nesdev->cqp_vbase = pci_alloc_consistent(nesdev->pcidev, nesdev->cqp_mem_size,
894 &nesdev->cqp_pbase);
895 if (!nesdev->cqp_vbase) {
896 nes_debug(NES_DBG_INIT, "Unable to allocate memory for host descriptor rings\n");
897 return -ENOMEM;
898 }
899 memset(nesdev->cqp_vbase, 0, nesdev->cqp_mem_size);
900
901 /* Allocate a twice the number of CQP requests as the SQ size */
902 nesdev->nes_cqp_requests = kzalloc(sizeof(struct nes_cqp_request) *
903 2 * NES_CQP_SQ_SIZE, GFP_KERNEL);
904 if (nesdev->nes_cqp_requests == NULL) {
905 nes_debug(NES_DBG_INIT, "Unable to allocate memory CQP request entries.\n");
906 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size, nesdev->cqp.sq_vbase,
907 nesdev->cqp.sq_pbase);
908 return -ENOMEM;
909 }
910
911 nes_debug(NES_DBG_INIT, "Allocated CQP structures at %p (phys = %016lX), size = %u.\n",
912 nesdev->cqp_vbase, (unsigned long)nesdev->cqp_pbase, nesdev->cqp_mem_size);
913
914 spin_lock_init(&nesdev->cqp.lock);
915 init_waitqueue_head(&nesdev->cqp.waitq);
916
917 /* Setup Various Structures */
918 vmem = (void *)(((unsigned long)nesdev->cqp_vbase + (512 - 1)) &
919 ~(unsigned long)(512 - 1));
920 pmem = (dma_addr_t)(((unsigned long long)nesdev->cqp_pbase + (512 - 1)) &
921 ~(unsigned long long)(512 - 1));
922
923 nesdev->cqp.sq_vbase = vmem;
924 nesdev->cqp.sq_pbase = pmem;
925 nesdev->cqp.sq_size = NES_CQP_SQ_SIZE;
926 nesdev->cqp.sq_head = 0;
927 nesdev->cqp.sq_tail = 0;
928 nesdev->cqp.qp_id = PCI_FUNC(nesdev->pcidev->devfn);
929
930 vmem += (sizeof(struct nes_hw_cqp_wqe) * nesdev->cqp.sq_size);
931 pmem += (sizeof(struct nes_hw_cqp_wqe) * nesdev->cqp.sq_size);
932
933 nesdev->ccq.cq_vbase = vmem;
934 nesdev->ccq.cq_pbase = pmem;
935 nesdev->ccq.cq_size = NES_CCQ_SIZE;
936 nesdev->ccq.cq_head = 0;
937 nesdev->ccq.ce_handler = nes_cqp_ce_handler;
938 nesdev->ccq.cq_number = PCI_FUNC(nesdev->pcidev->devfn);
939
940 vmem += (sizeof(struct nes_hw_cqe) * nesdev->ccq.cq_size);
941 pmem += (sizeof(struct nes_hw_cqe) * nesdev->ccq.cq_size);
942
943 nesdev->ceq_index = PCI_FUNC(nesdev->pcidev->devfn);
944 ceq = &nesadapter->ceq[nesdev->ceq_index];
945 ceq->ceq_vbase = vmem;
946 ceq->ceq_pbase = pmem;
947 ceq->ceq_size = NES_CCEQ_SIZE;
948 ceq->ceq_head = 0;
949
950 vmem += max(((u32)sizeof(struct nes_hw_ceqe) * ceq->ceq_size), (u32)256);
951 pmem += max(((u32)sizeof(struct nes_hw_ceqe) * ceq->ceq_size), (u32)256);
952
953 nesdev->nic_ceq_index = PCI_FUNC(nesdev->pcidev->devfn) + 8;
954 nic_ceq = &nesadapter->ceq[nesdev->nic_ceq_index];
955 nic_ceq->ceq_vbase = vmem;
956 nic_ceq->ceq_pbase = pmem;
957 nic_ceq->ceq_size = NES_NIC_CEQ_SIZE;
958 nic_ceq->ceq_head = 0;
959
960 vmem += max(((u32)sizeof(struct nes_hw_ceqe) * nic_ceq->ceq_size), (u32)256);
961 pmem += max(((u32)sizeof(struct nes_hw_ceqe) * nic_ceq->ceq_size), (u32)256);
962
963 aeq = &nesadapter->aeq[PCI_FUNC(nesdev->pcidev->devfn)];
964 aeq->aeq_vbase = vmem;
965 aeq->aeq_pbase = pmem;
966 aeq->aeq_size = nesadapter->max_qp;
967 aeq->aeq_head = 0;
968
969 /* Setup QP Context */
970 vmem += (sizeof(struct nes_hw_aeqe) * aeq->aeq_size);
971 pmem += (sizeof(struct nes_hw_aeqe) * aeq->aeq_size);
972
973 cqp_qp_context = vmem;
974 cqp_qp_context->context_words[0] =
975 cpu_to_le32((PCI_FUNC(nesdev->pcidev->devfn) << 12) + (2 << 10));
976 cqp_qp_context->context_words[1] = 0;
977 cqp_qp_context->context_words[2] = cpu_to_le32((u32)nesdev->cqp.sq_pbase);
978 cqp_qp_context->context_words[3] = cpu_to_le32(((u64)nesdev->cqp.sq_pbase) >> 32);
979
980
981 /* Write the address to Create CQP */
982 if ((sizeof(dma_addr_t) > 4)) {
983 nes_write_indexed(nesdev,
984 NES_IDX_CREATE_CQP_HIGH + (PCI_FUNC(nesdev->pcidev->devfn) * 8),
985 ((u64)pmem) >> 32);
986 } else {
987 nes_write_indexed(nesdev,
988 NES_IDX_CREATE_CQP_HIGH + (PCI_FUNC(nesdev->pcidev->devfn) * 8), 0);
989 }
990 nes_write_indexed(nesdev,
991 NES_IDX_CREATE_CQP_LOW + (PCI_FUNC(nesdev->pcidev->devfn) * 8),
992 (u32)pmem);
993
994 INIT_LIST_HEAD(&nesdev->cqp_avail_reqs);
995 INIT_LIST_HEAD(&nesdev->cqp_pending_reqs);
996
997 for (count = 0; count < 2*NES_CQP_SQ_SIZE; count++) {
998 init_waitqueue_head(&nesdev->nes_cqp_requests[count].waitq);
999 list_add_tail(&nesdev->nes_cqp_requests[count].list, &nesdev->cqp_avail_reqs);
1000 }
1001
1002 /* Write Create CCQ WQE */
1003 cqp_head = nesdev->cqp.sq_head++;
1004 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1005 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1006 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1007 (NES_CQP_CREATE_CQ | NES_CQP_CQ_CEQ_VALID |
1008 NES_CQP_CQ_CHK_OVERFLOW | ((u32)nesdev->ccq.cq_size << 16)));
1009 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
1010 (nesdev->ccq.cq_number |
1011 ((u32)nesdev->ceq_index << 16)));
1012 u64temp = (u64)nesdev->ccq.cq_pbase;
1013 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1014 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = 0;
1015 u64temp = (unsigned long)&nesdev->ccq;
1016 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] =
1017 cpu_to_le32((u32)(u64temp >> 1));
1018 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] =
1019 cpu_to_le32(((u32)((u64temp) >> 33)) & 0x7FFFFFFF);
1020 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX] = 0;
1021
1022 /* Write Create CEQ WQE */
1023 cqp_head = nesdev->cqp.sq_head++;
1024 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1025 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1026 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1027 (NES_CQP_CREATE_CEQ + ((u32)nesdev->ceq_index << 8)));
1028 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX, ceq->ceq_size);
1029 u64temp = (u64)ceq->ceq_pbase;
1030 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1031
1032 /* Write Create AEQ WQE */
1033 cqp_head = nesdev->cqp.sq_head++;
1034 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1035 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1036 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1037 (NES_CQP_CREATE_AEQ + ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 8)));
1038 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX, aeq->aeq_size);
1039 u64temp = (u64)aeq->aeq_pbase;
1040 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1041
1042 /* Write Create NIC CEQ WQE */
1043 cqp_head = nesdev->cqp.sq_head++;
1044 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1045 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1046 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1047 (NES_CQP_CREATE_CEQ + ((u32)nesdev->nic_ceq_index << 8)));
1048 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX, nic_ceq->ceq_size);
1049 u64temp = (u64)nic_ceq->ceq_pbase;
1050 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1051
1052 /* Poll until CCQP done */
1053 count = 0;
1054 do {
1055 if (count++ > 1000) {
1056 printk(KERN_ERR PFX "Error creating CQP\n");
1057 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size,
1058 nesdev->cqp_vbase, nesdev->cqp_pbase);
1059 return -1;
1060 }
1061 udelay(10);
1062 } while (!(nes_read_indexed(nesdev,
1063 NES_IDX_QP_CONTROL + (PCI_FUNC(nesdev->pcidev->devfn) * 8)) & (1 << 8)));
1064
1065 nes_debug(NES_DBG_INIT, "CQP Status = 0x%08X\n", nes_read_indexed(nesdev,
1066 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1067
1068 u32temp = 0x04800000;
1069 nes_write32(nesdev->regs+NES_WQE_ALLOC, u32temp | nesdev->cqp.qp_id);
1070
1071 /* wait for the CCQ, CEQ, and AEQ to get created */
1072 count = 0;
1073 do {
1074 if (count++ > 1000) {
1075 printk(KERN_ERR PFX "Error creating CCQ, CEQ, and AEQ\n");
1076 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size,
1077 nesdev->cqp_vbase, nesdev->cqp_pbase);
1078 return -1;
1079 }
1080 udelay(10);
1081 } while (((nes_read_indexed(nesdev,
1082 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15<<8)) != (15<<8)));
1083
1084 /* dump the QP status value */
1085 nes_debug(NES_DBG_INIT, "QP Status = 0x%08X\n", nes_read_indexed(nesdev,
1086 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1087
1088 nesdev->cqp.sq_tail++;
1089
1090 return 0;
1091 }
1092
1093
1094 /**
1095 * nes_destroy_cqp
1096 */
1097 int nes_destroy_cqp(struct nes_device *nesdev)
1098 {
1099 struct nes_hw_cqp_wqe *cqp_wqe;
1100 u32 count = 0;
1101 u32 cqp_head;
1102 unsigned long flags;
1103
1104 do {
1105 if (count++ > 1000)
1106 break;
1107 udelay(10);
1108 } while (!(nesdev->cqp.sq_head == nesdev->cqp.sq_tail));
1109
1110 /* Reset CCQ */
1111 nes_write32(nesdev->regs+NES_CQE_ALLOC, NES_CQE_ALLOC_RESET |
1112 nesdev->ccq.cq_number);
1113
1114 /* Disable device interrupts */
1115 nes_write32(nesdev->regs+NES_INT_MASK, 0x7fffffff);
1116
1117 spin_lock_irqsave(&nesdev->cqp.lock, flags);
1118
1119 /* Destroy the AEQ */
1120 cqp_head = nesdev->cqp.sq_head++;
1121 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1122 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1123 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_AEQ |
1124 ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 8));
1125 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = 0;
1126
1127 /* Destroy the NIC CEQ */
1128 cqp_head = nesdev->cqp.sq_head++;
1129 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1130 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1131 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CEQ |
1132 ((u32)nesdev->nic_ceq_index << 8));
1133
1134 /* Destroy the CEQ */
1135 cqp_head = nesdev->cqp.sq_head++;
1136 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1137 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1138 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CEQ |
1139 (nesdev->ceq_index << 8));
1140
1141 /* Destroy the CCQ */
1142 cqp_head = nesdev->cqp.sq_head++;
1143 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1144 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1145 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CQ);
1146 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->ccq.cq_number |
1147 ((u32)nesdev->ceq_index << 16));
1148
1149 /* Destroy CQP */
1150 cqp_head = nesdev->cqp.sq_head++;
1151 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1152 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1153 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_QP |
1154 NES_CQP_QP_TYPE_CQP);
1155 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->cqp.qp_id);
1156
1157 barrier();
1158 /* Ring doorbell (5 WQEs) */
1159 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x05800000 | nesdev->cqp.qp_id);
1160
1161 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
1162
1163 /* wait for the CCQ, CEQ, and AEQ to get destroyed */
1164 count = 0;
1165 do {
1166 if (count++ > 1000) {
1167 printk(KERN_ERR PFX "Function%d: Error destroying CCQ, CEQ, and AEQ\n",
1168 PCI_FUNC(nesdev->pcidev->devfn));
1169 break;
1170 }
1171 udelay(10);
1172 } while (((nes_read_indexed(nesdev,
1173 NES_IDX_QP_CONTROL + (PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15 << 8)) != 0));
1174
1175 /* dump the QP status value */
1176 nes_debug(NES_DBG_SHUTDOWN, "Function%d: QP Status = 0x%08X\n",
1177 PCI_FUNC(nesdev->pcidev->devfn),
1178 nes_read_indexed(nesdev,
1179 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1180
1181 kfree(nesdev->nes_cqp_requests);
1182
1183 /* Free the control structures */
1184 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size, nesdev->cqp.sq_vbase,
1185 nesdev->cqp.sq_pbase);
1186
1187 return 0;
1188 }
1189
1190
1191 /**
1192 * nes_init_phy
1193 */
1194 int nes_init_phy(struct nes_device *nesdev)
1195 {
1196 struct nes_adapter *nesadapter = nesdev->nesadapter;
1197 u32 counter = 0;
1198 u32 mac_index = nesdev->mac_index;
1199 u32 tx_config;
1200 u16 phy_data;
1201
1202 if (nesadapter->OneG_Mode) {
1203 nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index);
1204 if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_1G) {
1205 printk(PFX "%s: Programming mdc config for 1G\n", __FUNCTION__);
1206 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1207 tx_config |= 0x04;
1208 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1209 }
1210
1211 nes_read_1G_phy_reg(nesdev, 1, nesadapter->phy_index[mac_index], &phy_data);
1212 nes_debug(NES_DBG_PHY, "Phy data from register 1 phy address %u = 0x%X.\n",
1213 nesadapter->phy_index[mac_index], phy_data);
1214 nes_write_1G_phy_reg(nesdev, 23, nesadapter->phy_index[mac_index], 0xb000);
1215
1216 /* Reset the PHY */
1217 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], 0x8000);
1218 udelay(100);
1219 counter = 0;
1220 do {
1221 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data);
1222 nes_debug(NES_DBG_PHY, "Phy data from register 0 = 0x%X.\n", phy_data);
1223 if (counter++ > 100) break;
1224 } while (phy_data & 0x8000);
1225
1226 /* Setting no phy loopback */
1227 phy_data &= 0xbfff;
1228 phy_data |= 0x1140;
1229 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], phy_data);
1230 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data);
1231 nes_debug(NES_DBG_PHY, "Phy data from register 0 = 0x%X.\n", phy_data);
1232
1233 nes_read_1G_phy_reg(nesdev, 0x17, nesadapter->phy_index[mac_index], &phy_data);
1234 nes_debug(NES_DBG_PHY, "Phy data from register 0x17 = 0x%X.\n", phy_data);
1235
1236 nes_read_1G_phy_reg(nesdev, 0x1e, nesadapter->phy_index[mac_index], &phy_data);
1237 nes_debug(NES_DBG_PHY, "Phy data from register 0x1e = 0x%X.\n", phy_data);
1238
1239 /* Setting the interrupt mask */
1240 nes_read_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], &phy_data);
1241 nes_debug(NES_DBG_PHY, "Phy data from register 0x19 = 0x%X.\n", phy_data);
1242 nes_write_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], 0xffee);
1243
1244 nes_read_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], &phy_data);
1245 nes_debug(NES_DBG_PHY, "Phy data from register 0x19 = 0x%X.\n", phy_data);
1246
1247 /* turning on flow control */
1248 nes_read_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], &phy_data);
1249 nes_debug(NES_DBG_PHY, "Phy data from register 0x4 = 0x%X.\n", phy_data);
1250 nes_write_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index],
1251 (phy_data & ~(0x03E0)) | 0xc00);
1252 /* nes_write_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index],
1253 phy_data | 0xc00); */
1254 nes_read_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], &phy_data);
1255 nes_debug(NES_DBG_PHY, "Phy data from register 0x4 = 0x%X.\n", phy_data);
1256
1257 nes_read_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index], &phy_data);
1258 nes_debug(NES_DBG_PHY, "Phy data from register 0x9 = 0x%X.\n", phy_data);
1259 /* Clear Half duplex */
1260 nes_write_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index],
1261 phy_data & ~(0x0100));
1262 nes_read_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index], &phy_data);
1263 nes_debug(NES_DBG_PHY, "Phy data from register 0x9 = 0x%X.\n", phy_data);
1264
1265 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data);
1266 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], phy_data | 0x0300);
1267 } else {
1268 if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_IRIS) {
1269 /* setup 10G MDIO operation */
1270 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1271 tx_config |= 0x14;
1272 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1273 }
1274 }
1275 return 0;
1276 }
1277
1278
1279 /**
1280 * nes_replenish_nic_rq
1281 */
1282 static void nes_replenish_nic_rq(struct nes_vnic *nesvnic)
1283 {
1284 unsigned long flags;
1285 dma_addr_t bus_address;
1286 struct sk_buff *skb;
1287 struct nes_hw_nic_rq_wqe *nic_rqe;
1288 struct nes_hw_nic *nesnic;
1289 struct nes_device *nesdev;
1290 u32 rx_wqes_posted = 0;
1291
1292 nesnic = &nesvnic->nic;
1293 nesdev = nesvnic->nesdev;
1294 spin_lock_irqsave(&nesnic->rq_lock, flags);
1295 if (nesnic->replenishing_rq !=0) {
1296 if (((nesnic->rq_size-1) == atomic_read(&nesvnic->rx_skbs_needed)) &&
1297 (atomic_read(&nesvnic->rx_skb_timer_running) == 0)) {
1298 atomic_set(&nesvnic->rx_skb_timer_running, 1);
1299 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1300 nesvnic->rq_wqes_timer.expires = jiffies + (HZ/2); /* 1/2 second */
1301 add_timer(&nesvnic->rq_wqes_timer);
1302 } else
1303 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1304 return;
1305 }
1306 nesnic->replenishing_rq = 1;
1307 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1308 do {
1309 skb = dev_alloc_skb(nesvnic->max_frame_size);
1310 if (skb) {
1311 skb->dev = nesvnic->netdev;
1312
1313 bus_address = pci_map_single(nesdev->pcidev,
1314 skb->data, nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
1315
1316 nic_rqe = &nesnic->rq_vbase[nesvnic->nic.rq_head];
1317 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_1_0_IDX] =
1318 cpu_to_le32(nesvnic->max_frame_size);
1319 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_3_2_IDX] = 0;
1320 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX] =
1321 cpu_to_le32((u32)bus_address);
1322 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX] =
1323 cpu_to_le32((u32)((u64)bus_address >> 32));
1324 nesnic->rx_skb[nesnic->rq_head] = skb;
1325 nesnic->rq_head++;
1326 nesnic->rq_head &= nesnic->rq_size - 1;
1327 atomic_dec(&nesvnic->rx_skbs_needed);
1328 barrier();
1329 if (++rx_wqes_posted == 255) {
1330 nes_write32(nesdev->regs+NES_WQE_ALLOC, (rx_wqes_posted << 24) | nesnic->qp_id);
1331 rx_wqes_posted = 0;
1332 }
1333 } else {
1334 spin_lock_irqsave(&nesnic->rq_lock, flags);
1335 if (((nesnic->rq_size-1) == atomic_read(&nesvnic->rx_skbs_needed)) &&
1336 (atomic_read(&nesvnic->rx_skb_timer_running) == 0)) {
1337 atomic_set(&nesvnic->rx_skb_timer_running, 1);
1338 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1339 nesvnic->rq_wqes_timer.expires = jiffies + (HZ/2); /* 1/2 second */
1340 add_timer(&nesvnic->rq_wqes_timer);
1341 } else
1342 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1343 break;
1344 }
1345 } while (atomic_read(&nesvnic->rx_skbs_needed));
1346 barrier();
1347 if (rx_wqes_posted)
1348 nes_write32(nesdev->regs+NES_WQE_ALLOC, (rx_wqes_posted << 24) | nesnic->qp_id);
1349 nesnic->replenishing_rq = 0;
1350 }
1351
1352
1353 /**
1354 * nes_rq_wqes_timeout
1355 */
1356 static void nes_rq_wqes_timeout(unsigned long parm)
1357 {
1358 struct nes_vnic *nesvnic = (struct nes_vnic *)parm;
1359 printk("%s: Timer fired.\n", __FUNCTION__);
1360 atomic_set(&nesvnic->rx_skb_timer_running, 0);
1361 if (atomic_read(&nesvnic->rx_skbs_needed))
1362 nes_replenish_nic_rq(nesvnic);
1363 }
1364
1365
1366 /**
1367 * nes_init_nic_qp
1368 */
1369 int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
1370 {
1371 struct nes_hw_cqp_wqe *cqp_wqe;
1372 struct nes_hw_nic_sq_wqe *nic_sqe;
1373 struct nes_hw_nic_qp_context *nic_context;
1374 struct sk_buff *skb;
1375 struct nes_hw_nic_rq_wqe *nic_rqe;
1376 struct nes_vnic *nesvnic = netdev_priv(netdev);
1377 unsigned long flags;
1378 void *vmem;
1379 dma_addr_t pmem;
1380 u64 u64temp;
1381 int ret;
1382 u32 cqp_head;
1383 u32 counter;
1384 u32 wqe_count;
1385 u8 jumbomode=0;
1386
1387 /* Allocate fragment, SQ, RQ, and CQ; Reuse CEQ based on the PCI function */
1388 nesvnic->nic_mem_size = 256 +
1389 (NES_NIC_WQ_SIZE * sizeof(struct nes_first_frag)) +
1390 (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe)) +
1391 (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe)) +
1392 (NES_NIC_WQ_SIZE * 2 * sizeof(struct nes_hw_nic_cqe)) +
1393 sizeof(struct nes_hw_nic_qp_context);
1394
1395 nesvnic->nic_vbase = pci_alloc_consistent(nesdev->pcidev, nesvnic->nic_mem_size,
1396 &nesvnic->nic_pbase);
1397 if (!nesvnic->nic_vbase) {
1398 nes_debug(NES_DBG_INIT, "Unable to allocate memory for NIC host descriptor rings\n");
1399 return -ENOMEM;
1400 }
1401 memset(nesvnic->nic_vbase, 0, nesvnic->nic_mem_size);
1402 nes_debug(NES_DBG_INIT, "Allocated NIC QP structures at %p (phys = %016lX), size = %u.\n",
1403 nesvnic->nic_vbase, (unsigned long)nesvnic->nic_pbase, nesvnic->nic_mem_size);
1404
1405 vmem = (void *)(((unsigned long)nesvnic->nic_vbase + (256 - 1)) &
1406 ~(unsigned long)(256 - 1));
1407 pmem = (dma_addr_t)(((unsigned long long)nesvnic->nic_pbase + (256 - 1)) &
1408 ~(unsigned long long)(256 - 1));
1409
1410 /* Setup the first Fragment buffers */
1411 nesvnic->nic.first_frag_vbase = vmem;
1412
1413 for (counter = 0; counter < NES_NIC_WQ_SIZE; counter++) {
1414 nesvnic->nic.frag_paddr[counter] = pmem;
1415 pmem += sizeof(struct nes_first_frag);
1416 }
1417
1418 /* setup the SQ */
1419 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_first_frag));
1420
1421 nesvnic->nic.sq_vbase = (void *)vmem;
1422 nesvnic->nic.sq_pbase = pmem;
1423 nesvnic->nic.sq_head = 0;
1424 nesvnic->nic.sq_tail = 0;
1425 nesvnic->nic.sq_size = NES_NIC_WQ_SIZE;
1426 for (counter = 0; counter < NES_NIC_WQ_SIZE; counter++) {
1427 nic_sqe = &nesvnic->nic.sq_vbase[counter];
1428 nic_sqe->wqe_words[NES_NIC_SQ_WQE_MISC_IDX] =
1429 cpu_to_le32(NES_NIC_SQ_WQE_DISABLE_CHKSUM |
1430 NES_NIC_SQ_WQE_COMPLETION);
1431 nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX] =
1432 cpu_to_le32((u32)NES_FIRST_FRAG_SIZE << 16);
1433 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX] =
1434 cpu_to_le32((u32)nesvnic->nic.frag_paddr[counter]);
1435 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX] =
1436 cpu_to_le32((u32)((u64)nesvnic->nic.frag_paddr[counter] >> 32));
1437 }
1438
1439 nesvnic->get_cqp_request = nes_get_cqp_request;
1440 nesvnic->post_cqp_request = nes_post_cqp_request;
1441 nesvnic->mcrq_mcast_filter = NULL;
1442
1443 spin_lock_init(&nesvnic->nic.sq_lock);
1444 spin_lock_init(&nesvnic->nic.rq_lock);
1445
1446 /* setup the RQ */
1447 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe));
1448 pmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe));
1449
1450
1451 nesvnic->nic.rq_vbase = vmem;
1452 nesvnic->nic.rq_pbase = pmem;
1453 nesvnic->nic.rq_head = 0;
1454 nesvnic->nic.rq_tail = 0;
1455 nesvnic->nic.rq_size = NES_NIC_WQ_SIZE;
1456
1457 /* setup the CQ */
1458 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe));
1459 pmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe));
1460
1461 if (nesdev->nesadapter->netdev_count > 2)
1462 nesvnic->mcrq_qp_id = nesvnic->nic_index + 32;
1463 else
1464 nesvnic->mcrq_qp_id = nesvnic->nic.qp_id + 4;
1465
1466 nesvnic->nic_cq.cq_vbase = vmem;
1467 nesvnic->nic_cq.cq_pbase = pmem;
1468 nesvnic->nic_cq.cq_head = 0;
1469 nesvnic->nic_cq.cq_size = NES_NIC_WQ_SIZE * 2;
1470
1471 nesvnic->nic_cq.ce_handler = nes_nic_napi_ce_handler;
1472
1473 /* Send CreateCQ request to CQP */
1474 spin_lock_irqsave(&nesdev->cqp.lock, flags);
1475 cqp_head = nesdev->cqp.sq_head;
1476
1477 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1478 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1479
1480 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(
1481 NES_CQP_CREATE_CQ | NES_CQP_CQ_CEQ_VALID |
1482 ((u32)nesvnic->nic_cq.cq_size << 16));
1483 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(
1484 nesvnic->nic_cq.cq_number | ((u32)nesdev->nic_ceq_index << 16));
1485 u64temp = (u64)nesvnic->nic_cq.cq_pbase;
1486 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1487 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = 0;
1488 u64temp = (unsigned long)&nesvnic->nic_cq;
1489 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] = cpu_to_le32((u32)(u64temp >> 1));
1490 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] =
1491 cpu_to_le32(((u32)((u64temp) >> 33)) & 0x7FFFFFFF);
1492 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX] = 0;
1493 if (++cqp_head >= nesdev->cqp.sq_size)
1494 cqp_head = 0;
1495 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1496 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1497
1498 /* Send CreateQP request to CQP */
1499 nic_context = (void *)(&nesvnic->nic_cq.cq_vbase[nesvnic->nic_cq.cq_size]);
1500 nic_context->context_words[NES_NIC_CTX_MISC_IDX] =
1501 cpu_to_le32((u32)NES_NIC_CTX_SIZE |
1502 ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 12));
1503 nes_debug(NES_DBG_INIT, "RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x%08X, RX_WINDOW_BUFFER_SIZE = 0x%08X\n",
1504 nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE),
1505 nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE));
1506 if (nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE) != 0) {
1507 nic_context->context_words[NES_NIC_CTX_MISC_IDX] |= cpu_to_le32(NES_NIC_BACK_STORE);
1508 }
1509
1510 u64temp = (u64)nesvnic->nic.sq_pbase;
1511 nic_context->context_words[NES_NIC_CTX_SQ_LOW_IDX] = cpu_to_le32((u32)u64temp);
1512 nic_context->context_words[NES_NIC_CTX_SQ_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
1513 u64temp = (u64)nesvnic->nic.rq_pbase;
1514 nic_context->context_words[NES_NIC_CTX_RQ_LOW_IDX] = cpu_to_le32((u32)u64temp);
1515 nic_context->context_words[NES_NIC_CTX_RQ_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
1516
1517 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_CREATE_QP |
1518 NES_CQP_QP_TYPE_NIC);
1519 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesvnic->nic.qp_id);
1520 u64temp = (u64)nesvnic->nic_cq.cq_pbase +
1521 (nesvnic->nic_cq.cq_size * sizeof(struct nes_hw_nic_cqe));
1522 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_QP_WQE_CONTEXT_LOW_IDX, u64temp);
1523
1524 if (++cqp_head >= nesdev->cqp.sq_size)
1525 cqp_head = 0;
1526 nesdev->cqp.sq_head = cqp_head;
1527
1528 barrier();
1529
1530 /* Ring doorbell (2 WQEs) */
1531 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x02800000 | nesdev->cqp.qp_id);
1532
1533 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
1534 nes_debug(NES_DBG_INIT, "Waiting for create NIC QP%u to complete.\n",
1535 nesvnic->nic.qp_id);
1536
1537 ret = wait_event_timeout(nesdev->cqp.waitq, (nesdev->cqp.sq_tail == cqp_head),
1538 NES_EVENT_TIMEOUT);
1539 nes_debug(NES_DBG_INIT, "Create NIC QP%u completed, wait_event_timeout ret = %u.\n",
1540 nesvnic->nic.qp_id, ret);
1541 if (!ret) {
1542 nes_debug(NES_DBG_INIT, "NIC QP%u create timeout expired\n", nesvnic->nic.qp_id);
1543 pci_free_consistent(nesdev->pcidev, nesvnic->nic_mem_size, nesvnic->nic_vbase,
1544 nesvnic->nic_pbase);
1545 return -EIO;
1546 }
1547
1548 /* Populate the RQ */
1549 for (counter = 0; counter < (NES_NIC_WQ_SIZE - 1); counter++) {
1550 skb = dev_alloc_skb(nesvnic->max_frame_size);
1551 if (!skb) {
1552 nes_debug(NES_DBG_INIT, "%s: out of memory for receive skb\n", netdev->name);
1553
1554 nes_destroy_nic_qp(nesvnic);
1555 return -ENOMEM;
1556 }
1557
1558 skb->dev = netdev;
1559
1560 pmem = pci_map_single(nesdev->pcidev, skb->data,
1561 nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
1562
1563 nic_rqe = &nesvnic->nic.rq_vbase[counter];
1564 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_1_0_IDX] = cpu_to_le32(nesvnic->max_frame_size);
1565 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_3_2_IDX] = 0;
1566 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX] = cpu_to_le32((u32)pmem);
1567 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX] = cpu_to_le32((u32)((u64)pmem >> 32));
1568 nesvnic->nic.rx_skb[counter] = skb;
1569 }
1570
1571 wqe_count = NES_NIC_WQ_SIZE - 1;
1572 nesvnic->nic.rq_head = wqe_count;
1573 barrier();
1574 do {
1575 counter = min(wqe_count, ((u32)255));
1576 wqe_count -= counter;
1577 nes_write32(nesdev->regs+NES_WQE_ALLOC, (counter << 24) | nesvnic->nic.qp_id);
1578 } while (wqe_count);
1579 init_timer(&nesvnic->rq_wqes_timer);
1580 nesvnic->rq_wqes_timer.function = nes_rq_wqes_timeout;
1581 nesvnic->rq_wqes_timer.data = (unsigned long)nesvnic;
1582 nes_debug(NES_DBG_INIT, "NAPI support Enabled\n");
1583
1584 if (nesdev->nesadapter->et_use_adaptive_rx_coalesce)
1585 {
1586 nes_nic_init_timer(nesdev);
1587 if (netdev->mtu > 1500)
1588 jumbomode = 1;
1589 nes_nic_init_timer_defaults(nesdev, jumbomode);
1590 }
1591
1592 return 0;
1593 }
1594
1595
1596 /**
1597 * nes_destroy_nic_qp
1598 */
1599 void nes_destroy_nic_qp(struct nes_vnic *nesvnic)
1600 {
1601 struct nes_device *nesdev = nesvnic->nesdev;
1602 struct nes_hw_cqp_wqe *cqp_wqe;
1603 struct nes_hw_nic_rq_wqe *nic_rqe;
1604 u64 wqe_frag;
1605 u32 cqp_head;
1606 unsigned long flags;
1607 int ret;
1608
1609 /* Free remaining NIC receive buffers */
1610 while (nesvnic->nic.rq_head != nesvnic->nic.rq_tail) {
1611 nic_rqe = &nesvnic->nic.rq_vbase[nesvnic->nic.rq_tail];
1612 wqe_frag = (u64)le32_to_cpu(nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX]);
1613 wqe_frag |= ((u64)le32_to_cpu(nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX])) << 32;
1614 pci_unmap_single(nesdev->pcidev, (dma_addr_t)wqe_frag,
1615 nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
1616 dev_kfree_skb(nesvnic->nic.rx_skb[nesvnic->nic.rq_tail++]);
1617 nesvnic->nic.rq_tail &= (nesvnic->nic.rq_size - 1);
1618 }
1619
1620 spin_lock_irqsave(&nesdev->cqp.lock, flags);
1621
1622 /* Destroy NIC QP */
1623 cqp_head = nesdev->cqp.sq_head;
1624 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1625 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1626
1627 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1628 (NES_CQP_DESTROY_QP | NES_CQP_QP_TYPE_NIC));
1629 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
1630 nesvnic->nic.qp_id);
1631
1632 if (++cqp_head >= nesdev->cqp.sq_size)
1633 cqp_head = 0;
1634
1635 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1636
1637 /* Destroy NIC CQ */
1638 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1639 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1640 (NES_CQP_DESTROY_CQ | ((u32)nesvnic->nic_cq.cq_size << 16)));
1641 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
1642 (nesvnic->nic_cq.cq_number | ((u32)nesdev->nic_ceq_index << 16)));
1643
1644 if (++cqp_head >= nesdev->cqp.sq_size)
1645 cqp_head = 0;
1646
1647 nesdev->cqp.sq_head = cqp_head;
1648 barrier();
1649
1650 /* Ring doorbell (2 WQEs) */
1651 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x02800000 | nesdev->cqp.qp_id);
1652
1653 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
1654 nes_debug(NES_DBG_SHUTDOWN, "Waiting for CQP, cqp_head=%u, cqp.sq_head=%u,"
1655 " cqp.sq_tail=%u, cqp.sq_size=%u\n",
1656 cqp_head, nesdev->cqp.sq_head,
1657 nesdev->cqp.sq_tail, nesdev->cqp.sq_size);
1658
1659 ret = wait_event_timeout(nesdev->cqp.waitq, (nesdev->cqp.sq_tail == cqp_head),
1660 NES_EVENT_TIMEOUT);
1661
1662 nes_debug(NES_DBG_SHUTDOWN, "Destroy NIC QP returned, wait_event_timeout ret = %u, cqp_head=%u,"
1663 " cqp.sq_head=%u, cqp.sq_tail=%u\n",
1664 ret, cqp_head, nesdev->cqp.sq_head, nesdev->cqp.sq_tail);
1665 if (!ret) {
1666 nes_debug(NES_DBG_SHUTDOWN, "NIC QP%u destroy timeout expired\n",
1667 nesvnic->nic.qp_id);
1668 }
1669
1670 pci_free_consistent(nesdev->pcidev, nesvnic->nic_mem_size, nesvnic->nic_vbase,
1671 nesvnic->nic_pbase);
1672 }
1673
1674 /**
1675 * nes_napi_isr
1676 */
1677 int nes_napi_isr(struct nes_device *nesdev)
1678 {
1679 struct nes_adapter *nesadapter = nesdev->nesadapter;
1680 u32 int_stat;
1681
1682 if (nesdev->napi_isr_ran) {
1683 /* interrupt status has already been read in ISR */
1684 int_stat = nesdev->int_stat;
1685 } else {
1686 int_stat = nes_read32(nesdev->regs + NES_INT_STAT);
1687 nesdev->int_stat = int_stat;
1688 nesdev->napi_isr_ran = 1;
1689 }
1690
1691 int_stat &= nesdev->int_req;
1692 /* iff NIC, process here, else wait for DPC */
1693 if ((int_stat) && ((int_stat & 0x0000ff00) == int_stat)) {
1694 nesdev->napi_isr_ran = 0;
1695 nes_write32(nesdev->regs+NES_INT_STAT,
1696 (int_stat &
1697 ~(NES_INT_INTF|NES_INT_TIMER|NES_INT_MAC0|NES_INT_MAC1|NES_INT_MAC2|NES_INT_MAC3)));
1698
1699 /* Process the CEQs */
1700 nes_process_ceq(nesdev, &nesdev->nesadapter->ceq[nesdev->nic_ceq_index]);
1701
1702 if (unlikely((((nesadapter->et_rx_coalesce_usecs_irq) &&
1703 (!nesadapter->et_use_adaptive_rx_coalesce)) ||
1704 ((nesadapter->et_use_adaptive_rx_coalesce) &&
1705 (nesdev->deepcq_count > nesadapter->et_pkt_rate_low)))) ) {
1706 if ((nesdev->int_req & NES_INT_TIMER) == 0) {
1707 /* Enable Periodic timer interrupts */
1708 nesdev->int_req |= NES_INT_TIMER;
1709 /* ack any pending periodic timer interrupts so we don't get an immediate interrupt */
1710 /* TODO: need to also ack other unused periodic timer values, get from nesadapter */
1711 nes_write32(nesdev->regs+NES_TIMER_STAT,
1712 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
1713 nes_write32(nesdev->regs+NES_INTF_INT_MASK,
1714 ~(nesdev->intf_int_req | NES_INTF_PERIODIC_TIMER));
1715 }
1716
1717 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
1718 {
1719 nes_nic_init_timer(nesdev);
1720 }
1721 /* Enable interrupts, except CEQs */
1722 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
1723 } else {
1724 /* Enable interrupts, make sure timer is off */
1725 nesdev->int_req &= ~NES_INT_TIMER;
1726 nes_write32(nesdev->regs+NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
1727 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
1728 }
1729 nesdev->deepcq_count = 0;
1730 return 1;
1731 } else {
1732 return 0;
1733 }
1734 }
1735
1736
1737 /**
1738 * nes_dpc
1739 */
1740 void nes_dpc(unsigned long param)
1741 {
1742 struct nes_device *nesdev = (struct nes_device *)param;
1743 struct nes_adapter *nesadapter = nesdev->nesadapter;
1744 u32 counter;
1745 u32 loop_counter = 0;
1746 u32 int_status_bit;
1747 u32 int_stat;
1748 u32 timer_stat;
1749 u32 temp_int_stat;
1750 u32 intf_int_stat;
1751 u32 debug_error;
1752 u32 processed_intf_int = 0;
1753 u16 processed_timer_int = 0;
1754 u16 completion_ints = 0;
1755 u16 timer_ints = 0;
1756
1757 /* nes_debug(NES_DBG_ISR, "\n"); */
1758
1759 do {
1760 timer_stat = 0;
1761 if (nesdev->napi_isr_ran) {
1762 nesdev->napi_isr_ran = 0;
1763 int_stat = nesdev->int_stat;
1764 } else
1765 int_stat = nes_read32(nesdev->regs+NES_INT_STAT);
1766 if (processed_intf_int != 0)
1767 int_stat &= nesdev->int_req & ~NES_INT_INTF;
1768 else
1769 int_stat &= nesdev->int_req;
1770 if (processed_timer_int == 0) {
1771 processed_timer_int = 1;
1772 if (int_stat & NES_INT_TIMER) {
1773 timer_stat = nes_read32(nesdev->regs + NES_TIMER_STAT);
1774 if ((timer_stat & nesdev->timer_int_req) == 0) {
1775 int_stat &= ~NES_INT_TIMER;
1776 }
1777 }
1778 } else {
1779 int_stat &= ~NES_INT_TIMER;
1780 }
1781
1782 if (int_stat) {
1783 if (int_stat & ~(NES_INT_INTF|NES_INT_TIMER|NES_INT_MAC0|
1784 NES_INT_MAC1|NES_INT_MAC2|NES_INT_MAC3)) {
1785 /* Ack the interrupts */
1786 nes_write32(nesdev->regs+NES_INT_STAT,
1787 (int_stat & ~(NES_INT_INTF|NES_INT_TIMER|NES_INT_MAC0|
1788 NES_INT_MAC1|NES_INT_MAC2|NES_INT_MAC3)));
1789 }
1790
1791 temp_int_stat = int_stat;
1792 for (counter = 0, int_status_bit = 1; counter < 16; counter++) {
1793 if (int_stat & int_status_bit) {
1794 nes_process_ceq(nesdev, &nesadapter->ceq[counter]);
1795 temp_int_stat &= ~int_status_bit;
1796 completion_ints = 1;
1797 }
1798 if (!(temp_int_stat & 0x0000ffff))
1799 break;
1800 int_status_bit <<= 1;
1801 }
1802
1803 /* Process the AEQ for this pci function */
1804 int_status_bit = 1 << (16 + PCI_FUNC(nesdev->pcidev->devfn));
1805 if (int_stat & int_status_bit) {
1806 nes_process_aeq(nesdev, &nesadapter->aeq[PCI_FUNC(nesdev->pcidev->devfn)]);
1807 }
1808
1809 /* Process the MAC interrupt for this pci function */
1810 int_status_bit = 1 << (24 + nesdev->mac_index);
1811 if (int_stat & int_status_bit) {
1812 nes_process_mac_intr(nesdev, nesdev->mac_index);
1813 }
1814
1815 if (int_stat & NES_INT_TIMER) {
1816 if (timer_stat & nesdev->timer_int_req) {
1817 nes_write32(nesdev->regs + NES_TIMER_STAT,
1818 (timer_stat & nesdev->timer_int_req) |
1819 ~(nesdev->nesadapter->timer_int_req));
1820 timer_ints = 1;
1821 }
1822 }
1823
1824 if (int_stat & NES_INT_INTF) {
1825 processed_intf_int = 1;
1826 intf_int_stat = nes_read32(nesdev->regs+NES_INTF_INT_STAT);
1827 intf_int_stat &= nesdev->intf_int_req;
1828 if (NES_INTF_INT_CRITERR & intf_int_stat) {
1829 debug_error = nes_read_indexed(nesdev, NES_IDX_DEBUG_ERROR_CONTROL_STATUS);
1830 printk(KERN_ERR PFX "Critical Error reported by device!!! 0x%02X\n",
1831 (u16)debug_error);
1832 nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_CONTROL_STATUS,
1833 0x01010000 | (debug_error & 0x0000ffff));
1834 /* BUG(); */
1835 if (crit_err_count++ > 10)
1836 nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS1, 1 << 0x17);
1837 }
1838 if (NES_INTF_INT_PCIERR & intf_int_stat) {
1839 printk(KERN_ERR PFX "PCI Error reported by device!!!\n");
1840 BUG();
1841 }
1842 if (NES_INTF_INT_AEQ_OFLOW & intf_int_stat) {
1843 printk(KERN_ERR PFX "AEQ Overflow reported by device!!!\n");
1844 BUG();
1845 }
1846 nes_write32(nesdev->regs+NES_INTF_INT_STAT, intf_int_stat);
1847 }
1848
1849 if (int_stat & NES_INT_TSW) {
1850 }
1851 }
1852 /* Don't use the interface interrupt bit stay in loop */
1853 int_stat &= ~NES_INT_INTF|NES_INT_TIMER|NES_INT_MAC0|
1854 NES_INT_MAC1|NES_INT_MAC2|NES_INT_MAC3;
1855 } while ((int_stat != 0) && (loop_counter++ < MAX_DPC_ITERATIONS));
1856
1857 if (timer_ints == 1) {
1858 if ((nesadapter->et_rx_coalesce_usecs_irq) || (nesadapter->et_use_adaptive_rx_coalesce)) {
1859 if (completion_ints == 0) {
1860 nesdev->timer_only_int_count++;
1861 if (nesdev->timer_only_int_count>=nesadapter->timer_int_limit) {
1862 nesdev->timer_only_int_count = 0;
1863 nesdev->int_req &= ~NES_INT_TIMER;
1864 nes_write32(nesdev->regs + NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
1865 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
1866 } else {
1867 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff|(~nesdev->int_req));
1868 }
1869 } else {
1870 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
1871 {
1872 nes_nic_init_timer(nesdev);
1873 }
1874 nesdev->timer_only_int_count = 0;
1875 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff|(~nesdev->int_req));
1876 }
1877 } else {
1878 nesdev->timer_only_int_count = 0;
1879 nesdev->int_req &= ~NES_INT_TIMER;
1880 nes_write32(nesdev->regs+NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
1881 nes_write32(nesdev->regs+NES_TIMER_STAT,
1882 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
1883 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
1884 }
1885 } else {
1886 if ( (completion_ints == 1) &&
1887 (((nesadapter->et_rx_coalesce_usecs_irq) &&
1888 (!nesadapter->et_use_adaptive_rx_coalesce)) ||
1889 ((nesdev->deepcq_count > nesadapter->et_pkt_rate_low) &&
1890 (nesadapter->et_use_adaptive_rx_coalesce) )) ) {
1891 /* nes_debug(NES_DBG_ISR, "Enabling periodic timer interrupt.\n" ); */
1892 nesdev->timer_only_int_count = 0;
1893 nesdev->int_req |= NES_INT_TIMER;
1894 nes_write32(nesdev->regs+NES_TIMER_STAT,
1895 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
1896 nes_write32(nesdev->regs+NES_INTF_INT_MASK,
1897 ~(nesdev->intf_int_req | NES_INTF_PERIODIC_TIMER));
1898 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
1899 } else {
1900 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
1901 }
1902 }
1903 nesdev->deepcq_count = 0;
1904 }
1905
1906
1907 /**
1908 * nes_process_ceq
1909 */
1910 void nes_process_ceq(struct nes_device *nesdev, struct nes_hw_ceq *ceq)
1911 {
1912 u64 u64temp;
1913 struct nes_hw_cq *cq;
1914 u32 head;
1915 u32 ceq_size;
1916
1917 /* nes_debug(NES_DBG_CQ, "\n"); */
1918 head = ceq->ceq_head;
1919 ceq_size = ceq->ceq_size;
1920
1921 do {
1922 if (le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX]) &
1923 NES_CEQE_VALID) {
1924 u64temp = (((u64)(le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX])))<<32) |
1925 ((u64)(le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_LOW_IDX])));
1926 u64temp <<= 1;
1927 cq = *((struct nes_hw_cq **)&u64temp);
1928 /* nes_debug(NES_DBG_CQ, "pCQ = %p\n", cq); */
1929 barrier();
1930 ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX] = 0;
1931
1932 /* call the event handler */
1933 cq->ce_handler(nesdev, cq);
1934
1935 if (++head >= ceq_size)
1936 head = 0;
1937 } else {
1938 break;
1939 }
1940
1941 } while (1);
1942
1943 ceq->ceq_head = head;
1944 }
1945
1946
1947 /**
1948 * nes_process_aeq
1949 */
1950 void nes_process_aeq(struct nes_device *nesdev, struct nes_hw_aeq *aeq)
1951 {
1952 // u64 u64temp;
1953 u32 head;
1954 u32 aeq_size;
1955 u32 aeqe_misc;
1956 u32 aeqe_cq_id;
1957 struct nes_hw_aeqe volatile *aeqe;
1958
1959 head = aeq->aeq_head;
1960 aeq_size = aeq->aeq_size;
1961
1962 do {
1963 aeqe = &aeq->aeq_vbase[head];
1964 if ((le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]) & NES_AEQE_VALID) == 0)
1965 break;
1966 aeqe_misc = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
1967 aeqe_cq_id = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]);
1968 if (aeqe_misc & (NES_AEQE_QP|NES_AEQE_CQ)) {
1969 if (aeqe_cq_id >= NES_FIRST_QPN) {
1970 /* dealing with an accelerated QP related AE */
1971 // u64temp = (((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_HIGH_IDX])))<<32) |
1972 // ((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_LOW_IDX])));
1973 nes_process_iwarp_aeqe(nesdev, (struct nes_hw_aeqe *)aeqe);
1974 } else {
1975 /* TODO: dealing with a CQP related AE */
1976 nes_debug(NES_DBG_AEQ, "Processing CQP related AE, misc = 0x%04X\n",
1977 (u16)(aeqe_misc >> 16));
1978 }
1979 }
1980
1981 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = 0;
1982
1983 if (++head >= aeq_size)
1984 head = 0;
1985 }
1986 while (1);
1987 aeq->aeq_head = head;
1988 }
1989
1990 static void nes_reset_link(struct nes_device *nesdev, u32 mac_index)
1991 {
1992 struct nes_adapter *nesadapter = nesdev->nesadapter;
1993 u32 reset_value;
1994 u32 i=0;
1995 u32 u32temp;
1996
1997 if (nesadapter->hw_rev == NE020_REV) {
1998 return;
1999 }
2000 mh_detected++;
2001
2002 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
2003
2004 if ((mac_index == 0) || ((mac_index == 1) && (nesadapter->OneG_Mode)))
2005 reset_value |= 0x0000001d;
2006 else
2007 reset_value |= 0x0000002d;
2008
2009 if (4 <= (nesadapter->link_interrupt_count[mac_index] / ((u16)NES_MAX_LINK_INTERRUPTS))) {
2010 if ((!nesadapter->OneG_Mode) && (nesadapter->port_count == 2)) {
2011 nesadapter->link_interrupt_count[0] = 0;
2012 nesadapter->link_interrupt_count[1] = 0;
2013 u32temp = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
2014 if (0x00000040 & u32temp)
2015 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088);
2016 else
2017 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
2018
2019 reset_value |= 0x0000003d;
2020 }
2021 nesadapter->link_interrupt_count[mac_index] = 0;
2022 }
2023
2024 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
2025
2026 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
2027 & 0x00000040) != 0x00000040) && (i++ < 5000));
2028
2029 if (0x0000003d == (reset_value & 0x0000003d)) {
2030 u32 pcs_control_status0, pcs_control_status1;
2031
2032 for (i = 0; i < 10; i++) {
2033 pcs_control_status0 = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0);
2034 pcs_control_status1 = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
2035 if (((0x0F000000 == (pcs_control_status0 & 0x0F000000))
2036 && (pcs_control_status0 & 0x00100000))
2037 || ((0x0F000000 == (pcs_control_status1 & 0x0F000000))
2038 && (pcs_control_status1 & 0x00100000)))
2039 continue;
2040 else
2041 break;
2042 }
2043 if (10 == i) {
2044 u32temp = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
2045 if (0x00000040 & u32temp)
2046 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088);
2047 else
2048 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
2049
2050 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
2051
2052 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET)
2053 & 0x00000040) != 0x00000040) && (i++ < 5000));
2054 }
2055 }
2056 }
2057
2058 /**
2059 * nes_process_mac_intr
2060 */
2061 void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2062 {
2063 unsigned long flags;
2064 u32 pcs_control_status;
2065 struct nes_adapter *nesadapter = nesdev->nesadapter;
2066 struct nes_vnic *nesvnic;
2067 u32 mac_status;
2068 u32 mac_index = nesdev->mac_index;
2069 u32 u32temp;
2070 u16 phy_data;
2071 u16 temp_phy_data;
2072
2073 spin_lock_irqsave(&nesadapter->phy_lock, flags);
2074 if (nesadapter->mac_sw_state[mac_number] != NES_MAC_SW_IDLE) {
2075 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2076 return;
2077 }
2078 nesadapter->mac_sw_state[mac_number] = NES_MAC_SW_INTERRUPT;
2079 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2080
2081 /* ack the MAC interrupt */
2082 mac_status = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (mac_index * 0x200));
2083 /* Clear the interrupt */
2084 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (mac_index * 0x200), mac_status);
2085
2086 nes_debug(NES_DBG_PHY, "MAC%u interrupt status = 0x%X.\n", mac_number, mac_status);
2087
2088 if (mac_status & (NES_MAC_INT_LINK_STAT_CHG | NES_MAC_INT_XGMII_EXT)) {
2089 nesdev->link_status_interrupts++;
2090 if (0 == (++nesadapter->link_interrupt_count[mac_index] % ((u16)NES_MAX_LINK_INTERRUPTS))) {
2091 spin_lock_irqsave(&nesadapter->phy_lock, flags);
2092 nes_reset_link(nesdev, mac_index);
2093 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2094 }
2095 /* read the PHY interrupt status register */
2096 if (nesadapter->OneG_Mode) {
2097 do {
2098 nes_read_1G_phy_reg(nesdev, 0x1a,
2099 nesadapter->phy_index[mac_index], &phy_data);
2100 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x1a = 0x%X.\n",
2101 nesadapter->phy_index[mac_index], phy_data);
2102 } while (phy_data&0x8000);
2103
2104 temp_phy_data = 0;
2105 do {
2106 nes_read_1G_phy_reg(nesdev, 0x11,
2107 nesadapter->phy_index[mac_index], &phy_data);
2108 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x11 = 0x%X.\n",
2109 nesadapter->phy_index[mac_index], phy_data);
2110 if (temp_phy_data == phy_data)
2111 break;
2112 temp_phy_data = phy_data;
2113 } while (1);
2114
2115 nes_read_1G_phy_reg(nesdev, 0x1e,
2116 nesadapter->phy_index[mac_index], &phy_data);
2117 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x1e = 0x%X.\n",
2118 nesadapter->phy_index[mac_index], phy_data);
2119
2120 nes_read_1G_phy_reg(nesdev, 1,
2121 nesadapter->phy_index[mac_index], &phy_data);
2122 nes_debug(NES_DBG_PHY, "1G phy%u data from register 1 = 0x%X\n",
2123 nesadapter->phy_index[mac_index], phy_data);
2124
2125 if (temp_phy_data & 0x1000) {
2126 nes_debug(NES_DBG_PHY, "The Link is up according to the PHY\n");
2127 phy_data = 4;
2128 } else {
2129 nes_debug(NES_DBG_PHY, "The Link is down according to the PHY\n");
2130 }
2131 }
2132 nes_debug(NES_DBG_PHY, "Eth SERDES Common Status: 0=0x%08X, 1=0x%08X\n",
2133 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0),
2134 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0+0x200));
2135 pcs_control_status = nes_read_indexed(nesdev,
2136 NES_IDX_PHY_PCS_CONTROL_STATUS0 + ((mac_index&1)*0x200));
2137 pcs_control_status = nes_read_indexed(nesdev,
2138 NES_IDX_PHY_PCS_CONTROL_STATUS0 + ((mac_index&1)*0x200));
2139 nes_debug(NES_DBG_PHY, "PCS PHY Control/Status%u: 0x%08X\n",
2140 mac_index, pcs_control_status);
2141 if (nesadapter->OneG_Mode) {
2142 u32temp = 0x01010000;
2143 if (nesadapter->port_count > 2) {
2144 u32temp |= 0x02020000;
2145 }
2146 if ((pcs_control_status & u32temp)!= u32temp) {
2147 phy_data = 0;
2148 nes_debug(NES_DBG_PHY, "PCS says the link is down\n");
2149 }
2150 } else if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_IRIS) {
2151 nes_read_10G_phy_reg(nesdev, 1, nesadapter->phy_index[mac_index]);
2152 temp_phy_data = (u16)nes_read_indexed(nesdev,
2153 NES_IDX_MAC_MDIO_CONTROL);
2154 u32temp = 20;
2155 do {
2156 nes_read_10G_phy_reg(nesdev, 1, nesadapter->phy_index[mac_index]);
2157 phy_data = (u16)nes_read_indexed(nesdev,
2158 NES_IDX_MAC_MDIO_CONTROL);
2159 if ((phy_data == temp_phy_data) || (!(--u32temp)))
2160 break;
2161 temp_phy_data = phy_data;
2162 } while (1);
2163 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
2164 __FUNCTION__, phy_data, nesadapter->mac_link_down ? "DOWN" : "UP");
2165
2166 } else {
2167 phy_data = (0x0f0f0000 == (pcs_control_status & 0x0f1f0000)) ? 4 : 0;
2168 }
2169
2170 if (phy_data & 0x0004) {
2171 nesadapter->mac_link_down[mac_index] = 0;
2172 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2173 nes_debug(NES_DBG_PHY, "The Link is UP!!. linkup was %d\n",
2174 nesvnic->linkup);
2175 if (nesvnic->linkup == 0) {
2176 printk(PFX "The Link is now up for port %u, netdev %p.\n",
2177 mac_index, nesvnic->netdev);
2178 if (netif_queue_stopped(nesvnic->netdev))
2179 netif_start_queue(nesvnic->netdev);
2180 nesvnic->linkup = 1;
2181 netif_carrier_on(nesvnic->netdev);
2182 }
2183 }
2184 } else {
2185 nesadapter->mac_link_down[mac_index] = 1;
2186 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2187 nes_debug(NES_DBG_PHY, "The Link is Down!!. linkup was %d\n",
2188 nesvnic->linkup);
2189 if (nesvnic->linkup == 1) {
2190 printk(PFX "The Link is now down for port %u, netdev %p.\n",
2191 mac_index, nesvnic->netdev);
2192 if (!(netif_queue_stopped(nesvnic->netdev)))
2193 netif_stop_queue(nesvnic->netdev);
2194 nesvnic->linkup = 0;
2195 netif_carrier_off(nesvnic->netdev);
2196 }
2197 }
2198 }
2199 }
2200
2201 nesadapter->mac_sw_state[mac_number] = NES_MAC_SW_IDLE;
2202 }
2203
2204
2205
2206 void nes_nic_napi_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
2207 {
2208 struct nes_vnic *nesvnic = container_of(cq, struct nes_vnic, nic_cq);
2209
2210 netif_rx_schedule(nesdev->netdev[nesvnic->netdev_index], &nesvnic->napi);
2211 }
2212
2213
2214 /* The MAX_RQES_TO_PROCESS defines how many max read requests to complete before
2215 * getting out of nic_ce_handler
2216 */
2217 #define MAX_RQES_TO_PROCESS 384
2218
2219 /**
2220 * nes_nic_ce_handler
2221 */
2222 void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
2223 {
2224 u64 u64temp;
2225 dma_addr_t bus_address;
2226 struct nes_hw_nic *nesnic;
2227 struct nes_vnic *nesvnic = container_of(cq, struct nes_vnic, nic_cq);
2228 struct nes_adapter *nesadapter = nesdev->nesadapter;
2229 struct nes_hw_nic_rq_wqe *nic_rqe;
2230 struct nes_hw_nic_sq_wqe *nic_sqe;
2231 struct sk_buff *skb;
2232 struct sk_buff *rx_skb;
2233 __le16 *wqe_fragment_length;
2234 u32 head;
2235 u32 cq_size;
2236 u32 rx_pkt_size;
2237 u32 cqe_count=0;
2238 u32 cqe_errv;
2239 u32 cqe_misc;
2240 u16 wqe_fragment_index = 1; /* first fragment (0) is used by copy buffer */
2241 u16 vlan_tag;
2242 u16 pkt_type;
2243 u16 rqes_processed = 0;
2244 u8 sq_cqes = 0;
2245
2246 head = cq->cq_head;
2247 cq_size = cq->cq_size;
2248 cq->cqes_pending = 1;
2249 do {
2250 if (le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX]) &
2251 NES_NIC_CQE_VALID) {
2252 nesnic = &nesvnic->nic;
2253 cqe_misc = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX]);
2254 if (cqe_misc & NES_NIC_CQE_SQ) {
2255 sq_cqes++;
2256 wqe_fragment_index = 1;
2257 nic_sqe = &nesnic->sq_vbase[nesnic->sq_tail];
2258 skb = nesnic->tx_skb[nesnic->sq_tail];
2259 wqe_fragment_length = (__le16 *)&nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX];
2260 /* bump past the vlan tag */
2261 wqe_fragment_length++;
2262 if (le16_to_cpu(wqe_fragment_length[wqe_fragment_index]) != 0) {
2263 u64temp = (u64) le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX+wqe_fragment_index*2]);
2264 u64temp += ((u64)le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX+wqe_fragment_index*2]))<<32;
2265 bus_address = (dma_addr_t)u64temp;
2266 if (test_and_clear_bit(nesnic->sq_tail, nesnic->first_frag_overflow)) {
2267 pci_unmap_single(nesdev->pcidev,
2268 bus_address,
2269 le16_to_cpu(wqe_fragment_length[wqe_fragment_index++]),
2270 PCI_DMA_TODEVICE);
2271 }
2272 for (; wqe_fragment_index < 5; wqe_fragment_index++) {
2273 if (wqe_fragment_length[wqe_fragment_index]) {
2274 u64temp = le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX+wqe_fragment_index*2]);
2275 u64temp += ((u64)le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX+wqe_fragment_index*2]))<<32;
2276 bus_address = (dma_addr_t)u64temp;
2277 pci_unmap_page(nesdev->pcidev,
2278 bus_address,
2279 le16_to_cpu(wqe_fragment_length[wqe_fragment_index]),
2280 PCI_DMA_TODEVICE);
2281 } else
2282 break;
2283 }
2284 if (skb)
2285 dev_kfree_skb_any(skb);
2286 }
2287 nesnic->sq_tail++;
2288 nesnic->sq_tail &= nesnic->sq_size-1;
2289 if (sq_cqes > 128) {
2290 barrier();
2291 /* restart the queue if it had been stopped */
2292 if (netif_queue_stopped(nesvnic->netdev))
2293 netif_wake_queue(nesvnic->netdev);
2294 sq_cqes = 0;
2295 }
2296 } else {
2297 rqes_processed ++;
2298
2299 cq->rx_cqes_completed++;
2300 cq->rx_pkts_indicated++;
2301 rx_pkt_size = cqe_misc & 0x0000ffff;
2302 nic_rqe = &nesnic->rq_vbase[nesnic->rq_tail];
2303 /* Get the skb */
2304 rx_skb = nesnic->rx_skb[nesnic->rq_tail];
2305 nic_rqe = &nesnic->rq_vbase[nesvnic->nic.rq_tail];
2306 bus_address = (dma_addr_t)le32_to_cpu(nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX]);
2307 bus_address += ((u64)le32_to_cpu(nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX])) << 32;
2308 pci_unmap_single(nesdev->pcidev, bus_address,
2309 nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
2310 /* rx_skb->tail = rx_skb->data + rx_pkt_size; */
2311 /* rx_skb->len = rx_pkt_size; */
2312 rx_skb->len = 0; /* TODO: see if this is necessary */
2313 skb_put(rx_skb, rx_pkt_size);
2314 rx_skb->protocol = eth_type_trans(rx_skb, nesvnic->netdev);
2315 nesnic->rq_tail++;
2316 nesnic->rq_tail &= nesnic->rq_size - 1;
2317
2318 atomic_inc(&nesvnic->rx_skbs_needed);
2319 if (atomic_read(&nesvnic->rx_skbs_needed) > (nesvnic->nic.rq_size>>1)) {
2320 nes_write32(nesdev->regs+NES_CQE_ALLOC,
2321 cq->cq_number | (cqe_count << 16));
2322 // nesadapter->tune_timer.cq_count += cqe_count;
2323 nesdev->currcq_count += cqe_count;
2324 cqe_count = 0;
2325 nes_replenish_nic_rq(nesvnic);
2326 }
2327 pkt_type = (u16)(le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_TAG_PKT_TYPE_IDX]));
2328 cqe_errv = (cqe_misc & NES_NIC_CQE_ERRV_MASK) >> NES_NIC_CQE_ERRV_SHIFT;
2329 rx_skb->ip_summed = CHECKSUM_NONE;
2330
2331 if ((NES_PKT_TYPE_TCPV4_BITS == (pkt_type & NES_PKT_TYPE_TCPV4_MASK)) ||
2332 (NES_PKT_TYPE_UDPV4_BITS == (pkt_type & NES_PKT_TYPE_UDPV4_MASK))) {
2333 if ((cqe_errv &
2334 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR | NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR |
2335 NES_NIC_ERRV_BITS_IPH_ERR | NES_NIC_ERRV_BITS_WQE_OVERRUN)) == 0) {
2336 if (nesvnic->rx_checksum_disabled == 0) {
2337 rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
2338 }
2339 } else
2340 nes_debug(NES_DBG_CQ, "%s: unsuccessfully checksummed TCP or UDP packet."
2341 " errv = 0x%X, pkt_type = 0x%X.\n",
2342 nesvnic->netdev->name, cqe_errv, pkt_type);
2343
2344 } else if ((pkt_type & NES_PKT_TYPE_IPV4_MASK) == NES_PKT_TYPE_IPV4_BITS) {
2345 if ((cqe_errv &
2346 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR | NES_NIC_ERRV_BITS_IPH_ERR |
2347 NES_NIC_ERRV_BITS_WQE_OVERRUN)) == 0) {
2348 if (nesvnic->rx_checksum_disabled == 0) {
2349 rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
2350 /* nes_debug(NES_DBG_CQ, "%s: Reporting successfully checksummed IPv4 packet.\n",
2351 nesvnic->netdev->name); */
2352 }
2353 } else
2354 nes_debug(NES_DBG_CQ, "%s: unsuccessfully checksummed TCP or UDP packet."
2355 " errv = 0x%X, pkt_type = 0x%X.\n",
2356 nesvnic->netdev->name, cqe_errv, pkt_type);
2357 }
2358 /* nes_debug(NES_DBG_CQ, "pkt_type=%x, APBVT_MASK=%x\n",
2359 pkt_type, (pkt_type & NES_PKT_TYPE_APBVT_MASK)); */
2360
2361 if ((pkt_type & NES_PKT_TYPE_APBVT_MASK) == NES_PKT_TYPE_APBVT_BITS) {
2362 nes_cm_recv(rx_skb, nesvnic->netdev);
2363 } else {
2364 if ((cqe_misc & NES_NIC_CQE_TAG_VALID) && (nesvnic->vlan_grp != NULL)) {
2365 vlan_tag = (u16)(le32_to_cpu(
2366 cq->cq_vbase[head].cqe_words[NES_NIC_CQE_TAG_PKT_TYPE_IDX])
2367 >> 16);
2368 nes_debug(NES_DBG_CQ, "%s: Reporting stripped VLAN packet. Tag = 0x%04X\n",
2369 nesvnic->netdev->name, vlan_tag);
2370 nes_vlan_rx(rx_skb, nesvnic->vlan_grp, vlan_tag);
2371 } else {
2372 nes_netif_rx(rx_skb);
2373 }
2374 }
2375
2376 nesvnic->netdev->last_rx = jiffies;
2377 /* nesvnic->netstats.rx_packets++; */
2378 /* nesvnic->netstats.rx_bytes += rx_pkt_size; */
2379 }
2380
2381 cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX] = 0;
2382 /* Accounting... */
2383 cqe_count++;
2384 if (++head >= cq_size)
2385 head = 0;
2386 if (cqe_count == 255) {
2387 /* Replenish Nic CQ */
2388 nes_write32(nesdev->regs+NES_CQE_ALLOC,
2389 cq->cq_number | (cqe_count << 16));
2390 // nesdev->nesadapter->tune_timer.cq_count += cqe_count;
2391 nesdev->currcq_count += cqe_count;
2392 cqe_count = 0;
2393 }
2394
2395 if (cq->rx_cqes_completed >= nesvnic->budget)
2396 break;
2397 } else {
2398 cq->cqes_pending = 0;
2399 break;
2400 }
2401
2402 } while (1);
2403
2404 if (sq_cqes) {
2405 barrier();
2406 /* restart the queue if it had been stopped */
2407 if (netif_queue_stopped(nesvnic->netdev))
2408 netif_wake_queue(nesvnic->netdev);
2409 }
2410
2411 cq->cq_head = head;
2412 /* nes_debug(NES_DBG_CQ, "CQ%u Processed = %u cqes, new head = %u.\n",
2413 cq->cq_number, cqe_count, cq->cq_head); */
2414 cq->cqe_allocs_pending = cqe_count;
2415 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
2416 {
2417 // nesdev->nesadapter->tune_timer.cq_count += cqe_count;
2418 nesdev->currcq_count += cqe_count;
2419 nes_nic_tune_timer(nesdev);
2420 }
2421 if (atomic_read(&nesvnic->rx_skbs_needed))
2422 nes_replenish_nic_rq(nesvnic);
2423 }
2424
2425
2426 /**
2427 * nes_cqp_ce_handler
2428 */
2429 void nes_cqp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *cq)
2430 {
2431 u64 u64temp;
2432 unsigned long flags;
2433 struct nes_hw_cqp *cqp = NULL;
2434 struct nes_cqp_request *cqp_request;
2435 struct nes_hw_cqp_wqe *cqp_wqe;
2436 u32 head;
2437 u32 cq_size;
2438 u32 cqe_count=0;
2439 u32 error_code;
2440 /* u32 counter; */
2441
2442 head = cq->cq_head;
2443 cq_size = cq->cq_size;
2444
2445 do {
2446 /* process the CQE */
2447 /* nes_debug(NES_DBG_CQP, "head=%u cqe_words=%08X\n", head,
2448 le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX])); */
2449
2450 if (le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX]) & NES_CQE_VALID) {
2451 u64temp = (((u64)(le32_to_cpu(cq->cq_vbase[head].
2452 cqe_words[NES_CQE_COMP_COMP_CTX_HIGH_IDX])))<<32) |
2453 ((u64)(le32_to_cpu(cq->cq_vbase[head].
2454 cqe_words[NES_CQE_COMP_COMP_CTX_LOW_IDX])));
2455 cqp = *((struct nes_hw_cqp **)&u64temp);
2456
2457 error_code = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_ERROR_CODE_IDX]);
2458 if (error_code) {
2459 nes_debug(NES_DBG_CQP, "Bad Completion code for opcode 0x%02X from CQP,"
2460 " Major/Minor codes = 0x%04X:%04X.\n",
2461 le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX])&0x3f,
2462 (u16)(error_code >> 16),
2463 (u16)error_code);
2464 nes_debug(NES_DBG_CQP, "cqp: qp_id=%u, sq_head=%u, sq_tail=%u\n",
2465 cqp->qp_id, cqp->sq_head, cqp->sq_tail);
2466 }
2467
2468 u64temp = (((u64)(le32_to_cpu(nesdev->cqp.sq_vbase[cqp->sq_tail].
2469 wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX])))<<32) |
2470 ((u64)(le32_to_cpu(nesdev->cqp.sq_vbase[cqp->sq_tail].
2471 wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX])));
2472 cqp_request = *((struct nes_cqp_request **)&u64temp);
2473 if (cqp_request) {
2474 if (cqp_request->waiting) {
2475 /* nes_debug(NES_DBG_CQP, "%s: Waking up requestor\n"); */
2476 cqp_request->major_code = (u16)(error_code >> 16);
2477 cqp_request->minor_code = (u16)error_code;
2478 barrier();
2479 cqp_request->request_done = 1;
2480 wake_up(&cqp_request->waitq);
2481 if (atomic_dec_and_test(&cqp_request->refcount)) {
2482 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) freed.\n",
2483 cqp_request,
2484 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f);
2485 if (cqp_request->dynamic) {
2486 kfree(cqp_request);
2487 } else {
2488 spin_lock_irqsave(&nesdev->cqp.lock, flags);
2489 list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
2490 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
2491 }
2492 }
2493 } else if (cqp_request->callback) {
2494 /* Envoke the callback routine */
2495 cqp_request->cqp_callback(nesdev, cqp_request);
2496 if (cqp_request->dynamic) {
2497 kfree(cqp_request);
2498 } else {
2499 spin_lock_irqsave(&nesdev->cqp.lock, flags);
2500 list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
2501 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
2502 }
2503 } else {
2504 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) freed.\n",
2505 cqp_request,
2506 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f);
2507 if (cqp_request->dynamic) {
2508 kfree(cqp_request);
2509 } else {
2510 spin_lock_irqsave(&nesdev->cqp.lock, flags);
2511 list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
2512 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
2513 }
2514 }
2515 } else {
2516 wake_up(&nesdev->cqp.waitq);
2517 }
2518
2519 cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX] = 0;
2520 nes_write32(nesdev->regs+NES_CQE_ALLOC, cq->cq_number | (1 << 16));
2521 if (++cqp->sq_tail >= cqp->sq_size)
2522 cqp->sq_tail = 0;
2523
2524 /* Accounting... */
2525 cqe_count++;
2526 if (++head >= cq_size)
2527 head = 0;
2528 } else {
2529 break;
2530 }
2531 } while (1);
2532 cq->cq_head = head;
2533
2534 spin_lock_irqsave(&nesdev->cqp.lock, flags);
2535 while ((!list_empty(&nesdev->cqp_pending_reqs)) &&
2536 ((((nesdev->cqp.sq_tail+nesdev->cqp.sq_size)-nesdev->cqp.sq_head) &
2537 (nesdev->cqp.sq_size - 1)) != 1)) {
2538 cqp_request = list_entry(nesdev->cqp_pending_reqs.next,
2539 struct nes_cqp_request, list);
2540 list_del_init(&cqp_request->list);
2541 head = nesdev->cqp.sq_head++;
2542 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
2543 cqp_wqe = &nesdev->cqp.sq_vbase[head];
2544 memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
2545 barrier();
2546 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] =
2547 cpu_to_le32((u32)((unsigned long)cqp_request));
2548 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] =
2549 cpu_to_le32((u32)(upper_32_bits((unsigned long)cqp_request)));
2550 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) put on CQPs SQ wqe%u.\n",
2551 cqp_request, le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f, head);
2552 /* Ring doorbell (1 WQEs) */
2553 barrier();
2554 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
2555 }
2556 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
2557
2558 /* Arm the CCQ */
2559 nes_write32(nesdev->regs+NES_CQE_ALLOC, NES_CQE_ALLOC_NOTIFY_NEXT |
2560 cq->cq_number);
2561 nes_read32(nesdev->regs+NES_CQE_ALLOC);
2562 }
2563
2564
2565 /**
2566 * nes_process_iwarp_aeqe
2567 */
2568 void nes_process_iwarp_aeqe(struct nes_device *nesdev, struct nes_hw_aeqe *aeqe)
2569 {
2570 u64 context;
2571 u64 aeqe_context = 0;
2572 unsigned long flags;
2573 struct nes_qp *nesqp;
2574 int resource_allocated;
2575 /* struct iw_cm_id *cm_id; */
2576 struct nes_adapter *nesadapter = nesdev->nesadapter;
2577 struct ib_event ibevent;
2578 /* struct iw_cm_event cm_event; */
2579 u32 aeq_info;
2580 u32 next_iwarp_state = 0;
2581 u16 async_event_id;
2582 u8 tcp_state;
2583 u8 iwarp_state;
2584
2585 nes_debug(NES_DBG_AEQ, "\n");
2586 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
2587 if ((NES_AEQE_INBOUND_RDMA&aeq_info) || (!(NES_AEQE_QP&aeq_info))) {
2588 context = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_LOW_IDX]);
2589 context += ((u64)le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_HIGH_IDX])) << 32;
2590 } else {
2591 aeqe_context = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_LOW_IDX]);
2592 aeqe_context += ((u64)le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_HIGH_IDX])) << 32;
2593 context = (unsigned long)nesadapter->qp_table[le32_to_cpu(
2594 aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX])-NES_FIRST_QPN];
2595 BUG_ON(!context);
2596 }
2597
2598 async_event_id = (u16)aeq_info;
2599 tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT;
2600 iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT;
2601 nes_debug(NES_DBG_AEQ, "aeid = 0x%04X, qp-cq id = %d, aeqe = %p,"
2602 " Tcp state = %s, iWARP state = %s\n",
2603 async_event_id,
2604 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]), aeqe,
2605 nes_tcp_state_str[tcp_state], nes_iwarp_state_str[iwarp_state]);
2606
2607
2608 switch (async_event_id) {
2609 case NES_AEQE_AEID_LLP_FIN_RECEIVED:
2610 nesqp = *((struct nes_qp **)&context);
2611 if (atomic_inc_return(&nesqp->close_timer_started) == 1) {
2612 nesqp->cm_id->add_ref(nesqp->cm_id);
2613 nes_add_ref(&nesqp->ibqp);
2614 schedule_nes_timer(nesqp->cm_node, (struct sk_buff *)nesqp,
2615 NES_TIMER_TYPE_CLOSE, 1, 0);
2616 nes_debug(NES_DBG_AEQ, "QP%u Not decrementing QP refcount (%d),"
2617 " need ae to finish up, original_last_aeq = 0x%04X."
2618 " last_aeq = 0x%04X, scheduling timer. TCP state = %d\n",
2619 nesqp->hwqp.qp_id, atomic_read(&nesqp->refcount),
2620 async_event_id, nesqp->last_aeq, tcp_state);
2621 }
2622 if ((tcp_state != NES_AEQE_TCP_STATE_CLOSE_WAIT) ||
2623 (nesqp->ibqp_state != IB_QPS_RTS)) {
2624 /* FIN Received but tcp state or IB state moved on,
2625 should expect a close complete */
2626 return;
2627 }
2628 case NES_AEQE_AEID_LLP_CLOSE_COMPLETE:
2629 case NES_AEQE_AEID_LLP_CONNECTION_RESET:
2630 case NES_AEQE_AEID_TERMINATE_SENT:
2631 case NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE:
2632 case NES_AEQE_AEID_RESET_SENT:
2633 nesqp = *((struct nes_qp **)&context);
2634 if (async_event_id == NES_AEQE_AEID_RESET_SENT) {
2635 tcp_state = NES_AEQE_TCP_STATE_CLOSED;
2636 }
2637 nes_add_ref(&nesqp->ibqp);
2638 spin_lock_irqsave(&nesqp->lock, flags);
2639 nesqp->hw_iwarp_state = iwarp_state;
2640 nesqp->hw_tcp_state = tcp_state;
2641 nesqp->last_aeq = async_event_id;
2642
2643 if ((tcp_state == NES_AEQE_TCP_STATE_CLOSED) ||
2644 (tcp_state == NES_AEQE_TCP_STATE_TIME_WAIT)) {
2645 nesqp->hte_added = 0;
2646 spin_unlock_irqrestore(&nesqp->lock, flags);
2647 nes_debug(NES_DBG_AEQ, "issuing hw modifyqp for QP%u to remove hte\n",
2648 nesqp->hwqp.qp_id);
2649 nes_hw_modify_qp(nesdev, nesqp,
2650 NES_CQP_QP_IWARP_STATE_ERROR | NES_CQP_QP_DEL_HTE, 0);
2651 spin_lock_irqsave(&nesqp->lock, flags);
2652 }
2653
2654 if ((nesqp->ibqp_state == IB_QPS_RTS) &&
2655 ((tcp_state == NES_AEQE_TCP_STATE_CLOSE_WAIT) ||
2656 (async_event_id == NES_AEQE_AEID_LLP_CONNECTION_RESET))) {
2657 switch (nesqp->hw_iwarp_state) {
2658 case NES_AEQE_IWARP_STATE_RTS:
2659 next_iwarp_state = NES_CQP_QP_IWARP_STATE_CLOSING;
2660 nesqp->hw_iwarp_state = NES_AEQE_IWARP_STATE_CLOSING;
2661 break;
2662 case NES_AEQE_IWARP_STATE_TERMINATE:
2663 next_iwarp_state = NES_CQP_QP_IWARP_STATE_TERMINATE;
2664 nesqp->hw_iwarp_state = NES_AEQE_IWARP_STATE_TERMINATE;
2665 if (async_event_id == NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE) {
2666 next_iwarp_state |= 0x02000000;
2667 nesqp->hw_tcp_state = NES_AEQE_TCP_STATE_CLOSED;
2668 }
2669 break;
2670 default:
2671 next_iwarp_state = 0;
2672 }
2673 spin_unlock_irqrestore(&nesqp->lock, flags);
2674 if (next_iwarp_state) {
2675 nes_add_ref(&nesqp->ibqp);
2676 nes_debug(NES_DBG_AEQ, "issuing hw modifyqp for QP%u. next state = 0x%08X,"
2677 " also added another reference\n",
2678 nesqp->hwqp.qp_id, next_iwarp_state);
2679 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0);
2680 }
2681 nes_cm_disconn(nesqp);
2682 } else {
2683 if (async_event_id == NES_AEQE_AEID_LLP_FIN_RECEIVED) {
2684 /* FIN Received but ib state not RTS,
2685 close complete will be on its way */
2686 spin_unlock_irqrestore(&nesqp->lock, flags);
2687 nes_rem_ref(&nesqp->ibqp);
2688 return;
2689 }
2690 spin_unlock_irqrestore(&nesqp->lock, flags);
2691 if (async_event_id == NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE) {
2692 next_iwarp_state = NES_CQP_QP_IWARP_STATE_TERMINATE | 0x02000000;
2693 nesqp->hw_tcp_state = NES_AEQE_TCP_STATE_CLOSED;
2694 nes_debug(NES_DBG_AEQ, "issuing hw modifyqp for QP%u. next state = 0x%08X,"
2695 " also added another reference\n",
2696 nesqp->hwqp.qp_id, next_iwarp_state);
2697 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0);
2698 }
2699 nes_cm_disconn(nesqp);
2700 }
2701 break;
2702 case NES_AEQE_AEID_LLP_TERMINATE_RECEIVED:
2703 nesqp = *((struct nes_qp **)&context);
2704 spin_lock_irqsave(&nesqp->lock, flags);
2705 nesqp->hw_iwarp_state = iwarp_state;
2706 nesqp->hw_tcp_state = tcp_state;
2707 nesqp->last_aeq = async_event_id;
2708 spin_unlock_irqrestore(&nesqp->lock, flags);
2709 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_LLP_TERMINATE_RECEIVED"
2710 " event on QP%u \n Q2 Data:\n",
2711 nesqp->hwqp.qp_id);
2712 if (nesqp->ibqp.event_handler) {
2713 ibevent.device = nesqp->ibqp.device;
2714 ibevent.element.qp = &nesqp->ibqp;
2715 ibevent.event = IB_EVENT_QP_FATAL;
2716 nesqp->ibqp.event_handler(&ibevent, nesqp->ibqp.qp_context);
2717 }
2718 if ((tcp_state == NES_AEQE_TCP_STATE_CLOSE_WAIT) ||
2719 ((nesqp->ibqp_state == IB_QPS_RTS)&&
2720 (async_event_id == NES_AEQE_AEID_LLP_CONNECTION_RESET))) {
2721 nes_add_ref(&nesqp->ibqp);
2722 nes_cm_disconn(nesqp);
2723 } else {
2724 nesqp->in_disconnect = 0;
2725 wake_up(&nesqp->kick_waitq);
2726 }
2727 break;
2728 case NES_AEQE_AEID_LLP_TOO_MANY_RETRIES:
2729 nesqp = *((struct nes_qp **)&context);
2730 nes_add_ref(&nesqp->ibqp);
2731 spin_lock_irqsave(&nesqp->lock, flags);
2732 nesqp->hw_iwarp_state = NES_AEQE_IWARP_STATE_ERROR;
2733 nesqp->hw_tcp_state = NES_AEQE_TCP_STATE_CLOSED;
2734 nesqp->last_aeq = async_event_id;
2735 if (nesqp->cm_id) {
2736 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_LLP_TOO_MANY_RETRIES"
2737 " event on QP%u, remote IP = 0x%08X \n",
2738 nesqp->hwqp.qp_id,
2739 ntohl(nesqp->cm_id->remote_addr.sin_addr.s_addr));
2740 } else {
2741 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_LLP_TOO_MANY_RETRIES"
2742 " event on QP%u \n",
2743 nesqp->hwqp.qp_id);
2744 }
2745 spin_unlock_irqrestore(&nesqp->lock, flags);
2746 next_iwarp_state = NES_CQP_QP_IWARP_STATE_ERROR | NES_CQP_QP_RESET;
2747 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0);
2748 if (nesqp->ibqp.event_handler) {
2749 ibevent.device = nesqp->ibqp.device;
2750 ibevent.element.qp = &nesqp->ibqp;
2751 ibevent.event = IB_EVENT_QP_FATAL;
2752 nesqp->ibqp.event_handler(&ibevent, nesqp->ibqp.qp_context);
2753 }
2754 break;
2755 case NES_AEQE_AEID_AMP_BAD_STAG_INDEX:
2756 if (NES_AEQE_INBOUND_RDMA&aeq_info) {
2757 nesqp = nesadapter->qp_table[le32_to_cpu(
2758 aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX])-NES_FIRST_QPN];
2759 } else {
2760 /* TODO: get the actual WQE and mask off wqe index */
2761 context &= ~((u64)511);
2762 nesqp = *((struct nes_qp **)&context);
2763 }
2764 spin_lock_irqsave(&nesqp->lock, flags);
2765 nesqp->hw_iwarp_state = iwarp_state;
2766 nesqp->hw_tcp_state = tcp_state;
2767 nesqp->last_aeq = async_event_id;
2768 spin_unlock_irqrestore(&nesqp->lock, flags);
2769 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_AMP_BAD_STAG_INDEX event on QP%u\n",
2770 nesqp->hwqp.qp_id);
2771 if (nesqp->ibqp.event_handler) {
2772 ibevent.device = nesqp->ibqp.device;
2773 ibevent.element.qp = &nesqp->ibqp;
2774 ibevent.event = IB_EVENT_QP_ACCESS_ERR;
2775 nesqp->ibqp.event_handler(&ibevent, nesqp->ibqp.qp_context);
2776 }
2777 break;
2778 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG:
2779 nesqp = *((struct nes_qp **)&context);
2780 spin_lock_irqsave(&nesqp->lock, flags);
2781 nesqp->hw_iwarp_state = iwarp_state;
2782 nesqp->hw_tcp_state = tcp_state;
2783 nesqp->last_aeq = async_event_id;
2784 spin_unlock_irqrestore(&nesqp->lock, flags);
2785 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_AMP_UNALLOCATED_STAG event on QP%u\n",
2786 nesqp->hwqp.qp_id);
2787 if (nesqp->ibqp.event_handler) {
2788 ibevent.device = nesqp->ibqp.device;
2789 ibevent.element.qp = &nesqp->ibqp;
2790 ibevent.event = IB_EVENT_QP_ACCESS_ERR;
2791 nesqp->ibqp.event_handler(&ibevent, nesqp->ibqp.qp_context);
2792 }
2793 break;
2794 case NES_AEQE_AEID_PRIV_OPERATION_DENIED:
2795 nesqp = nesadapter->qp_table[le32_to_cpu(aeqe->aeqe_words
2796 [NES_AEQE_COMP_QP_CQ_ID_IDX])-NES_FIRST_QPN];
2797 spin_lock_irqsave(&nesqp->lock, flags);
2798 nesqp->hw_iwarp_state = iwarp_state;
2799 nesqp->hw_tcp_state = tcp_state;
2800 nesqp->last_aeq = async_event_id;
2801 spin_unlock_irqrestore(&nesqp->lock, flags);
2802 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_PRIV_OPERATION_DENIED event on QP%u,"
2803 " nesqp = %p, AE reported %p\n",
2804 nesqp->hwqp.qp_id, nesqp, *((struct nes_qp **)&context));
2805 if (nesqp->ibqp.event_handler) {
2806 ibevent.device = nesqp->ibqp.device;
2807 ibevent.element.qp = &nesqp->ibqp;
2808 ibevent.event = IB_EVENT_QP_ACCESS_ERR;
2809 nesqp->ibqp.event_handler(&ibevent, nesqp->ibqp.qp_context);
2810 }
2811 break;
2812 case NES_AEQE_AEID_CQ_OPERATION_ERROR:
2813 context <<= 1;
2814 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u, %p\n",
2815 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]), (void *)(unsigned long)context);
2816 resource_allocated = nes_is_resource_allocated(nesadapter, nesadapter->allocated_cqs,
2817 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]));
2818 if (resource_allocated) {
2819 printk(KERN_ERR PFX "%s: Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u\n",
2820 __FUNCTION__, le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]));
2821 }
2822 break;
2823 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
2824 nesqp = nesadapter->qp_table[le32_to_cpu(
2825 aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX])-NES_FIRST_QPN];
2826 spin_lock_irqsave(&nesqp->lock, flags);
2827 nesqp->hw_iwarp_state = iwarp_state;
2828 nesqp->hw_tcp_state = tcp_state;
2829 nesqp->last_aeq = async_event_id;
2830 spin_unlock_irqrestore(&nesqp->lock, flags);
2831 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG"
2832 "_FOR_AVAILABLE_BUFFER event on QP%u\n",
2833 nesqp->hwqp.qp_id);
2834 if (nesqp->ibqp.event_handler) {
2835 ibevent.device = nesqp->ibqp.device;
2836 ibevent.element.qp = &nesqp->ibqp;
2837 ibevent.event = IB_EVENT_QP_ACCESS_ERR;
2838 nesqp->ibqp.event_handler(&ibevent, nesqp->ibqp.qp_context);
2839 }
2840 /* tell cm to disconnect, cm will queue work to thread */
2841 nes_add_ref(&nesqp->ibqp);
2842 nes_cm_disconn(nesqp);
2843 break;
2844 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
2845 nesqp = *((struct nes_qp **)&context);
2846 spin_lock_irqsave(&nesqp->lock, flags);
2847 nesqp->hw_iwarp_state = iwarp_state;
2848 nesqp->hw_tcp_state = tcp_state;
2849 nesqp->last_aeq = async_event_id;
2850 spin_unlock_irqrestore(&nesqp->lock, flags);
2851 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_DDP_UBE_INVALID_MSN"
2852 "_NO_BUFFER_AVAILABLE event on QP%u\n",
2853 nesqp->hwqp.qp_id);
2854 if (nesqp->ibqp.event_handler) {
2855 ibevent.device = nesqp->ibqp.device;
2856 ibevent.element.qp = &nesqp->ibqp;
2857 ibevent.event = IB_EVENT_QP_FATAL;
2858 nesqp->ibqp.event_handler(&ibevent, nesqp->ibqp.qp_context);
2859 }
2860 /* tell cm to disconnect, cm will queue work to thread */
2861 nes_add_ref(&nesqp->ibqp);
2862 nes_cm_disconn(nesqp);
2863 break;
2864 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR:
2865 nesqp = *((struct nes_qp **)&context);
2866 spin_lock_irqsave(&nesqp->lock, flags);
2867 nesqp->hw_iwarp_state = iwarp_state;
2868 nesqp->hw_tcp_state = tcp_state;
2869 nesqp->last_aeq = async_event_id;
2870 spin_unlock_irqrestore(&nesqp->lock, flags);
2871 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR"
2872 " event on QP%u \n Q2 Data:\n",
2873 nesqp->hwqp.qp_id);
2874 if (nesqp->ibqp.event_handler) {
2875 ibevent.device = nesqp->ibqp.device;
2876 ibevent.element.qp = &nesqp->ibqp;
2877 ibevent.event = IB_EVENT_QP_FATAL;
2878 nesqp->ibqp.event_handler(&ibevent, nesqp->ibqp.qp_context);
2879 }
2880 /* tell cm to disconnect, cm will queue work to thread */
2881 nes_add_ref(&nesqp->ibqp);
2882 nes_cm_disconn(nesqp);
2883 break;
2884 /* TODO: additional AEs need to be here */
2885 default:
2886 nes_debug(NES_DBG_AEQ, "Processing an iWARP related AE for QP, misc = 0x%04X\n",
2887 async_event_id);
2888 break;
2889 }
2890
2891 }
2892
2893
2894 /**
2895 * nes_iwarp_ce_handler
2896 */
2897 void nes_iwarp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *hw_cq)
2898 {
2899 struct nes_cq *nescq = container_of(hw_cq, struct nes_cq, hw_cq);
2900
2901 /* nes_debug(NES_DBG_CQ, "Processing completion event for iWARP CQ%u.\n",
2902 nescq->hw_cq.cq_number); */
2903 nes_write32(nesdev->regs+NES_CQ_ACK, nescq->hw_cq.cq_number);
2904
2905 if (nescq->ibcq.comp_handler)
2906 nescq->ibcq.comp_handler(&nescq->ibcq, nescq->ibcq.cq_context);
2907
2908 return;
2909 }
2910
2911
2912 /**
2913 * nes_manage_apbvt()
2914 */
2915 int nes_manage_apbvt(struct nes_vnic *nesvnic, u32 accel_local_port,
2916 u32 nic_index, u32 add_port)
2917 {
2918 struct nes_device *nesdev = nesvnic->nesdev;
2919 struct nes_hw_cqp_wqe *cqp_wqe;
2920 unsigned long flags;
2921 struct nes_cqp_request *cqp_request;
2922 int ret = 0;
2923 u16 major_code;
2924
2925 /* Send manage APBVT request to CQP */
2926 cqp_request = nes_get_cqp_request(nesdev);
2927 if (cqp_request == NULL) {
2928 nes_debug(NES_DBG_QP, "Failed to get a cqp_request.\n");
2929 return -ENOMEM;
2930 }
2931 cqp_request->waiting = 1;
2932 cqp_wqe = &cqp_request->cqp_wqe;
2933
2934 nes_debug(NES_DBG_QP, "%s APBV for local port=%u(0x%04x), nic_index=%u\n",
2935 (add_port == NES_MANAGE_APBVT_ADD) ? "ADD" : "DEL",
2936 accel_local_port, accel_local_port, nic_index);
2937
2938 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
2939 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX, (NES_CQP_MANAGE_APBVT |
2940 ((add_port == NES_MANAGE_APBVT_ADD) ? NES_CQP_APBVT_ADD : 0)));
2941 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
2942 ((nic_index << NES_CQP_APBVT_NIC_SHIFT) | accel_local_port));
2943
2944 nes_debug(NES_DBG_QP, "Waiting for CQP completion for APBVT.\n");
2945
2946 atomic_set(&cqp_request->refcount, 2);
2947 nes_post_cqp_request(nesdev, cqp_request, NES_CQP_REQUEST_RING_DOORBELL);
2948
2949 if (add_port == NES_MANAGE_APBVT_ADD)
2950 ret = wait_event_timeout(cqp_request->waitq, (cqp_request->request_done != 0),
2951 NES_EVENT_TIMEOUT);
2952 nes_debug(NES_DBG_QP, "Completed, ret=%u, CQP Major:Minor codes = 0x%04X:0x%04X\n",
2953 ret, cqp_request->major_code, cqp_request->minor_code);
2954 major_code = cqp_request->major_code;
2955 if (atomic_dec_and_test(&cqp_request->refcount)) {
2956 if (cqp_request->dynamic) {
2957 kfree(cqp_request);
2958 } else {
2959 spin_lock_irqsave(&nesdev->cqp.lock, flags);
2960 list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
2961 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
2962 }
2963 }
2964 if (!ret)
2965 return -ETIME;
2966 else if (major_code)
2967 return -EIO;
2968 else
2969 return 0;
2970 }
2971
2972
2973 /**
2974 * nes_manage_arp_cache
2975 */
2976 void nes_manage_arp_cache(struct net_device *netdev, unsigned char *mac_addr,
2977 u32 ip_addr, u32 action)
2978 {
2979 struct nes_hw_cqp_wqe *cqp_wqe;
2980 struct nes_vnic *nesvnic = netdev_priv(netdev);
2981 struct nes_device *nesdev;
2982 struct nes_cqp_request *cqp_request;
2983 int arp_index;
2984
2985 nesdev = nesvnic->nesdev;
2986 arp_index = nes_arp_table(nesdev, ip_addr, mac_addr, action);
2987 if (arp_index == -1) {
2988 return;
2989 }
2990
2991 /* update the ARP entry */
2992 cqp_request = nes_get_cqp_request(nesdev);
2993 if (cqp_request == NULL) {
2994 nes_debug(NES_DBG_NETDEV, "Failed to get a cqp_request.\n");
2995 return;
2996 }
2997 cqp_request->waiting = 0;
2998 cqp_wqe = &cqp_request->cqp_wqe;
2999 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3000
3001 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(
3002 NES_CQP_MANAGE_ARP_CACHE | NES_CQP_ARP_PERM);
3003 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] |= cpu_to_le32(
3004 (u32)PCI_FUNC(nesdev->pcidev->devfn) << NES_CQP_ARP_AEQ_INDEX_SHIFT);
3005 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(arp_index);
3006
3007 if (action == NES_ARP_ADD) {
3008 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] |= cpu_to_le32(NES_CQP_ARP_VALID);
3009 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX] = cpu_to_le32(
3010 (((u32)mac_addr[2]) << 24) | (((u32)mac_addr[3]) << 16) |
3011 (((u32)mac_addr[4]) << 8) | (u32)mac_addr[5]);
3012 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_HIGH_IDX] = cpu_to_le32(
3013 (((u32)mac_addr[0]) << 16) | (u32)mac_addr[1]);
3014 } else {
3015 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX] = 0;
3016 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_HIGH_IDX] = 0;
3017 }
3018
3019 nes_debug(NES_DBG_NETDEV, "Not waiting for CQP, cqp.sq_head=%u, cqp.sq_tail=%u\n",
3020 nesdev->cqp.sq_head, nesdev->cqp.sq_tail);
3021
3022 atomic_set(&cqp_request->refcount, 1);
3023 nes_post_cqp_request(nesdev, cqp_request, NES_CQP_REQUEST_RING_DOORBELL);
3024 }
3025
3026
3027 /**
3028 * flush_wqes
3029 */
3030 void flush_wqes(struct nes_device *nesdev, struct nes_qp *nesqp,
3031 u32 which_wq, u32 wait_completion)
3032 {
3033 unsigned long flags;
3034 struct nes_cqp_request *cqp_request;
3035 struct nes_hw_cqp_wqe *cqp_wqe;
3036 int ret;
3037
3038 cqp_request = nes_get_cqp_request(nesdev);
3039 if (cqp_request == NULL) {
3040 nes_debug(NES_DBG_QP, "Failed to get a cqp_request.\n");
3041 return;
3042 }
3043 if (wait_completion) {
3044 cqp_request->waiting = 1;
3045 atomic_set(&cqp_request->refcount, 2);
3046 } else {
3047 cqp_request->waiting = 0;
3048 }
3049 cqp_wqe = &cqp_request->cqp_wqe;
3050 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3051
3052 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] =
3053 cpu_to_le32(NES_CQP_FLUSH_WQES | which_wq);
3054 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesqp->hwqp.qp_id);
3055
3056 nes_post_cqp_request(nesdev, cqp_request, NES_CQP_REQUEST_RING_DOORBELL);
3057
3058 if (wait_completion) {
3059 /* Wait for CQP */
3060 ret = wait_event_timeout(cqp_request->waitq, (cqp_request->request_done != 0),
3061 NES_EVENT_TIMEOUT);
3062 nes_debug(NES_DBG_QP, "Flush SQ QP WQEs completed, ret=%u,"
3063 " CQP Major:Minor codes = 0x%04X:0x%04X\n",
3064 ret, cqp_request->major_code, cqp_request->minor_code);
3065 if (atomic_dec_and_test(&cqp_request->refcount)) {
3066 if (cqp_request->dynamic) {
3067 kfree(cqp_request);
3068 } else {
3069 spin_lock_irqsave(&nesdev->cqp.lock, flags);
3070 list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
3071 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
3072 }
3073 }
3074 }
3075 }
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