drivers/ide/pci/sl82c105.c

   1 /*
   2  * SL82C105/Winbond 553 IDE driver
   3  *
   4  * Maintainer unknown.
   5  *
   6  * Drive tuning added from Rebel.com's kernel sources
   7  *  -- Russell King (15/11/98) linux@arm.linux.org.uk
   8  *
   9  * Merge in Russell's HW workarounds, fix various problems
  10  * with the timing registers setup.
  11  *  -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
  12  *
  13  * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
  14  * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/hdreg.h>
  21 #include <linux/pci.h>
  22 #include <linux/ide.h>
  23
  24 #include <asm/io.h>
  25
  26 #undef DEBUG
  27
  28 #ifdef DEBUG
  29 #define DBG(arg) printk arg
  30 #else
  31 #define DBG(fmt,...)
  32 #endif
  33 /*
  34  * SL82C105 PCI config register 0x40 bits.
  35  */
  36 #define CTRL_IDE_IRQB   (1 << 30)
  37 #define CTRL_IDE_IRQA   (1 << 28)
  38 #define CTRL_LEGIRQ     (1 << 11)
  39 #define CTRL_P1F16      (1 << 5)
  40 #define CTRL_P1EN       (1 << 4)
  41 #define CTRL_P0F16      (1 << 1)
  42 #define CTRL_P0EN       (1 << 0)
  43
  44 /*
  45  * Convert a PIO mode and cycle time to the required on/off times
  46  * for the interface.  This has protection against runaway timings.
  47  */
  48 static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
  49 {
  50         unsigned int cmd_on, cmd_off;
  51         u8 iordy = 0;
  52
  53         cmd_on  = (ide_pio_timings[pio].active_time + 29) / 30;
  54         cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
  55
  56         if (cmd_on == 0)
  57                 cmd_on = 1;
  58
  59         if (cmd_off == 0)
  60                 cmd_off = 1;
  61
  62         if (pio > 2 || ide_dev_has_iordy(drive->id))
  63                 iordy = 0x40;
  64
  65         return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
  66 }
  67
  68 /*
  69  * Configure the chipset for PIO mode.
  70  */
  71 static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
  72 {
  73         struct pci_dev *dev     = to_pci_dev(drive->hwif->dev);
  74         int reg                 = 0x44 + drive->dn * 4;
  75         u16 drv_ctrl;
  76
  77         drv_ctrl = get_pio_timings(drive, pio);
  78
  79         /*
  80          * Store the PIO timings so that we can restore them
  81          * in case DMA will be turned off...
  82          */
  83         drive->drive_data &= 0xffff0000;
  84         drive->drive_data |= drv_ctrl;
  85
  86         pci_write_config_word(dev, reg,  drv_ctrl);
  87         pci_read_config_word (dev, reg, &drv_ctrl);
  88
  89         printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
  90                           ide_xfer_verbose(pio + XFER_PIO_0),
  91                           ide_pio_cycle_time(drive, pio), drv_ctrl);
  92 }
  93
  94 /*
  95  * Configure the chipset for DMA mode.
  96  */
  97 static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
  98 {
  99         static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
 100         u16 drv_ctrl;
 101
 102         DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
 103              drive->name, ide_xfer_verbose(speed)));
 104
 105         drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
 106
 107         /*
 108          * Store the DMA timings so that we can actually program
 109          * them when DMA will be turned on...
 110          */
 111         drive->drive_data &= 0x0000ffff;
 112         drive->drive_data |= (unsigned long)drv_ctrl << 16;
 113 }
 114
 115 /*
 116  * The SL82C105 holds off all IDE interrupts while in DMA mode until
 117  * all DMA activity is completed.  Sometimes this causes problems (eg,
 118  * when the drive wants to report an error condition).
 119  *
 120  * 0x7e is a "chip testing" register.  Bit 2 resets the DMA controller
 121  * state machine.  We need to kick this to work around various bugs.
 122  */
 123 static inline void sl82c105_reset_host(struct pci_dev *dev)
 124 {
 125         u16 val;
 126
 127         pci_read_config_word(dev, 0x7e, &val);
 128         pci_write_config_word(dev, 0x7e, val | (1 << 2));
 129         pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
 130 }
 131
 132 /*
 133  * If we get an IRQ timeout, it might be that the DMA state machine
 134  * got confused.  Fix from Todd Inglett.  Details from Winbond.
 135  *
 136  * This function is called when the IDE timer expires, the drive
 137  * indicates that it is READY, and we were waiting for DMA to complete.
 138  */
 139 static void sl82c105_dma_lost_irq(ide_drive_t *drive)
 140 {
 141         ide_hwif_t *hwif        = HWIF(drive);
 142         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 143         u32 val, mask           = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
 144         u8 dma_cmd;
 145
 146         printk("sl82c105: lost IRQ, resetting host\n");
 147
 148         /*
 149          * Check the raw interrupt from the drive.
 150          */
 151         pci_read_config_dword(dev, 0x40, &val);
 152         if (val & mask)
 153                 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
 154
 155         /*
 156          * Was DMA enabled?  If so, disable it - we're resetting the
 157          * host.  The IDE layer will be handling the drive for us.
 158          */
 159         dma_cmd = inb(hwif->dma_command);
 160         if (dma_cmd & 1) {
 161                 outb(dma_cmd & ~1, hwif->dma_command);
 162                 printk("sl82c105: DMA was enabled\n");
 163         }
 164
 165         sl82c105_reset_host(dev);
 166 }
 167
 168 /*
 169  * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
 170  * Winbond recommend that the DMA state machine is reset prior to
 171  * setting the bus master DMA enable bit.
 172  *
 173  * The generic IDE core will have disabled the BMEN bit before this
 174  * function is called.
 175  */
 176 static void sl82c105_dma_start(ide_drive_t *drive)
 177 {
 178         ide_hwif_t *hwif        = HWIF(drive);
 179         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 180         int reg                 = 0x44 + drive->dn * 4;
 181
 182         DBG(("%s(drive:%s)\n", __FUNCTION__, drive->name));
 183
 184         pci_write_config_word(dev, reg, drive->drive_data >> 16);
 185
 186         sl82c105_reset_host(dev);
 187         ide_dma_start(drive);
 188 }
 189
 190 static void sl82c105_dma_timeout(ide_drive_t *drive)
 191 {
 192         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
 193
 194         DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name));
 195
 196         sl82c105_reset_host(dev);
 197         ide_dma_timeout(drive);
 198 }
 199
 200 static int sl82c105_dma_end(ide_drive_t *drive)
 201 {
 202         struct pci_dev *dev     = to_pci_dev(drive->hwif->dev);
 203         int reg                 = 0x44 + drive->dn * 4;
 204         int ret;
 205
 206         DBG(("%s(drive:%s)\n", __FUNCTION__, drive->name));
 207
 208         ret = __ide_dma_end(drive);
 209
 210         pci_write_config_word(dev, reg, drive->drive_data);
 211
 212         return ret;
 213 }
 214
 215 /*
 216  * ATA reset will clear the 16 bits mode in the control
 217  * register, we need to reprogram it
 218  */
 219 static void sl82c105_resetproc(ide_drive_t *drive)
 220 {
 221         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
 222         u32 val;
 223
 224         DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
 225
 226         pci_read_config_dword(dev, 0x40, &val);
 227         val |= (CTRL_P1F16 | CTRL_P0F16);
 228         pci_write_config_dword(dev, 0x40, val);
 229 }
 230
 231 /*
 232  * Return the revision of the Winbond bridge
 233  * which this function is part of.
 234  */
 235 static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
 236 {
 237         struct pci_dev *bridge;
 238
 239         /*
 240          * The bridge should be part of the same device, but function 0.
 241          */
 242         bridge = pci_get_bus_and_slot(dev->bus->number,
 243                                PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
 244         if (!bridge)
 245                 return -1;
 246
 247         /*
 248          * Make sure it is a Winbond 553 and is an ISA bridge.
 249          */
 250         if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
 251             bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
 252             bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
 253                 pci_dev_put(bridge);
 254                 return -1;
 255         }
 256         /*
 257          * We need to find function 0's revision, not function 1
 258          */
 259         pci_dev_put(bridge);
 260
 261         return bridge->revision;
 262 }
 263
 264 /*
 265  * Enable the PCI device
 266  *
 267  * --BenH: It's arch fixup code that should enable channels that
 268  * have not been enabled by firmware. I decided we can still enable
 269  * channel 0 here at least, but channel 1 has to be enabled by
 270  * firmware or arch code. We still set both to 16 bits mode.
 271  */
 272 static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
 273 {
 274         u32 val;
 275
 276         DBG(("init_chipset_sl82c105()\n"));
 277
 278         pci_read_config_dword(dev, 0x40, &val);
 279         val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
 280         pci_write_config_dword(dev, 0x40, val);
 281
 282         return dev->irq;
 283 }
 284
 285 /*
 286  * Initialise IDE channel
 287  */
 288 static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
 289 {
 290         struct pci_dev *dev = to_pci_dev(hwif->dev);
 291         unsigned int rev;
 292
 293         DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
 294
 295         hwif->set_pio_mode      = &sl82c105_set_pio_mode;
 296         hwif->set_dma_mode      = &sl82c105_set_dma_mode;
 297         hwif->resetproc         = &sl82c105_resetproc;
 298
 299         if (!hwif->dma_base)
 300                 return;
 301
 302         rev = sl82c105_bridge_revision(dev);
 303         if (rev <= 5) {
 304                 /*
 305                  * Never ever EVER under any circumstances enable
 306                  * DMA when the bridge is this old.
 307                  */
 308                 printk("    %s: Winbond W83C553 bridge revision %d, "
 309                        "BM-DMA disabled\n", hwif->name, rev);
 310                 return;
 311         }
 312
 313         hwif->mwdma_mask = ATA_MWDMA2;
 314
 315         hwif->dma_lost_irq              = &sl82c105_dma_lost_irq;
 316         hwif->dma_start                 = &sl82c105_dma_start;
 317         hwif->ide_dma_end               = &sl82c105_dma_end;
 318         hwif->dma_timeout               = &sl82c105_dma_timeout;
 319
 320         if (hwif->mate)
 321                 hwif->serialized = hwif->mate->serialized = 1;
 322 }
 323
 324 static const struct ide_port_info sl82c105_chipset __devinitdata = {
 325         .name           = "W82C105",
 326         .init_chipset   = init_chipset_sl82c105,
 327         .init_hwif      = init_hwif_sl82c105,
 328         .enablebits     = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
 329         .host_flags     = IDE_HFLAG_IO_32BIT |
 330                           IDE_HFLAG_UNMASK_IRQS |
 331                           IDE_HFLAG_NO_AUTODMA |
 332                           IDE_HFLAG_BOOTABLE,
 333         .pio_mask       = ATA_PIO5,
 334 };
 335
 336 static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 337 {
 338         return ide_setup_pci_device(dev, &sl82c105_chipset);
 339 }
 340
 341 static const struct pci_device_id sl82c105_pci_tbl[] = {
 342         { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 },
 343         { 0, },
 344 };
 345 MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
 346
 347 static struct pci_driver driver = {
 348         .name           = "W82C105_IDE",
 349         .id_table       = sl82c105_pci_tbl,
 350         .probe          = sl82c105_init_one,
 351 };
 352
 353 static int __init sl82c105_ide_init(void)
 354 {
 355         return ide_pci_register_driver(&driver);
 356 }
 357
 358 module_init(sl82c105_ide_init);
 359
 360 MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
 361 MODULE_LICENSE("GPL");