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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / ide / pci / sis5513.c
blob512bb4c1fd5cdab9a2005fff535ea0838d3d2a90
1 /*
2 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
4 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 *
7 * May be copied or modified under the terms of the GNU General Public License
8 *
9 *
10 * Thanks :
11 *
12 * SiS Taiwan : for direct support and hardware.
13 * Daniela Engert : for initial ATA100 advices and numerous others.
14 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
15 * for checking code correctness, providing patches.
16 *
17 *
18 * Original tests and design on the SiS620 chipset.
19 * ATA100 tests and design on the SiS735 chipset.
20 * ATA16/33 support from specs
21 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
22 * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
23 *
24 * Documentation:
25 * SiS chipset documentation available under NDA to companies only
26 * (not to individuals).
27 */
28
29 /*
30 * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
31 * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
32 * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
33 *
34 * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
35 * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
36 * can figure out that we have a more modern and more capable 5513 by looking
37 * for the respective NorthBridge IDs.
38 *
39 * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
40 * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
41 * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
42 * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
43 * bits, changing its device id to the true one - 5517 for 961 and 5518 for
44 * 962/963.
45 */
46
47 #include <linux/types.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/hdreg.h>
51 #include <linux/pci.h>
52 #include <linux/init.h>
53 #include <linux/ide.h>
54
55 #include "ide-timing.h"
56
57 /* registers layout and init values are chipset family dependant */
58
59 #define ATA_16 0x01
60 #define ATA_33 0x02
61 #define ATA_66 0x03
62 #define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
63 #define ATA_100 0x05
64 #define ATA_133a 0x06 // SiS961b with 133 support
65 #define ATA_133 0x07 // SiS962/963
66
67 static u8 chipset_family;
68
69 /*
70 * Devices supported
71 */
72 static const struct {
73 const char *name;
74 u16 host_id;
75 u8 chipset_family;
76 u8 flags;
77 } SiSHostChipInfo[] = {
78 { "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 },
79 { "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 },
80 { "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 },
81 { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
82 { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
83 { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
84 { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
85 { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
86
87 { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
88 { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
89
90 { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
91 { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
92 { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
93 { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
94 { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
95
96 { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
97 { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
98 { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
99 { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
100 { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
101 { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
102
103 { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
104 { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
105 { "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 },
106 { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
107 };
108
109 /* Cycle time bits and values vary across chip dma capabilities
110 These three arrays hold the register layout and the values to set.
111 Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
112
113 /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
114 static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
115 static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
116 static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
117 {0,0,0,0,0,0,0}, /* no udma */
118 {0,0,0,0,0,0,0}, /* no udma */
119 {3,2,1,0,0,0,0}, /* ATA_33 */
120 {7,5,3,2,1,0,0}, /* ATA_66 */
121 {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
122 {11,7,5,4,2,1,0}, /* ATA_100 */
123 {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
124 {15,10,7,5,3,2,1}, /* ATA_133 */
125 };
126 /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
127 See SiS962 data sheet for more detail */
128 static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
129 {0,0,0,0,0,0,0}, /* no udma */
130 {0,0,0,0,0,0,0}, /* no udma */
131 {2,1,1,0,0,0,0},
132 {4,3,2,1,0,0,0},
133 {4,3,2,1,0,0,0},
134 {6,4,3,1,1,1,0},
135 {9,6,4,2,2,2,2},
136 {9,6,4,2,2,2,2},
137 };
138 /* Initialize time, Active time, Recovery time vary across
139 IDE clock settings. These 3 arrays hold the register value
140 for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
141 static u8 ini_time_value[][8] = {
142 {0,0,0,0,0,0,0,0},
143 {0,0,0,0,0,0,0,0},
144 {2,1,0,0,0,1,0,0},
145 {4,3,1,1,1,3,1,1},
146 {4,3,1,1,1,3,1,1},
147 {6,4,2,2,2,4,2,2},
148 {9,6,3,3,3,6,3,3},
149 {9,6,3,3,3,6,3,3},
150 };
151 static u8 act_time_value[][8] = {
152 {0,0,0,0,0,0,0,0},
153 {0,0,0,0,0,0,0,0},
154 {9,9,9,2,2,7,2,2},
155 {19,19,19,5,4,14,5,4},
156 {19,19,19,5,4,14,5,4},
157 {28,28,28,7,6,21,7,6},
158 {38,38,38,10,9,28,10,9},
159 {38,38,38,10,9,28,10,9},
160 };
161 static u8 rco_time_value[][8] = {
162 {0,0,0,0,0,0,0,0},
163 {0,0,0,0,0,0,0,0},
164 {9,2,0,2,0,7,1,1},
165 {19,5,1,5,2,16,3,2},
166 {19,5,1,5,2,16,3,2},
167 {30,9,3,9,4,25,6,4},
168 {40,12,4,12,5,34,12,5},
169 {40,12,4,12,5,34,12,5},
170 };
171
172 /*
173 * Printing configuration
174 */
175 /* Used for chipset type printing at boot time */
176 static char* chipset_capability[] = {
177 "ATA", "ATA 16",
178 "ATA 33", "ATA 66",
179 "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
180 "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
181 };
182
183 /*
184 * Configuration functions
185 */
186
187 static u8 sis_ata133_get_base(ide_drive_t *drive)
188 {
189 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
190 u32 reg54 = 0;
191
192 pci_read_config_dword(dev, 0x54, &reg54);
193
194 return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
195 }
196
197 static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
198 {
199 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
200 u16 t1 = 0;
201 u8 drive_pci = 0x40 + drive->dn * 2;
202
203 const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 };
204 const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };
205
206 pci_read_config_word(dev, drive_pci, &t1);
207
208 /* clear active/recovery timings */
209 t1 &= ~0x070f;
210 if (mode >= XFER_MW_DMA_0) {
211 if (chipset_family > ATA_16)
212 t1 &= ~0x8000; /* disable UDMA */
213 t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
214 } else
215 t1 |= pio_timings[mode - XFER_PIO_0];
216
217 pci_write_config_word(dev, drive_pci, t1);
218 }
219
220 static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
221 {
222 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
223 u8 t1, drive_pci = 0x40 + drive->dn * 2;
224
225 /* timing bits: 7:4 active 3:0 recovery */
226 const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
227 const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };
228
229 if (mode >= XFER_MW_DMA_0) {
230 u8 t2 = 0;
231
232 pci_read_config_byte(dev, drive_pci, &t2);
233 t2 &= ~0x80; /* disable UDMA */
234 pci_write_config_byte(dev, drive_pci, t2);
235
236 t1 = mwdma_timings[mode - XFER_MW_DMA_0];
237 } else
238 t1 = pio_timings[mode - XFER_PIO_0];
239
240 pci_write_config_byte(dev, drive_pci + 1, t1);
241 }
242
243 static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
244 {
245 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
246 u32 t1 = 0;
247 u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
248
249 pci_read_config_dword(dev, drive_pci, &t1);
250
251 t1 &= 0xc0c00fff;
252 clk = (t1 & 0x08) ? ATA_133 : ATA_100;
253 if (mode >= XFER_MW_DMA_0) {
254 t1 &= ~0x04; /* disable UDMA */
255 idx = mode - XFER_MW_DMA_0 + 5;
256 } else
257 idx = mode - XFER_PIO_0;
258 t1 |= ini_time_value[clk][idx] << 12;
259 t1 |= act_time_value[clk][idx] << 16;
260 t1 |= rco_time_value[clk][idx] << 24;
261
262 pci_write_config_dword(dev, drive_pci, t1);
263 }
264
265 static void sis_program_timings(ide_drive_t *drive, const u8 mode)
266 {
267 if (chipset_family < ATA_100) /* ATA_16/33/66/100a */
268 sis_ata16_program_timings(drive, mode);
269 else if (chipset_family < ATA_133) /* ATA_100/133a */
270 sis_ata100_program_timings(drive, mode);
271 else /* ATA_133 */
272 sis_ata133_program_timings(drive, mode);
273 }
274
275 static void config_drive_art_rwp (ide_drive_t *drive)
276 {
277 ide_hwif_t *hwif = HWIF(drive);
278 struct pci_dev *dev = to_pci_dev(hwif->dev);
279 u8 reg4bh = 0;
280 u8 rw_prefetch = 0;
281
282 pci_read_config_byte(dev, 0x4b, &reg4bh);
283
284 if (drive->media == ide_disk)
285 rw_prefetch = 0x11 << drive->dn;
286
287 if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch)
288 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
289 }
290
291 static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
292 {
293 config_drive_art_rwp(drive);
294 sis_program_timings(drive, XFER_PIO_0 + pio);
295 }
296
297 static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
298 {
299 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
300 u32 regdw = 0;
301 u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
302
303 pci_read_config_dword(dev, drive_pci, &regdw);
304
305 regdw |= 0x04;
306 regdw &= 0xfffff00f;
307 /* check if ATA133 enable */
308 clk = (regdw & 0x08) ? ATA_133 : ATA_100;
309 idx = mode - XFER_UDMA_0;
310 regdw |= cycle_time_value[clk][idx] << 4;
311 regdw |= cvs_time_value[clk][idx] << 8;
312
313 pci_write_config_dword(dev, drive_pci, regdw);
314 }
315
316 static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
317 {
318 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
319 u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;
320
321 pci_read_config_byte(dev, drive_pci + 1, &reg);
322
323 /* force the UDMA bit on if we want to use UDMA */
324 reg |= 0x80;
325 /* clean reg cycle time bits */
326 reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
327 /* set reg cycle time bits */
328 reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];
329
330 pci_write_config_byte(dev, drive_pci + 1, reg);
331 }
332
333 static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
334 {
335 if (chipset_family >= ATA_133) /* ATA_133 */
336 sis_ata133_program_udma_timings(drive, mode);
337 else /* ATA_33/66/100a/100/133a */
338 sis_ata33_program_udma_timings(drive, mode);
339 }
340
341 static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
342 {
343 if (speed >= XFER_UDMA_0)
344 sis_program_udma_timings(drive, speed);
345 else
346 sis_program_timings(drive, speed);
347 }
348
349 static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
350 {
351 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
352 u32 regdw = 0;
353 u8 drive_pci = sis_ata133_get_base(drive);
354
355 pci_read_config_dword(dev, drive_pci, &regdw);
356
357 /* if ATA133 disable, we should not set speed above UDMA5 */
358 return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5;
359 }
360
361 /* Chip detection and general config */
362 static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name)
363 {
364 struct pci_dev *host;
365 int i = 0;
366
367 chipset_family = 0;
368
369 for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
370
371 host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
372
373 if (!host)
374 continue;
375
376 chipset_family = SiSHostChipInfo[i].chipset_family;
377
378 /* Special case for SiS630 : 630S/ET is ATA_100a */
379 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
380 if (host->revision >= 0x30)
381 chipset_family = ATA_100a;
382 }
383 pci_dev_put(host);
384
385 printk(KERN_INFO "SIS5513: %s %s controller\n",
386 SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
387 }
388
389 if (!chipset_family) { /* Belongs to pci-quirks */
390
391 u32 idemisc;
392 u16 trueid;
393
394 /* Disable ID masking and register remapping */
395 pci_read_config_dword(dev, 0x54, &idemisc);
396 pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
397 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
398 pci_write_config_dword(dev, 0x54, idemisc);
399
400 if (trueid == 0x5518) {
401 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
402 chipset_family = ATA_133;
403
404 /* Check for 5513 compability mapping
405 * We must use this, else the port enabled code will fail,
406 * as it expects the enablebits at 0x4a.
407 */
408 if ((idemisc & 0x40000000) == 0) {
409 pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
410 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
411 }
412 }
413 }
414
415 if (!chipset_family) { /* Belongs to pci-quirks */
416
417 struct pci_dev *lpc_bridge;
418 u16 trueid;
419 u8 prefctl;
420 u8 idecfg;
421
422 pci_read_config_byte(dev, 0x4a, &idecfg);
423 pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
424 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
425 pci_write_config_byte(dev, 0x4a, idecfg);
426
427 if (trueid == 0x5517) { /* SiS 961/961B */
428
429 lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
430 pci_read_config_byte(dev, 0x49, &prefctl);
431 pci_dev_put(lpc_bridge);
432
433 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
434 printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
435 chipset_family = ATA_133a;
436 } else {
437 printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
438 chipset_family = ATA_100;
439 }
440 }
441 }
442
443 if (!chipset_family)
444 return -1;
445
446 /* Make general config ops here
447 1/ tell IDE channels to operate in Compatibility mode only
448 2/ tell old chips to allow per drive IDE timings */
449
450 {
451 u8 reg;
452 u16 regw;
453
454 switch(chipset_family) {
455 case ATA_133:
456 /* SiS962 operation mode */
457 pci_read_config_word(dev, 0x50, &regw);
458 if (regw & 0x08)
459 pci_write_config_word(dev, 0x50, regw&0xfff7);
460 pci_read_config_word(dev, 0x52, &regw);
461 if (regw & 0x08)
462 pci_write_config_word(dev, 0x52, regw&0xfff7);
463 break;
464 case ATA_133a:
465 case ATA_100:
466 /* Fixup latency */
467 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
468 /* Set compatibility bit */
469 pci_read_config_byte(dev, 0x49, &reg);
470 if (!(reg & 0x01)) {
471 pci_write_config_byte(dev, 0x49, reg|0x01);
472 }
473 break;
474 case ATA_100a:
475 case ATA_66:
476 /* Fixup latency */
477 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
478
479 /* On ATA_66 chips the bit was elsewhere */
480 pci_read_config_byte(dev, 0x52, &reg);
481 if (!(reg & 0x04)) {
482 pci_write_config_byte(dev, 0x52, reg|0x04);
483 }
484 break;
485 case ATA_33:
486 /* On ATA_33 we didn't have a single bit to set */
487 pci_read_config_byte(dev, 0x09, &reg);
488 if ((reg & 0x0f) != 0x00) {
489 pci_write_config_byte(dev, 0x09, reg&0xf0);
490 }
491 case ATA_16:
492 /* force per drive recovery and active timings
493 needed on ATA_33 and below chips */
494 pci_read_config_byte(dev, 0x52, &reg);
495 if (!(reg & 0x08)) {
496 pci_write_config_byte(dev, 0x52, reg|0x08);
497 }
498 break;
499 }
500 }
501
502 return 0;
503 }
504
505 struct sis_laptop {
506 u16 device;
507 u16 subvendor;
508 u16 subdevice;
509 };
510
511 static const struct sis_laptop sis_laptop[] = {
512 /* devid, subvendor, subdev */
513 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
514 { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */
515 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
516 /* end marker */
517 { 0, }
518 };
519
520 static u8 __devinit ata66_sis5513(ide_hwif_t *hwif)
521 {
522 struct pci_dev *pdev = to_pci_dev(hwif->dev);
523 const struct sis_laptop *lap = &sis_laptop[0];
524 u8 ata66 = 0;
525
526 while (lap->device) {
527 if (lap->device == pdev->device &&
528 lap->subvendor == pdev->subsystem_vendor &&
529 lap->subdevice == pdev->subsystem_device)
530 return ATA_CBL_PATA40_SHORT;
531 lap++;
532 }
533
534 if (chipset_family >= ATA_133) {
535 u16 regw = 0;
536 u16 reg_addr = hwif->channel ? 0x52: 0x50;
537 pci_read_config_word(pdev, reg_addr, &regw);
538 ata66 = (regw & 0x8000) ? 0 : 1;
539 } else if (chipset_family >= ATA_66) {
540 u8 reg48h = 0;
541 u8 mask = hwif->channel ? 0x20 : 0x10;
542 pci_read_config_byte(pdev, 0x48, &reg48h);
543 ata66 = (reg48h & mask) ? 0 : 1;
544 }
545
546 return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
547 }
548
549 static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
550 {
551 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
552
553 hwif->set_pio_mode = &sis_set_pio_mode;
554 hwif->set_dma_mode = &sis_set_dma_mode;
555
556 if (chipset_family >= ATA_133)
557 hwif->udma_filter = sis5513_ata133_udma_filter;
558
559 hwif->cable_detect = ata66_sis5513;
560
561 if (hwif->dma_base == 0)
562 return;
563
564 hwif->ultra_mask = udma_rates[chipset_family];
565 }
566
567 static const struct ide_port_info sis5513_chipset __devinitdata = {
568 .name = "SIS5513",
569 .init_chipset = init_chipset_sis5513,
570 .init_hwif = init_hwif_sis5513,
571 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
572 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA |
573 IDE_HFLAG_BOOTABLE,
574 .pio_mask = ATA_PIO4,
575 .mwdma_mask = ATA_MWDMA2,
576 };
577
578 static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
579 {
580 return ide_setup_pci_device(dev, &sis5513_chipset);
581 }
582
583 static const struct pci_device_id sis5513_pci_tbl[] = {
584 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 },
585 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 },
586 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 },
587 { 0, },
588 };
589 MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
590
591 static struct pci_driver driver = {
592 .name = "SIS_IDE",
593 .id_table = sis5513_pci_tbl,
594 .probe = sis5513_init_one,
595 };
596
597 static int __init sis5513_ide_init(void)
598 {
599 return ide_pci_register_driver(&driver);
600 }
601
602 module_init(sis5513_ide_init);
603
604 MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
605 MODULE_DESCRIPTION("PCI driver module for SIS IDE");
606 MODULE_LICENSE("GPL");
607
608 /*
609 * TODO:
610 * - CLEANUP
611 * - Use drivers/ide/ide-timing.h !
612 * - More checks in the config registers (force values instead of
613 * relying on the BIOS setting them correctly).
614 * - Further optimisations ?
615 * . for example ATA66+ regs 0x48 & 0x4A
616 */
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