?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / ide / pci / pdc202xx_new.c
blob1c8cb7797a4aea2a6800c22da7ab251fe9cb8163
1 /*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2007 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/hdreg.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/ide.h>
26
27 #include <asm/io.h>
28
29 #ifdef CONFIG_PPC_PMAC
30 #include <asm/prom.h>
31 #include <asm/pci-bridge.h>
32 #endif
33
34 #undef DEBUG
35
36 #ifdef DEBUG
37 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
38 #else
39 #define DBG(fmt, args...)
40 #endif
41
42 static const char *pdc_quirk_drives[] = {
43 "QUANTUM FIREBALLlct08 08",
44 "QUANTUM FIREBALLP KA6.4",
45 "QUANTUM FIREBALLP KA9.1",
46 "QUANTUM FIREBALLP LM20.4",
47 "QUANTUM FIREBALLP KX13.6",
48 "QUANTUM FIREBALLP KX20.5",
49 "QUANTUM FIREBALLP KX27.3",
50 "QUANTUM FIREBALLP LM20.5",
51 NULL
52 };
53
54 static u8 max_dma_rate(struct pci_dev *pdev)
55 {
56 u8 mode;
57
58 switch(pdev->device) {
59 case PCI_DEVICE_ID_PROMISE_20277:
60 case PCI_DEVICE_ID_PROMISE_20276:
61 case PCI_DEVICE_ID_PROMISE_20275:
62 case PCI_DEVICE_ID_PROMISE_20271:
63 case PCI_DEVICE_ID_PROMISE_20269:
64 mode = 4;
65 break;
66 case PCI_DEVICE_ID_PROMISE_20270:
67 case PCI_DEVICE_ID_PROMISE_20268:
68 mode = 3;
69 break;
70 default:
71 return 0;
72 }
73
74 return mode;
75 }
76
77 /**
78 * get_indexed_reg - Get indexed register
79 * @hwif: for the port address
80 * @index: index of the indexed register
81 */
82 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
83 {
84 u8 value;
85
86 outb(index, hwif->dma_vendor1);
87 value = inb(hwif->dma_vendor3);
88
89 DBG("index[%02X] value[%02X]\n", index, value);
90 return value;
91 }
92
93 /**
94 * set_indexed_reg - Set indexed register
95 * @hwif: for the port address
96 * @index: index of the indexed register
97 */
98 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
99 {
100 outb(index, hwif->dma_vendor1);
101 outb(value, hwif->dma_vendor3);
102 DBG("index[%02X] value[%02X]\n", index, value);
103 }
104
105 /*
106 * ATA Timing Tables based on 133 MHz PLL output clock.
107 *
108 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
109 * the timing registers automatically when "set features" command is
110 * issued to the device. However, if the PLL output clock is 133 MHz,
111 * the following tables must be used.
112 */
113 static struct pio_timing {
114 u8 reg0c, reg0d, reg13;
115 } pio_timings [] = {
116 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
117 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
118 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
119 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
120 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
121 };
122
123 static struct mwdma_timing {
124 u8 reg0e, reg0f;
125 } mwdma_timings [] = {
126 { 0xdf, 0x5f }, /* MWDMA mode 0 */
127 { 0x6b, 0x27 }, /* MWDMA mode 1 */
128 { 0x69, 0x25 }, /* MWDMA mode 2 */
129 };
130
131 static struct udma_timing {
132 u8 reg10, reg11, reg12;
133 } udma_timings [] = {
134 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
135 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
136 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
137 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
138 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
139 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
140 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
141 };
142
143 static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
144 {
145 ide_hwif_t *hwif = HWIF(drive);
146 struct pci_dev *dev = to_pci_dev(hwif->dev);
147 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
148
149 /*
150 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
151 * IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
152 * automatically set the timing registers based on 100 MHz PLL output.
153 *
154 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
155 * chips, we must override the default register settings...
156 */
157 if (max_dma_rate(dev) == 4) {
158 u8 mode = speed & 0x07;
159
160 if (speed >= XFER_UDMA_0) {
161 set_indexed_reg(hwif, 0x10 + adj,
162 udma_timings[mode].reg10);
163 set_indexed_reg(hwif, 0x11 + adj,
164 udma_timings[mode].reg11);
165 set_indexed_reg(hwif, 0x12 + adj,
166 udma_timings[mode].reg12);
167 } else {
168 set_indexed_reg(hwif, 0x0e + adj,
169 mwdma_timings[mode].reg0e);
170 set_indexed_reg(hwif, 0x0f + adj,
171 mwdma_timings[mode].reg0f);
172 }
173 } else if (speed == XFER_UDMA_2) {
174 /* Set tHOLD bit to 0 if using UDMA mode 2 */
175 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
176
177 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
178 }
179 }
180
181 static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
182 {
183 ide_hwif_t *hwif = drive->hwif;
184 struct pci_dev *dev = to_pci_dev(hwif->dev);
185 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
186
187 if (max_dma_rate(dev) == 4) {
188 set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
189 set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
190 set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
191 }
192 }
193
194 static u8 __devinit pdcnew_cable_detect(ide_hwif_t *hwif)
195 {
196 if (get_indexed_reg(hwif, 0x0b) & 0x04)
197 return ATA_CBL_PATA40;
198 else
199 return ATA_CBL_PATA80;
200 }
201
202 static void pdcnew_quirkproc(ide_drive_t *drive)
203 {
204 const char **list, *model = drive->id->model;
205
206 for (list = pdc_quirk_drives; *list != NULL; list++)
207 if (strstr(model, *list) != NULL) {
208 drive->quirk_list = 2;
209 return;
210 }
211
212 drive->quirk_list = 0;
213 }
214
215 static void pdcnew_reset(ide_drive_t *drive)
216 {
217 /*
218 * Deleted this because it is redundant from the caller.
219 */
220 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
221 HWIF(drive)->channel ? "Secondary" : "Primary");
222 }
223
224 /**
225 * read_counter - Read the byte count registers
226 * @dma_base: for the port address
227 */
228 static long __devinit read_counter(u32 dma_base)
229 {
230 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
231 u8 cnt0, cnt1, cnt2, cnt3;
232 long count = 0, last;
233 int retry = 3;
234
235 do {
236 last = count;
237
238 /* Read the current count */
239 outb(0x20, pri_dma_base + 0x01);
240 cnt0 = inb(pri_dma_base + 0x03);
241 outb(0x21, pri_dma_base + 0x01);
242 cnt1 = inb(pri_dma_base + 0x03);
243 outb(0x20, sec_dma_base + 0x01);
244 cnt2 = inb(sec_dma_base + 0x03);
245 outb(0x21, sec_dma_base + 0x01);
246 cnt3 = inb(sec_dma_base + 0x03);
247
248 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
249
250 /*
251 * The 30-bit decrementing counter is read in 4 pieces.
252 * Incorrect value may be read when the most significant bytes
253 * are changing...
254 */
255 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
256
257 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
258 cnt0, cnt1, cnt2, cnt3);
259
260 return count;
261 }
262
263 /**
264 * detect_pll_input_clock - Detect the PLL input clock in Hz.
265 * @dma_base: for the port address
266 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
267 */
268 static long __devinit detect_pll_input_clock(unsigned long dma_base)
269 {
270 struct timeval start_time, end_time;
271 long start_count, end_count;
272 long pll_input, usec_elapsed;
273 u8 scr1;
274
275 start_count = read_counter(dma_base);
276 do_gettimeofday(&start_time);
277
278 /* Start the test mode */
279 outb(0x01, dma_base + 0x01);
280 scr1 = inb(dma_base + 0x03);
281 DBG("scr1[%02X]\n", scr1);
282 outb(scr1 | 0x40, dma_base + 0x03);
283
284 /* Let the counter run for 10 ms. */
285 mdelay(10);
286
287 end_count = read_counter(dma_base);
288 do_gettimeofday(&end_time);
289
290 /* Stop the test mode */
291 outb(0x01, dma_base + 0x01);
292 scr1 = inb(dma_base + 0x03);
293 DBG("scr1[%02X]\n", scr1);
294 outb(scr1 & ~0x40, dma_base + 0x03);
295
296 /*
297 * Calculate the input clock in Hz
298 * (the clock counter is 30 bit wide and counts down)
299 */
300 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
301 (end_time.tv_usec - start_time.tv_usec);
302 pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
303 (10000000 / usec_elapsed);
304
305 DBG("start[%ld] end[%ld]\n", start_count, end_count);
306
307 return pll_input;
308 }
309
310 #ifdef CONFIG_PPC_PMAC
311 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
312 {
313 struct device_node *np = pci_device_to_OF_node(pdev);
314 u8 conf;
315
316 if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
317 return;
318
319 if (pdev->revision >= 0x03) {
320 /* Setup chip magic config stuff (from darwin) */
321 pci_read_config_byte (pdev, 0x40, &conf);
322 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
323 }
324 }
325 #endif /* CONFIG_PPC_PMAC */
326
327 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
328 {
329 unsigned long dma_base = pci_resource_start(dev, 4);
330 unsigned long sec_dma_base = dma_base + 0x08;
331 long pll_input, pll_output, ratio;
332 int f, r;
333 u8 pll_ctl0, pll_ctl1;
334
335 if (dma_base == 0)
336 return -EFAULT;
337
338 #ifdef CONFIG_PPC_PMAC
339 apple_kiwi_init(dev);
340 #endif
341
342 /* Calculate the required PLL output frequency */
343 switch(max_dma_rate(dev)) {
344 case 4: /* it's 133 MHz for Ultra133 chips */
345 pll_output = 133333333;
346 break;
347 case 3: /* and 100 MHz for Ultra100 chips */
348 default:
349 pll_output = 100000000;
350 break;
351 }
352
353 /*
354 * Detect PLL input clock.
355 * On some systems, where PCI bus is running at non-standard clock rate
356 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
357 * PDC20268 and newer chips employ PLL circuit to help correct timing
358 * registers setting.
359 */
360 pll_input = detect_pll_input_clock(dma_base);
361 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
362
363 /* Sanity check */
364 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
365 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
366 name, pll_input);
367 goto out;
368 }
369
370 #ifdef DEBUG
371 DBG("pll_output is %ld Hz\n", pll_output);
372
373 /* Show the current clock value of PLL control register
374 * (maybe already configured by the BIOS)
375 */
376 outb(0x02, sec_dma_base + 0x01);
377 pll_ctl0 = inb(sec_dma_base + 0x03);
378 outb(0x03, sec_dma_base + 0x01);
379 pll_ctl1 = inb(sec_dma_base + 0x03);
380
381 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
382 #endif
383
384 /*
385 * Calculate the ratio of F, R and NO
386 * POUT = (F + 2) / (( R + 2) * NO)
387 */
388 ratio = pll_output / (pll_input / 1000);
389 if (ratio < 8600L) { /* 8.6x */
390 /* Using NO = 0x01, R = 0x0d */
391 r = 0x0d;
392 } else if (ratio < 12900L) { /* 12.9x */
393 /* Using NO = 0x01, R = 0x08 */
394 r = 0x08;
395 } else if (ratio < 16100L) { /* 16.1x */
396 /* Using NO = 0x01, R = 0x06 */
397 r = 0x06;
398 } else if (ratio < 64000L) { /* 64x */
399 r = 0x00;
400 } else {
401 /* Invalid ratio */
402 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
403 goto out;
404 }
405
406 f = (ratio * (r + 2)) / 1000 - 2;
407
408 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
409
410 if (unlikely(f < 0 || f > 127)) {
411 /* Invalid F */
412 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
413 goto out;
414 }
415
416 pll_ctl0 = (u8) f;
417 pll_ctl1 = (u8) r;
418
419 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
420
421 outb(0x02, sec_dma_base + 0x01);
422 outb(pll_ctl0, sec_dma_base + 0x03);
423 outb(0x03, sec_dma_base + 0x01);
424 outb(pll_ctl1, sec_dma_base + 0x03);
425
426 /* Wait the PLL circuit to be stable */
427 mdelay(30);
428
429 #ifdef DEBUG
430 /*
431 * Show the current clock value of PLL control register
432 */
433 outb(0x02, sec_dma_base + 0x01);
434 pll_ctl0 = inb(sec_dma_base + 0x03);
435 outb(0x03, sec_dma_base + 0x01);
436 pll_ctl1 = inb(sec_dma_base + 0x03);
437
438 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
439 #endif
440
441 out:
442 return dev->irq;
443 }
444
445 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
446 {
447 hwif->set_pio_mode = &pdcnew_set_pio_mode;
448 hwif->set_dma_mode = &pdcnew_set_dma_mode;
449
450 hwif->quirkproc = &pdcnew_quirkproc;
451 hwif->resetproc = &pdcnew_reset;
452
453 hwif->cable_detect = pdcnew_cable_detect;
454 }
455
456 static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
457 {
458 struct pci_dev *dev2;
459
460 dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
461 PCI_FUNC(dev->devfn)));
462
463 if (dev2 &&
464 dev2->vendor == dev->vendor &&
465 dev2->device == dev->device) {
466
467 if (dev2->irq != dev->irq) {
468 dev2->irq = dev->irq;
469 printk(KERN_INFO "PDC20270: PCI config space "
470 "interrupt fixed\n");
471 }
472
473 return dev2;
474 }
475
476 return NULL;
477 }
478
479 #define DECLARE_PDCNEW_DEV(name_str, udma) \
480 { \
481 .name = name_str, \
482 .init_chipset = init_chipset_pdcnew, \
483 .init_hwif = init_hwif_pdc202new, \
484 .host_flags = IDE_HFLAG_POST_SET_MODE | \
485 IDE_HFLAG_ERROR_STOPS_FIFO | \
486 IDE_HFLAG_OFF_BOARD, \
487 .pio_mask = ATA_PIO4, \
488 .mwdma_mask = ATA_MWDMA2, \
489 .udma_mask = udma, \
490 }
491
492 static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
493 /* 0 */ DECLARE_PDCNEW_DEV("PDC20268", ATA_UDMA5),
494 /* 1 */ DECLARE_PDCNEW_DEV("PDC20269", ATA_UDMA6),
495 /* 2 */ DECLARE_PDCNEW_DEV("PDC20270", ATA_UDMA5),
496 /* 3 */ DECLARE_PDCNEW_DEV("PDC20271", ATA_UDMA6),
497 /* 4 */ DECLARE_PDCNEW_DEV("PDC20275", ATA_UDMA6),
498 /* 5 */ DECLARE_PDCNEW_DEV("PDC20276", ATA_UDMA6),
499 /* 6 */ DECLARE_PDCNEW_DEV("PDC20277", ATA_UDMA6),
500 };
501
502 /**
503 * pdc202new_init_one - called when a pdc202xx is found
504 * @dev: the pdc202new device
505 * @id: the matching pci id
506 *
507 * Called when the PCI registration layer (or the IDE initialization)
508 * finds a device matching our IDE device tables.
509 */
510
511 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
512 {
513 const struct ide_port_info *d;
514 struct pci_dev *bridge = dev->bus->self;
515 u8 idx = id->driver_data;
516
517 d = &pdcnew_chipsets[idx];
518
519 if (idx == 2 && bridge &&
520 bridge->vendor == PCI_VENDOR_ID_DEC &&
521 bridge->device == PCI_DEVICE_ID_DEC_21150) {
522 struct pci_dev *dev2;
523
524 if (PCI_SLOT(dev->devfn) & 2)
525 return -ENODEV;
526
527 dev2 = pdc20270_get_dev2(dev);
528
529 if (dev2) {
530 int ret = ide_setup_pci_devices(dev, dev2, d);
531 if (ret < 0)
532 pci_dev_put(dev2);
533 return ret;
534 }
535 }
536
537 if (idx == 5 && bridge &&
538 bridge->vendor == PCI_VENDOR_ID_INTEL &&
539 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
540 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
541 printk(KERN_INFO "PDC20276: attached to I2O RAID controller, "
542 "skipping\n");
543 return -ENODEV;
544 }
545
546 return ide_setup_pci_device(dev, d);
547 }
548
549 static const struct pci_device_id pdc202new_pci_tbl[] = {
550 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
551 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
552 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
553 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
554 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
555 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
556 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
557 { 0, },
558 };
559 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
560
561 static struct pci_driver driver = {
562 .name = "Promise_IDE",
563 .id_table = pdc202new_pci_tbl,
564 .probe = pdc202new_init_one,
565 };
566
567 static int __init pdc202new_ide_init(void)
568 {
569 return ide_pci_register_driver(&driver);
570 }
571
572 module_init(pdc202new_ide_init);
573
574 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
575 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
576 MODULE_LICENSE("GPL");
mah project overlay