drivers/ide/pci/cy82c693.c

   1 /*
   2  *  Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
   3  *  Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
   4  *
   5  * CYPRESS CY82C693 chipset IDE controller
   6  *
   7  * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
   8  * Writing the driver was quite simple, since most of the job is
   9  * done by the generic pci-ide support.
  10  * The hard part was finding the CY82C693's datasheet on Cypress's
  11  * web page :-(. But Altavista solved this problem :-).
  12  *
  13  *
  14  * Notes:
  15  * - I recently got a 16.8G IBM DTTA, so I was able to test it with
  16  *   a large and fast disk - the results look great, so I'd say the
  17  *   driver is working fine :-)
  18  *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
  19  * - this is my first linux driver, so there's probably a lot  of room
  20  *   for optimizations and bug fixing, so feel free to do it.
  21  * - use idebus=xx parameter to set PCI bus speed - needed to calc
  22  *   timings for PIO modes (default will be 40)
  23  * - if using PIO mode it's a good idea to set the PIO mode and
  24  *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
  25  * - I had some problems with my IBM DHEA with PIO modes < 2
  26  *   (lost interrupts) ?????
  27  * - first tests with DMA look okay, they seem to work, but there is a
  28  *   problem with sound - the BusMaster IDE TimeOut should fixed this
  29  *
  30  * Ancient History:
  31  * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
  32  * ASK@1999-01-23: v0.33 made a few minor code clean ups
  33  *                       removed DMA clock speed setting by default
  34  *                       added boot message
  35  * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
  36  *                       added support to set DMA Controller Clock Speed
  37  * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
  38  *                       on some drives.
  39  * ASK@1998-10-29: v0.3 added support to set DMA modes
  40  * ASK@1998-10-28: v0.2 added support to set PIO modes
  41  * ASK@1998-10-27: v0.1 first version - chipset detection
  42  *
  43  */
  44
  45 #include <linux/module.h>
  46 #include <linux/types.h>
  47 #include <linux/pci.h>
  48 #include <linux/ide.h>
  49 #include <linux/init.h>
  50
  51 #include <asm/io.h>
  52
  53 /* the current version */
  54 #define CY82_VERSION    "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
  55
  56 /*
  57  *      The following are used to debug the driver.
  58  */
  59 #define CY82C693_DEBUG_LOGS     0
  60 #define CY82C693_DEBUG_INFO     0
  61
  62 /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
  63 #undef CY82C693_SETDMA_CLOCK
  64
  65 /*
  66  *      NOTE: the value for busmaster timeout is tricky and I got it by
  67  *      trial and error!  By using a to low value will cause DMA timeouts
  68  *      and drop IDE performance, and by using a to high value will cause
  69  *      audio playback to scatter.
  70  *      If you know a better value or how to calc it, please let me know.
  71  */
  72
  73 /* twice the value written in cy82c693ub datasheet */
  74 #define BUSMASTER_TIMEOUT       0x50
  75 /*
  76  * the value above was tested on my machine and it seems to work okay
  77  */
  78
  79 /* here are the offset definitions for the registers */
  80 #define CY82_IDE_CMDREG         0x04
  81 #define CY82_IDE_ADDRSETUP      0x48
  82 #define CY82_IDE_MASTER_IOR     0x4C
  83 #define CY82_IDE_MASTER_IOW     0x4D
  84 #define CY82_IDE_SLAVE_IOR      0x4E
  85 #define CY82_IDE_SLAVE_IOW      0x4F
  86 #define CY82_IDE_MASTER_8BIT    0x50
  87 #define CY82_IDE_SLAVE_8BIT     0x51
  88
  89 #define CY82_INDEX_PORT         0x22
  90 #define CY82_DATA_PORT          0x23
  91
  92 #define CY82_INDEX_CTRLREG1     0x01
  93 #define CY82_INDEX_CHANNEL0     0x30
  94 #define CY82_INDEX_CHANNEL1     0x31
  95 #define CY82_INDEX_TIMEOUT      0x32
  96
  97 /* the min and max PCI bus speed in MHz - from datasheet */
  98 #define CY82C963_MIN_BUS_SPEED  25
  99 #define CY82C963_MAX_BUS_SPEED  33
 100
 101 /* the struct for the PIO mode timings */
 102 typedef struct pio_clocks_s {
 103         u8      address_time;   /* Address setup (clocks) */
 104         u8      time_16r;       /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
 105         u8      time_16w;       /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
 106         u8      time_8;         /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
 107 } pio_clocks_t;
 108
 109 /*
 110  * calc clocks using bus_speed
 111  * returns (rounded up) time in bus clocks for time in ns
 112  */
 113 static int calc_clk (int time, int bus_speed)
 114 {
 115         int clocks;
 116
 117         clocks = (time*bus_speed+999)/1000 -1;
 118
 119         if (clocks < 0)
 120                 clocks = 0;
 121
 122         if (clocks > 0x0F)
 123                 clocks = 0x0F;
 124
 125         return clocks;
 126 }
 127
 128 /*
 129  * compute the values for the clock registers for PIO
 130  * mode and pci_clk [MHz] speed
 131  *
 132  * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 133  *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 134  *
 135  */
 136 static void compute_clocks (u8 pio, pio_clocks_t *p_pclk)
 137 {
 138         int clk1, clk2;
 139         int bus_speed = system_bus_clock();     /* get speed of PCI bus */
 140
 141         /* we don't check against CY82C693's min and max speed,
 142          * so you can play with the idebus=xx parameter
 143          */
 144
 145         /* let's calc the address setup time clocks */
 146         p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
 147
 148         /* let's calc the active and recovery time clocks */
 149         clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
 150
 151         /* calc recovery timing */
 152         clk2 =  ide_pio_timings[pio].cycle_time -
 153                 ide_pio_timings[pio].active_time -
 154                 ide_pio_timings[pio].setup_time;
 155
 156         clk2 = calc_clk(clk2, bus_speed);
 157
 158         clk1 = (clk1<<4)|clk2;  /* combine active and recovery clocks */
 159
 160         /* note: we use the same values for 16bit IOR and IOW
 161          *      those are all the same, since I don't have other
 162          *      timings than those from ide-lib.c
 163          */
 164
 165         p_pclk->time_16r = (u8)clk1;
 166         p_pclk->time_16w = (u8)clk1;
 167
 168         /* what are good values for 8bit ?? */
 169         p_pclk->time_8 = (u8)clk1;
 170 }
 171
 172 /*
 173  * set DMA mode a specific channel for CY82C693
 174  */
 175
 176 static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
 177 {
 178         ide_hwif_t *hwif = drive->hwif;
 179         u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
 180
 181         index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
 182
 183 #if CY82C693_DEBUG_LOGS
 184         /* for debug let's show the previous values */
 185
 186         outb(index, CY82_INDEX_PORT);
 187         data = inb(CY82_DATA_PORT);
 188
 189         printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
 190                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 191                 (data&0x3), ((data>>2)&1));
 192 #endif /* CY82C693_DEBUG_LOGS */
 193
 194         data = (mode & 3) | (single << 2);
 195
 196         outb(index, CY82_INDEX_PORT);
 197         outb(data, CY82_DATA_PORT);
 198
 199 #if CY82C693_DEBUG_INFO
 200         printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
 201                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 202                 mode & 3, single);
 203 #endif /* CY82C693_DEBUG_INFO */
 204
 205         /*
 206          * note: below we set the value for Bus Master IDE TimeOut Register
 207          * I'm not absolutly sure what this does, but it solved my problem
 208          * with IDE DMA and sound, so I now can play sound and work with
 209          * my IDE driver at the same time :-)
 210          *
 211          * If you know the correct (best) value for this register please
 212          * let me know - ASK
 213          */
 214
 215         data = BUSMASTER_TIMEOUT;
 216         outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
 217         outb(data, CY82_DATA_PORT);
 218
 219 #if CY82C693_DEBUG_INFO
 220         printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
 221                 drive->name, data);
 222 #endif /* CY82C693_DEBUG_INFO */
 223 }
 224
 225 static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
 226 {
 227         ide_hwif_t *hwif = HWIF(drive);
 228         struct pci_dev *dev = to_pci_dev(hwif->dev);
 229         pio_clocks_t pclk;
 230         unsigned int addrCtrl;
 231
 232         /* select primary or secondary channel */
 233         if (hwif->index > 0) {  /* drive is on the secondary channel */
 234                 dev = pci_get_slot(dev->bus, dev->devfn+1);
 235                 if (!dev) {
 236                         printk(KERN_ERR "%s: tune_drive: "
 237                                 "Cannot find secondary interface!\n",
 238                                 drive->name);
 239                         return;
 240                 }
 241         }
 242
 243 #if CY82C693_DEBUG_LOGS
 244         /* for debug let's show the register values */
 245
 246         if (drive->select.b.unit == 0) {
 247                 /*
 248                  * get master drive registers
 249                  * address setup control register
 250                  * is 32 bit !!!
 251                  */
 252                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 253                 addrCtrl &= 0x0F;
 254
 255                 /* now let's get the remaining registers */
 256                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
 257                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
 258                 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
 259         } else {
 260                 /*
 261                  * set slave drive registers
 262                  * address setup control register
 263                  * is 32 bit !!!
 264                  */
 265                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 266
 267                 addrCtrl &= 0xF0;
 268                 addrCtrl >>= 4;
 269
 270                 /* now let's get the remaining registers */
 271                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
 272                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
 273                 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
 274         }
 275
 276         printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
 277                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 278                 drive->name, hwif->channel, drive->select.b.unit,
 279                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 280 #endif /* CY82C693_DEBUG_LOGS */
 281
 282         /* let's calc the values for this PIO mode */
 283         compute_clocks(pio, &pclk);
 284
 285         /* now let's write  the clocks registers */
 286         if (drive->select.b.unit == 0) {
 287                 /*
 288                  * set master drive
 289                  * address setup control register
 290                  * is 32 bit !!!
 291                  */
 292                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 293
 294                 addrCtrl &= (~0xF);
 295                 addrCtrl |= (unsigned int)pclk.address_time;
 296                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 297
 298                 /* now let's set the remaining registers */
 299                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
 300                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
 301                 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
 302
 303                 addrCtrl &= 0xF;
 304         } else {
 305                 /*
 306                  * set slave drive
 307                  * address setup control register
 308                  * is 32 bit !!!
 309                  */
 310                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 311
 312                 addrCtrl &= (~0xF0);
 313                 addrCtrl |= ((unsigned int)pclk.address_time<<4);
 314                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 315
 316                 /* now let's set the remaining registers */
 317                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
 318                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
 319                 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
 320
 321                 addrCtrl >>= 4;
 322                 addrCtrl &= 0xF;
 323         }
 324
 325 #if CY82C693_DEBUG_INFO
 326         printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
 327                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 328                 drive->name, hwif->channel, drive->select.b.unit,
 329                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 330 #endif /* CY82C693_DEBUG_INFO */
 331 }
 332
 333 /*
 334  * this function is called during init and is used to setup the cy82c693 chip
 335  */
 336 static unsigned int __devinit init_chipset_cy82c693(struct pci_dev *dev, const char *name)
 337 {
 338         if (PCI_FUNC(dev->devfn) != 1)
 339                 return 0;
 340
 341 #ifdef CY82C693_SETDMA_CLOCK
 342         u8 data = 0;
 343 #endif /* CY82C693_SETDMA_CLOCK */
 344
 345         /* write info about this verion of the driver */
 346         printk(KERN_INFO CY82_VERSION "\n");
 347
 348 #ifdef CY82C693_SETDMA_CLOCK
 349        /* okay let's set the DMA clock speed */
 350
 351         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 352         data = inb(CY82_DATA_PORT);
 353
 354 #if CY82C693_DEBUG_INFO
 355         printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
 356                 name, data);
 357 #endif /* CY82C693_DEBUG_INFO */
 358
 359         /*
 360          * for some reason sometimes the DMA controller
 361          * speed is set to ATCLK/2 ???? - we fix this here
 362          *
 363          * note: i don't know what causes this strange behaviour,
 364          *       but even changing the dma speed doesn't solve it :-(
 365          *       the ide performance is still only half the normal speed
 366          *
 367          *       if anybody knows what goes wrong with my machine, please
 368          *       let me know - ASK
 369          */
 370
 371         data |= 0x03;
 372
 373         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 374         outb(data, CY82_DATA_PORT);
 375
 376 #if CY82C693_DEBUG_INFO
 377         printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
 378                 name, data);
 379 #endif /* CY82C693_DEBUG_INFO */
 380
 381 #endif /* CY82C693_SETDMA_CLOCK */
 382         return 0;
 383 }
 384
 385 /*
 386  * the init function - called for each ide channel once
 387  */
 388 static void __devinit init_hwif_cy82c693(ide_hwif_t *hwif)
 389 {
 390         hwif->set_pio_mode = &cy82c693_set_pio_mode;
 391         hwif->set_dma_mode = &cy82c693_set_dma_mode;
 392 }
 393
 394 static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
 395 {
 396         static ide_hwif_t *primary;
 397         struct pci_dev *dev = to_pci_dev(hwif->dev);
 398
 399         if (PCI_FUNC(dev->devfn) == 1)
 400                 primary = hwif;
 401         else {
 402                 hwif->mate = primary;
 403                 hwif->channel = 1;
 404         }
 405 }
 406
 407 static const struct ide_port_info cy82c693_chipset __devinitdata = {
 408         .name           = "CY82C693",
 409         .init_chipset   = init_chipset_cy82c693,
 410         .init_iops      = init_iops_cy82c693,
 411         .init_hwif      = init_hwif_cy82c693,
 412         .chipset        = ide_cy82c693,
 413         .host_flags     = IDE_HFLAG_SINGLE | IDE_HFLAG_CY82C693 |
 414                           IDE_HFLAG_BOOTABLE,
 415         .pio_mask       = ATA_PIO4,
 416         .swdma_mask     = ATA_SWDMA2,
 417         .mwdma_mask     = ATA_MWDMA2,
 418 };
 419
 420 static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 421 {
 422         struct pci_dev *dev2;
 423         int ret = -ENODEV;
 424
 425         /* CY82C693 is more than only a IDE controller.
 426            Function 1 is primary IDE channel, function 2 - secondary. */
 427         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
 428             PCI_FUNC(dev->devfn) == 1) {
 429                 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
 430                 ret = ide_setup_pci_devices(dev, dev2, &cy82c693_chipset);
 431                 /* We leak pci refs here but thats ok - we can't be unloaded */
 432         }
 433         return ret;
 434 }
 435
 436 static const struct pci_device_id cy82c693_pci_tbl[] = {
 437         { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
 438         { 0, },
 439 };
 440 MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
 441
 442 static struct pci_driver driver = {
 443         .name           = "Cypress_IDE",
 444         .id_table       = cy82c693_pci_tbl,
 445         .probe          = cy82c693_init_one,
 446 };
 447
 448 static int __init cy82c693_ide_init(void)
 449 {
 450         return ide_pci_register_driver(&driver);
 451 }
 452
 453 module_init(cy82c693_ide_init);
 454
 455 MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
 456 MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
 457 MODULE_LICENSE("GPL");