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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / ide / pci / amd74xx.c
blob2ef890ce80976fa83e6667f80ade5689df0899dc
1 /*
2 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
3 * IDE driver for Linux.
4 *
5 * Copyright (c) 2000-2002 Vojtech Pavlik
6 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
7 *
8 * Based on the work of:
9 * Andre Hedrick
10 */
11
12 /*
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License version 2 as published by
15 * the Free Software Foundation.
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/ide.h>
23
24 #include "ide-timing.h"
25
26 enum {
27 AMD_IDE_CONFIG = 0x41,
28 AMD_CABLE_DETECT = 0x42,
29 AMD_DRIVE_TIMING = 0x48,
30 AMD_8BIT_TIMING = 0x4e,
31 AMD_ADDRESS_SETUP = 0x4c,
32 AMD_UDMA_TIMING = 0x50,
33 };
34
35 static unsigned int amd_80w;
36 static unsigned int amd_clock;
37
38 static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
39 static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
40
41 static inline u8 amd_offset(struct pci_dev *dev)
42 {
43 return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;
44 }
45
46 /*
47 * amd_set_speed() writes timing values to the chipset registers
48 */
49
50 static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
51 struct ide_timing *timing)
52 {
53 u8 t = 0, offset = amd_offset(dev);
54
55 pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);
56 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
57 pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);
58
59 pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),
60 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
61
62 pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),
63 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
64
65 switch (udma_mask) {
66 case ATA_UDMA2: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
67 case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
68 case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
69 case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
70 default: return;
71 }
72
73 pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t);
74 }
75
76 /*
77 * amd_set_drive() computes timing values and configures the chipset
78 * to a desired transfer mode. It also can be called by upper layers.
79 */
80
81 static void amd_set_drive(ide_drive_t *drive, const u8 speed)
82 {
83 ide_hwif_t *hwif = drive->hwif;
84 struct pci_dev *dev = to_pci_dev(hwif->dev);
85 ide_drive_t *peer = hwif->drives + (~drive->dn & 1);
86 struct ide_timing t, p;
87 int T, UT;
88 u8 udma_mask = hwif->ultra_mask;
89
90 T = 1000000000 / amd_clock;
91 UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);
92
93 ide_timing_compute(drive, speed, &t, T, UT);
94
95 if (peer->present) {
96 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
97 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
98 }
99
100 if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
101 if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
102
103 amd_set_speed(dev, drive->dn, udma_mask, &t);
104 }
105
106 /*
107 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
108 */
109
110 static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
111 {
112 amd_set_drive(drive, XFER_PIO_0 + pio);
113 }
114
115 static void __devinit amd7409_cable_detect(struct pci_dev *dev,
116 const char *name)
117 {
118 /* no host side cable detection */
119 amd_80w = 0x03;
120 }
121
122 static void __devinit amd7411_cable_detect(struct pci_dev *dev,
123 const char *name)
124 {
125 int i;
126 u32 u = 0;
127 u8 t = 0, offset = amd_offset(dev);
128
129 pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
130 pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
131 amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
132 for (i = 24; i >= 0; i -= 8)
133 if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
134 printk(KERN_WARNING "%s: BIOS didn't set cable bits "
135 "correctly. Enabling workaround.\n",
136 name);
137 amd_80w |= (1 << (1 - (i >> 4)));
138 }
139 }
140
141 /*
142 * The initialization callback. Initialize drive independent registers.
143 */
144
145 static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev,
146 const char *name)
147 {
148 u8 t = 0, offset = amd_offset(dev);
149
150 /*
151 * Check 80-wire cable presence.
152 */
153
154 if (dev->vendor == PCI_VENDOR_ID_AMD &&
155 dev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
156 ; /* no UDMA > 2 */
157 else if (dev->vendor == PCI_VENDOR_ID_AMD &&
158 dev->device == PCI_DEVICE_ID_AMD_VIPER_7409)
159 amd7409_cable_detect(dev, name);
160 else
161 amd7411_cable_detect(dev, name);
162
163 /*
164 * Take care of prefetch & postwrite.
165 */
166
167 pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t);
168 /*
169 * Check for broken FIFO support.
170 */
171 if (dev->vendor == PCI_VENDOR_ID_AMD &&
172 dev->vendor == PCI_DEVICE_ID_AMD_VIPER_7411)
173 t &= 0x0f;
174 else
175 t |= 0xf0;
176 pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t);
177
178 /*
179 * Determine the system bus clock.
180 */
181
182 amd_clock = system_bus_clock() * 1000;
183
184 switch (amd_clock) {
185 case 33000: amd_clock = 33333; break;
186 case 37000: amd_clock = 37500; break;
187 case 41000: amd_clock = 41666; break;
188 }
189
190 if (amd_clock < 20000 || amd_clock > 50000) {
191 printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
192 name, amd_clock);
193 amd_clock = 33333;
194 }
195
196 return dev->irq;
197 }
198
199 static u8 __devinit amd_cable_detect(ide_hwif_t *hwif)
200 {
201 if ((amd_80w >> hwif->channel) & 1)
202 return ATA_CBL_PATA80;
203 else
204 return ATA_CBL_PATA40;
205 }
206
207 static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
208 {
209 struct pci_dev *dev = to_pci_dev(hwif->dev);
210
211 if (hwif->irq == 0) /* 0 is bogus but will do for now */
212 hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
213
214 hwif->set_pio_mode = &amd_set_pio_mode;
215 hwif->set_dma_mode = &amd_set_drive;
216
217 hwif->cable_detect = amd_cable_detect;
218 }
219
220 #define IDE_HFLAGS_AMD \
221 (IDE_HFLAG_PIO_NO_BLACKLIST | \
222 IDE_HFLAG_PIO_NO_DOWNGRADE | \
223 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
224 IDE_HFLAG_POST_SET_MODE | \
225 IDE_HFLAG_IO_32BIT | \
226 IDE_HFLAG_UNMASK_IRQS | \
227 IDE_HFLAG_BOOTABLE)
228
229 #define DECLARE_AMD_DEV(name_str, swdma, udma) \
230 { \
231 .name = name_str, \
232 .init_chipset = init_chipset_amd74xx, \
233 .init_hwif = init_hwif_amd74xx, \
234 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
235 .host_flags = IDE_HFLAGS_AMD, \
236 .pio_mask = ATA_PIO5, \
237 .swdma_mask = swdma, \
238 .mwdma_mask = ATA_MWDMA2, \
239 .udma_mask = udma, \
240 }
241
242 #define DECLARE_NV_DEV(name_str, udma) \
243 { \
244 .name = name_str, \
245 .init_chipset = init_chipset_amd74xx, \
246 .init_hwif = init_hwif_amd74xx, \
247 .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
248 .host_flags = IDE_HFLAGS_AMD, \
249 .pio_mask = ATA_PIO5, \
250 .swdma_mask = ATA_SWDMA2, \
251 .mwdma_mask = ATA_MWDMA2, \
252 .udma_mask = udma, \
253 }
254
255 static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
256 /* 0 */ DECLARE_AMD_DEV("AMD7401", 0x00, ATA_UDMA2),
257 /* 1 */ DECLARE_AMD_DEV("AMD7409", ATA_SWDMA2, ATA_UDMA4),
258 /* 2 */ DECLARE_AMD_DEV("AMD7411", ATA_SWDMA2, ATA_UDMA5),
259 /* 3 */ DECLARE_AMD_DEV("AMD7441", ATA_SWDMA2, ATA_UDMA5),
260 /* 4 */ DECLARE_AMD_DEV("AMD8111", ATA_SWDMA2, ATA_UDMA6),
261
262 /* 5 */ DECLARE_NV_DEV("NFORCE", ATA_UDMA5),
263 /* 6 */ DECLARE_NV_DEV("NFORCE2", ATA_UDMA6),
264 /* 7 */ DECLARE_NV_DEV("NFORCE2-U400R", ATA_UDMA6),
265 /* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA", ATA_UDMA6),
266 /* 9 */ DECLARE_NV_DEV("NFORCE3-150", ATA_UDMA6),
267 /* 10 */ DECLARE_NV_DEV("NFORCE3-250", ATA_UDMA6),
268 /* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA", ATA_UDMA6),
269 /* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2", ATA_UDMA6),
270 /* 13 */ DECLARE_NV_DEV("NFORCE-CK804", ATA_UDMA6),
271 /* 14 */ DECLARE_NV_DEV("NFORCE-MCP04", ATA_UDMA6),
272 /* 15 */ DECLARE_NV_DEV("NFORCE-MCP51", ATA_UDMA6),
273 /* 16 */ DECLARE_NV_DEV("NFORCE-MCP55", ATA_UDMA6),
274 /* 17 */ DECLARE_NV_DEV("NFORCE-MCP61", ATA_UDMA6),
275 /* 18 */ DECLARE_NV_DEV("NFORCE-MCP65", ATA_UDMA6),
276 /* 19 */ DECLARE_NV_DEV("NFORCE-MCP67", ATA_UDMA6),
277 /* 20 */ DECLARE_NV_DEV("NFORCE-MCP73", ATA_UDMA6),
278 /* 21 */ DECLARE_NV_DEV("NFORCE-MCP77", ATA_UDMA6),
279
280 /* 22 */ DECLARE_AMD_DEV("AMD5536", ATA_SWDMA2, ATA_UDMA5),
281 };
282
283 static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
284 {
285 struct ide_port_info d;
286 u8 idx = id->driver_data;
287
288 d = amd74xx_chipsets[idx];
289
290 /*
291 * Check for bad SWDMA and incorrectly wired Serenade mainboards.
292 */
293 if (idx == 1) {
294 if (dev->revision <= 7)
295 d.swdma_mask = 0;
296 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
297 } else if (idx == 4) {
298 if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
299 dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
300 d.udma_mask = ATA_UDMA5;
301 }
302
303 printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
304 d.name, pci_name(dev), dev->revision,
305 amd_dma[fls(d.udma_mask) - 1]);
306
307 return ide_setup_pci_device(dev, &d);
308 }
309
310 static const struct pci_device_id amd74xx_pci_tbl[] = {
311 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
312 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
313 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 },
314 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 3 },
315 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 4 },
316 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 5 },
317 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 6 },
318 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 7 },
319 #ifdef CONFIG_BLK_DEV_IDE_SATA
320 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 8 },
321 #endif
322 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 9 },
323 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 10 },
324 #ifdef CONFIG_BLK_DEV_IDE_SATA
325 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 11 },
326 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 12 },
327 #endif
328 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 13 },
329 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 14 },
330 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 15 },
331 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 16 },
332 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 17 },
333 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 18 },
334 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 19 },
335 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 20 },
336 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 21 },
337 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 22 },
338 { 0, },
339 };
340 MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
341
342 static struct pci_driver driver = {
343 .name = "AMD_IDE",
344 .id_table = amd74xx_pci_tbl,
345 .probe = amd74xx_probe,
346 };
347
348 static int __init amd74xx_ide_init(void)
349 {
350 return ide_pci_register_driver(&driver);
351 }
352
353 module_init(amd74xx_ide_init);
354
355 MODULE_AUTHOR("Vojtech Pavlik");
356 MODULE_DESCRIPTION("AMD PCI IDE driver");
357 MODULE_LICENSE("GPL");
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