?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / i2c / busses / i2c-i801.c
blobb0f771fe43265df51f425593fc1f42ee47ba058e
1 /*
2 i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
3 monitoring
4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6 <mdsxyz123@yahoo.com>
7 Copyright (C) 2007 Jean Delvare <khali@linux-fr.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 /*
25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 Tolapai 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46
47 Features supported by this driver:
48 Software PEC no
49 Hardware PEC yes
50 Block buffer yes
51 Block process call transaction no
52 I2C block read transaction yes (doesn't use the block buffer)
53
54 See the file Documentation/i2c/busses/i2c-i801 for details.
55 */
56
57 /* Note: we assume there can only be one I801, with one SMBus interface */
58
59 #include <linux/module.h>
60 #include <linux/pci.h>
61 #include <linux/kernel.h>
62 #include <linux/stddef.h>
63 #include <linux/delay.h>
64 #include <linux/ioport.h>
65 #include <linux/init.h>
66 #include <linux/i2c.h>
67 #include <asm/io.h>
68
69 /* I801 SMBus address offsets */
70 #define SMBHSTSTS (0 + i801_smba)
71 #define SMBHSTCNT (2 + i801_smba)
72 #define SMBHSTCMD (3 + i801_smba)
73 #define SMBHSTADD (4 + i801_smba)
74 #define SMBHSTDAT0 (5 + i801_smba)
75 #define SMBHSTDAT1 (6 + i801_smba)
76 #define SMBBLKDAT (7 + i801_smba)
77 #define SMBPEC (8 + i801_smba) /* ICH3 and later */
78 #define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
79 #define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
80
81 /* PCI Address Constants */
82 #define SMBBAR 4
83 #define SMBHSTCFG 0x040
84
85 /* Host configuration bits for SMBHSTCFG */
86 #define SMBHSTCFG_HST_EN 1
87 #define SMBHSTCFG_SMB_SMI_EN 2
88 #define SMBHSTCFG_I2C_EN 4
89
90 /* Auxillary control register bits, ICH4+ only */
91 #define SMBAUXCTL_CRC 1
92 #define SMBAUXCTL_E32B 2
93
94 /* kill bit for SMBHSTCNT */
95 #define SMBHSTCNT_KILL 2
96
97 /* Other settings */
98 #define MAX_TIMEOUT 100
99 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
100
101 /* I801 command constants */
102 #define I801_QUICK 0x00
103 #define I801_BYTE 0x04
104 #define I801_BYTE_DATA 0x08
105 #define I801_WORD_DATA 0x0C
106 #define I801_PROC_CALL 0x10 /* unimplemented */
107 #define I801_BLOCK_DATA 0x14
108 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
109 #define I801_BLOCK_LAST 0x34
110 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
111 #define I801_START 0x40
112 #define I801_PEC_EN 0x80 /* ICH3 and later */
113
114 /* I801 Hosts Status register bits */
115 #define SMBHSTSTS_BYTE_DONE 0x80
116 #define SMBHSTSTS_INUSE_STS 0x40
117 #define SMBHSTSTS_SMBALERT_STS 0x20
118 #define SMBHSTSTS_FAILED 0x10
119 #define SMBHSTSTS_BUS_ERR 0x08
120 #define SMBHSTSTS_DEV_ERR 0x04
121 #define SMBHSTSTS_INTR 0x02
122 #define SMBHSTSTS_HOST_BUSY 0x01
123
124 static unsigned long i801_smba;
125 static unsigned char i801_original_hstcfg;
126 static struct pci_driver i801_driver;
127 static struct pci_dev *I801_dev;
128
129 #define FEATURE_SMBUS_PEC (1 << 0)
130 #define FEATURE_BLOCK_BUFFER (1 << 1)
131 #define FEATURE_BLOCK_PROC (1 << 2)
132 #define FEATURE_I2C_BLOCK_READ (1 << 3)
133 static unsigned int i801_features;
134
135 static int i801_transaction(int xact)
136 {
137 int temp;
138 int result = 0;
139 int timeout = 0;
140
141 dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
142 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
143 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
144 inb_p(SMBHSTDAT1));
145
146 /* Make sure the SMBus host is ready to start transmitting */
147 /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
148 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
149 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
150 temp);
151 outb_p(temp, SMBHSTSTS);
152 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
153 dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
154 return -1;
155 } else {
156 dev_dbg(&I801_dev->dev, "Successful!\n");
157 }
158 }
159
160 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
161 * INTREN, SMBSCMD are passed in xact */
162 outb_p(xact | I801_START, SMBHSTCNT);
163
164 /* We will always wait for a fraction of a second! */
165 do {
166 msleep(1);
167 temp = inb_p(SMBHSTSTS);
168 } while ((temp & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
169
170 /* If the SMBus is still busy, we give up */
171 if (timeout >= MAX_TIMEOUT) {
172 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
173 result = -1;
174 /* try to stop the current command */
175 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
176 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
177 msleep(1);
178 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
179 }
180
181 if (temp & SMBHSTSTS_FAILED) {
182 result = -1;
183 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
184 }
185
186 if (temp & SMBHSTSTS_BUS_ERR) {
187 result = -1;
188 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
189 "until next hard reset. (sorry!)\n");
190 /* Clock stops and slave is stuck in mid-transmission */
191 }
192
193 if (temp & SMBHSTSTS_DEV_ERR) {
194 result = -1;
195 dev_dbg(&I801_dev->dev, "Error: no response!\n");
196 }
197
198 if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
199 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
200
201 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
202 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
203 "(%02x)\n", temp);
204 }
205 dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
206 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
207 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
208 inb_p(SMBHSTDAT1));
209 return result;
210 }
211
212 /* wait for INTR bit as advised by Intel */
213 static void i801_wait_hwpec(void)
214 {
215 int timeout = 0;
216 int temp;
217
218 do {
219 msleep(1);
220 temp = inb_p(SMBHSTSTS);
221 } while ((!(temp & SMBHSTSTS_INTR))
222 && (timeout++ < MAX_TIMEOUT));
223
224 if (timeout >= MAX_TIMEOUT) {
225 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
226 }
227 outb_p(temp, SMBHSTSTS);
228 }
229
230 static int i801_block_transaction_by_block(union i2c_smbus_data *data,
231 char read_write, int hwpec)
232 {
233 int i, len;
234
235 inb_p(SMBHSTCNT); /* reset the data buffer index */
236
237 /* Use 32-byte buffer to process this transaction */
238 if (read_write == I2C_SMBUS_WRITE) {
239 len = data->block[0];
240 outb_p(len, SMBHSTDAT0);
241 for (i = 0; i < len; i++)
242 outb_p(data->block[i+1], SMBBLKDAT);
243 }
244
245 if (i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
246 I801_PEC_EN * hwpec))
247 return -1;
248
249 if (read_write == I2C_SMBUS_READ) {
250 len = inb_p(SMBHSTDAT0);
251 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
252 return -1;
253
254 data->block[0] = len;
255 for (i = 0; i < len; i++)
256 data->block[i + 1] = inb_p(SMBBLKDAT);
257 }
258 return 0;
259 }
260
261 static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
262 char read_write, int command,
263 int hwpec)
264 {
265 int i, len;
266 int smbcmd;
267 int temp;
268 int result = 0;
269 int timeout;
270 unsigned char errmask;
271
272 len = data->block[0];
273
274 if (read_write == I2C_SMBUS_WRITE) {
275 outb_p(len, SMBHSTDAT0);
276 outb_p(data->block[1], SMBBLKDAT);
277 }
278
279 for (i = 1; i <= len; i++) {
280 if (i == len && read_write == I2C_SMBUS_READ) {
281 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
282 smbcmd = I801_I2C_BLOCK_LAST;
283 else
284 smbcmd = I801_BLOCK_LAST;
285 } else {
286 if (command == I2C_SMBUS_I2C_BLOCK_DATA
287 && read_write == I2C_SMBUS_READ)
288 smbcmd = I801_I2C_BLOCK_DATA;
289 else
290 smbcmd = I801_BLOCK_DATA;
291 }
292 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
293
294 dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
295 "ADD=%02x, DAT0=%02x, DAT1=%02x, BLKDAT=%02x\n", i,
296 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
297 inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1), inb_p(SMBBLKDAT));
298
299 /* Make sure the SMBus host is ready to start transmitting */
300 temp = inb_p(SMBHSTSTS);
301 if (i == 1) {
302 /* Erroneous conditions before transaction:
303 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
304 errmask = 0x9f;
305 } else {
306 /* Erroneous conditions during transaction:
307 * Failed, Bus_Err, Dev_Err, Intr */
308 errmask = 0x1e;
309 }
310 if (temp & errmask) {
311 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
312 "Resetting...\n", temp);
313 outb_p(temp, SMBHSTSTS);
314 if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
315 dev_err(&I801_dev->dev,
316 "Reset failed! (%02x)\n", temp);
317 return -1;
318 }
319 if (i != 1)
320 /* if die in middle of block transaction, fail */
321 return -1;
322 }
323
324 if (i == 1)
325 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
326
327 /* We will always wait for a fraction of a second! */
328 timeout = 0;
329 do {
330 msleep(1);
331 temp = inb_p(SMBHSTSTS);
332 }
333 while ((!(temp & SMBHSTSTS_BYTE_DONE))
334 && (timeout++ < MAX_TIMEOUT));
335
336 /* If the SMBus is still busy, we give up */
337 if (timeout >= MAX_TIMEOUT) {
338 /* try to stop the current command */
339 dev_dbg(&I801_dev->dev, "Terminating the current "
340 "operation\n");
341 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
342 msleep(1);
343 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL),
344 SMBHSTCNT);
345 result = -1;
346 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
347 }
348
349 if (temp & SMBHSTSTS_FAILED) {
350 result = -1;
351 dev_dbg(&I801_dev->dev,
352 "Error: Failed bus transaction\n");
353 } else if (temp & SMBHSTSTS_BUS_ERR) {
354 result = -1;
355 dev_err(&I801_dev->dev, "Bus collision!\n");
356 } else if (temp & SMBHSTSTS_DEV_ERR) {
357 result = -1;
358 dev_dbg(&I801_dev->dev, "Error: no response!\n");
359 }
360
361 if (i == 1 && read_write == I2C_SMBUS_READ
362 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
363 len = inb_p(SMBHSTDAT0);
364 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
365 return -1;
366 data->block[0] = len;
367 }
368
369 /* Retrieve/store value in SMBBLKDAT */
370 if (read_write == I2C_SMBUS_READ)
371 data->block[i] = inb_p(SMBBLKDAT);
372 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
373 outb_p(data->block[i+1], SMBBLKDAT);
374 if ((temp & 0x9e) != 0x00)
375 outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
376
377 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
378 dev_dbg(&I801_dev->dev,
379 "Bad status (%02x) at end of transaction\n",
380 temp);
381 }
382 dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
383 "ADD=%02x, DAT0=%02x, DAT1=%02x, BLKDAT=%02x\n", i,
384 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
385 inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1), inb_p(SMBBLKDAT));
386
387 if (result < 0)
388 return result;
389 }
390 return result;
391 }
392
393 static int i801_set_block_buffer_mode(void)
394 {
395 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
396 if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
397 return -1;
398 return 0;
399 }
400
401 /* Block transaction function */
402 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
403 int command, int hwpec)
404 {
405 int result = 0;
406 unsigned char hostc;
407
408 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
409 if (read_write == I2C_SMBUS_WRITE) {
410 /* set I2C_EN bit in configuration register */
411 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
412 pci_write_config_byte(I801_dev, SMBHSTCFG,
413 hostc | SMBHSTCFG_I2C_EN);
414 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
415 dev_err(&I801_dev->dev,
416 "I2C block read is unsupported!\n");
417 return -1;
418 }
419 }
420
421 if (read_write == I2C_SMBUS_WRITE
422 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
423 if (data->block[0] < 1)
424 data->block[0] = 1;
425 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
426 data->block[0] = I2C_SMBUS_BLOCK_MAX;
427 } else {
428 data->block[0] = 32; /* max for SMBus block reads */
429 }
430
431 if ((i801_features & FEATURE_BLOCK_BUFFER)
432 && !(command == I2C_SMBUS_I2C_BLOCK_DATA
433 && read_write == I2C_SMBUS_READ)
434 && i801_set_block_buffer_mode() == 0)
435 result = i801_block_transaction_by_block(data, read_write,
436 hwpec);
437 else
438 result = i801_block_transaction_byte_by_byte(data, read_write,
439 command, hwpec);
440
441 if (result == 0 && hwpec)
442 i801_wait_hwpec();
443
444 if (command == I2C_SMBUS_I2C_BLOCK_DATA
445 && read_write == I2C_SMBUS_WRITE) {
446 /* restore saved configuration register value */
447 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
448 }
449 return result;
450 }
451
452 /* Return -1 on error. */
453 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
454 unsigned short flags, char read_write, u8 command,
455 int size, union i2c_smbus_data * data)
456 {
457 int hwpec;
458 int block = 0;
459 int ret, xact = 0;
460
461 hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
462 && size != I2C_SMBUS_QUICK
463 && size != I2C_SMBUS_I2C_BLOCK_DATA;
464
465 switch (size) {
466 case I2C_SMBUS_QUICK:
467 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
468 SMBHSTADD);
469 xact = I801_QUICK;
470 break;
471 case I2C_SMBUS_BYTE:
472 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
473 SMBHSTADD);
474 if (read_write == I2C_SMBUS_WRITE)
475 outb_p(command, SMBHSTCMD);
476 xact = I801_BYTE;
477 break;
478 case I2C_SMBUS_BYTE_DATA:
479 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
480 SMBHSTADD);
481 outb_p(command, SMBHSTCMD);
482 if (read_write == I2C_SMBUS_WRITE)
483 outb_p(data->byte, SMBHSTDAT0);
484 xact = I801_BYTE_DATA;
485 break;
486 case I2C_SMBUS_WORD_DATA:
487 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
488 SMBHSTADD);
489 outb_p(command, SMBHSTCMD);
490 if (read_write == I2C_SMBUS_WRITE) {
491 outb_p(data->word & 0xff, SMBHSTDAT0);
492 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
493 }
494 xact = I801_WORD_DATA;
495 break;
496 case I2C_SMBUS_BLOCK_DATA:
497 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
498 SMBHSTADD);
499 outb_p(command, SMBHSTCMD);
500 block = 1;
501 break;
502 case I2C_SMBUS_I2C_BLOCK_DATA:
503 /* NB: page 240 of ICH5 datasheet shows that the R/#W
504 * bit should be cleared here, even when reading */
505 outb_p((addr & 0x7f) << 1, SMBHSTADD);
506 if (read_write == I2C_SMBUS_READ) {
507 /* NB: page 240 of ICH5 datasheet also shows
508 * that DATA1 is the cmd field when reading */
509 outb_p(command, SMBHSTDAT1);
510 } else
511 outb_p(command, SMBHSTCMD);
512 block = 1;
513 break;
514 case I2C_SMBUS_PROC_CALL:
515 default:
516 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
517 return -1;
518 }
519
520 if (hwpec) /* enable/disable hardware PEC */
521 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
522 else
523 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
524
525 if(block)
526 ret = i801_block_transaction(data, read_write, size, hwpec);
527 else
528 ret = i801_transaction(xact | ENABLE_INT9);
529
530 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
531 time, so we forcibly disable it after every transaction. Turn off
532 E32B for the same reason. */
533 if (hwpec || block)
534 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
535 SMBAUXCTL);
536
537 if(block)
538 return ret;
539 if(ret)
540 return -1;
541 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
542 return 0;
543
544 switch (xact & 0x7f) {
545 case I801_BYTE: /* Result put in SMBHSTDAT0 */
546 case I801_BYTE_DATA:
547 data->byte = inb_p(SMBHSTDAT0);
548 break;
549 case I801_WORD_DATA:
550 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
551 break;
552 }
553 return 0;
554 }
555
556
557 static u32 i801_func(struct i2c_adapter *adapter)
558 {
559 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
560 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
561 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
562 ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
563 ((i801_features & FEATURE_I2C_BLOCK_READ) ?
564 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
565 }
566
567 static const struct i2c_algorithm smbus_algorithm = {
568 .smbus_xfer = i801_access,
569 .functionality = i801_func,
570 };
571
572 static struct i2c_adapter i801_adapter = {
573 .owner = THIS_MODULE,
574 .id = I2C_HW_SMBUS_I801,
575 .class = I2C_CLASS_HWMON,
576 .algo = &smbus_algorithm,
577 };
578
579 static struct pci_device_id i801_ids[] = {
580 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
581 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
582 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
583 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
584 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
585 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
586 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
587 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
588 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
589 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
590 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
591 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
592 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
593 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
594 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
595 { 0, }
596 };
597
598 MODULE_DEVICE_TABLE (pci, i801_ids);
599
600 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
601 {
602 unsigned char temp;
603 int err;
604
605 I801_dev = dev;
606 i801_features = 0;
607 switch (dev->device) {
608 case PCI_DEVICE_ID_INTEL_82801EB_3:
609 case PCI_DEVICE_ID_INTEL_ESB_4:
610 case PCI_DEVICE_ID_INTEL_ICH6_16:
611 case PCI_DEVICE_ID_INTEL_ICH7_17:
612 case PCI_DEVICE_ID_INTEL_ESB2_17:
613 case PCI_DEVICE_ID_INTEL_ICH8_5:
614 case PCI_DEVICE_ID_INTEL_ICH9_6:
615 case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
616 case PCI_DEVICE_ID_INTEL_ICH10_4:
617 case PCI_DEVICE_ID_INTEL_ICH10_5:
618 i801_features |= FEATURE_I2C_BLOCK_READ;
619 /* fall through */
620 case PCI_DEVICE_ID_INTEL_82801DB_3:
621 i801_features |= FEATURE_SMBUS_PEC;
622 i801_features |= FEATURE_BLOCK_BUFFER;
623 break;
624 }
625
626 err = pci_enable_device(dev);
627 if (err) {
628 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
629 err);
630 goto exit;
631 }
632
633 /* Determine the address of the SMBus area */
634 i801_smba = pci_resource_start(dev, SMBBAR);
635 if (!i801_smba) {
636 dev_err(&dev->dev, "SMBus base address uninitialized, "
637 "upgrade BIOS\n");
638 err = -ENODEV;
639 goto exit;
640 }
641
642 err = pci_request_region(dev, SMBBAR, i801_driver.name);
643 if (err) {
644 dev_err(&dev->dev, "Failed to request SMBus region "
645 "0x%lx-0x%Lx\n", i801_smba,
646 (unsigned long long)pci_resource_end(dev, SMBBAR));
647 goto exit;
648 }
649
650 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
651 i801_original_hstcfg = temp;
652 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
653 if (!(temp & SMBHSTCFG_HST_EN)) {
654 dev_info(&dev->dev, "Enabling SMBus device\n");
655 temp |= SMBHSTCFG_HST_EN;
656 }
657 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
658
659 if (temp & SMBHSTCFG_SMB_SMI_EN)
660 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
661 else
662 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
663
664 /* Clear special mode bits */
665 if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
666 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
667 SMBAUXCTL);
668
669 /* set up the sysfs linkage to our parent device */
670 i801_adapter.dev.parent = &dev->dev;
671
672 snprintf(i801_adapter.name, sizeof(i801_adapter.name),
673 "SMBus I801 adapter at %04lx", i801_smba);
674 err = i2c_add_adapter(&i801_adapter);
675 if (err) {
676 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
677 goto exit_release;
678 }
679 return 0;
680
681 exit_release:
682 pci_release_region(dev, SMBBAR);
683 exit:
684 return err;
685 }
686
687 static void __devexit i801_remove(struct pci_dev *dev)
688 {
689 i2c_del_adapter(&i801_adapter);
690 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
691 pci_release_region(dev, SMBBAR);
692 /*
693 * do not call pci_disable_device(dev) since it can cause hard hangs on
694 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
695 */
696 }
697
698 #ifdef CONFIG_PM
699 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
700 {
701 pci_save_state(dev);
702 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
703 pci_set_power_state(dev, pci_choose_state(dev, mesg));
704 return 0;
705 }
706
707 static int i801_resume(struct pci_dev *dev)
708 {
709 pci_set_power_state(dev, PCI_D0);
710 pci_restore_state(dev);
711 return pci_enable_device(dev);
712 }
713 #else
714 #define i801_suspend NULL
715 #define i801_resume NULL
716 #endif
717
718 static struct pci_driver i801_driver = {
719 .name = "i801_smbus",
720 .id_table = i801_ids,
721 .probe = i801_probe,
722 .remove = __devexit_p(i801_remove),
723 .suspend = i801_suspend,
724 .resume = i801_resume,
725 };
726
727 static int __init i2c_i801_init(void)
728 {
729 return pci_register_driver(&i801_driver);
730 }
731
732 static void __exit i2c_i801_exit(void)
733 {
734 pci_unregister_driver(&i801_driver);
735 }
736
737 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
738 "Jean Delvare <khali@linux-fr.org>");
739 MODULE_DESCRIPTION("I801 SMBus driver");
740 MODULE_LICENSE("GPL");
741
742 module_init(i2c_i801_init);
743 module_exit(i2c_i801_exit);
mah project overlay