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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / dma / ioat_dma.c
blob4017d9e7acd2a2b68020e2584c71dc654dd20cae
1 /*
2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2007 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 */
22
23 /*
24 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
25 * copy operations.
26 */
27
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/dmaengine.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include "ioatdma.h"
36 #include "ioatdma_registers.h"
37 #include "ioatdma_hw.h"
38
39 #define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common)
40 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
41 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
42 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx)
43
44 static int ioat_pending_level = 4;
45 module_param(ioat_pending_level, int, 0644);
46 MODULE_PARM_DESC(ioat_pending_level,
47 "high-water mark for pushing ioat descriptors (default: 4)");
48
49 /* internal functions */
50 static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan);
51 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan);
52
53 static struct ioat_desc_sw *
54 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
55 static struct ioat_desc_sw *
56 ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
57
58 static inline struct ioat_dma_chan *ioat_lookup_chan_by_index(
59 struct ioatdma_device *device,
60 int index)
61 {
62 return device->idx[index];
63 }
64
65 /**
66 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
67 * @irq: interrupt id
68 * @data: interrupt data
69 */
70 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
71 {
72 struct ioatdma_device *instance = data;
73 struct ioat_dma_chan *ioat_chan;
74 unsigned long attnstatus;
75 int bit;
76 u8 intrctrl;
77
78 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
79
80 if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
81 return IRQ_NONE;
82
83 if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
84 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
85 return IRQ_NONE;
86 }
87
88 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
89 for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
90 ioat_chan = ioat_lookup_chan_by_index(instance, bit);
91 tasklet_schedule(&ioat_chan->cleanup_task);
92 }
93
94 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
95 return IRQ_HANDLED;
96 }
97
98 /**
99 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
100 * @irq: interrupt id
101 * @data: interrupt data
102 */
103 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
104 {
105 struct ioat_dma_chan *ioat_chan = data;
106
107 tasklet_schedule(&ioat_chan->cleanup_task);
108
109 return IRQ_HANDLED;
110 }
111
112 static void ioat_dma_cleanup_tasklet(unsigned long data);
113
114 /**
115 * ioat_dma_enumerate_channels - find and initialize the device's channels
116 * @device: the device to be enumerated
117 */
118 static int ioat_dma_enumerate_channels(struct ioatdma_device *device)
119 {
120 u8 xfercap_scale;
121 u32 xfercap;
122 int i;
123 struct ioat_dma_chan *ioat_chan;
124
125 device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
126 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
127 xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
128
129 for (i = 0; i < device->common.chancnt; i++) {
130 ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL);
131 if (!ioat_chan) {
132 device->common.chancnt = i;
133 break;
134 }
135
136 ioat_chan->device = device;
137 ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1));
138 ioat_chan->xfercap = xfercap;
139 ioat_chan->desccount = 0;
140 if (ioat_chan->device->version != IOAT_VER_1_2) {
141 writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE
142 | IOAT_DMA_DCA_ANY_CPU,
143 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
144 }
145 spin_lock_init(&ioat_chan->cleanup_lock);
146 spin_lock_init(&ioat_chan->desc_lock);
147 INIT_LIST_HEAD(&ioat_chan->free_desc);
148 INIT_LIST_HEAD(&ioat_chan->used_desc);
149 /* This should be made common somewhere in dmaengine.c */
150 ioat_chan->common.device = &device->common;
151 list_add_tail(&ioat_chan->common.device_node,
152 &device->common.channels);
153 device->idx[i] = ioat_chan;
154 tasklet_init(&ioat_chan->cleanup_task,
155 ioat_dma_cleanup_tasklet,
156 (unsigned long) ioat_chan);
157 tasklet_disable(&ioat_chan->cleanup_task);
158 }
159 return device->common.chancnt;
160 }
161
162 /**
163 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
164 * descriptors to hw
165 * @chan: DMA channel handle
166 */
167 static inline void __ioat1_dma_memcpy_issue_pending(
168 struct ioat_dma_chan *ioat_chan)
169 {
170 ioat_chan->pending = 0;
171 writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET);
172 }
173
174 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
175 {
176 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
177
178 if (ioat_chan->pending != 0) {
179 spin_lock_bh(&ioat_chan->desc_lock);
180 __ioat1_dma_memcpy_issue_pending(ioat_chan);
181 spin_unlock_bh(&ioat_chan->desc_lock);
182 }
183 }
184
185 static inline void __ioat2_dma_memcpy_issue_pending(
186 struct ioat_dma_chan *ioat_chan)
187 {
188 ioat_chan->pending = 0;
189 writew(ioat_chan->dmacount,
190 ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
191 }
192
193 static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan)
194 {
195 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
196
197 if (ioat_chan->pending != 0) {
198 spin_lock_bh(&ioat_chan->desc_lock);
199 __ioat2_dma_memcpy_issue_pending(ioat_chan);
200 spin_unlock_bh(&ioat_chan->desc_lock);
201 }
202 }
203
204 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
205 {
206 struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
207 struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
208 struct ioat_desc_sw *prev, *new;
209 struct ioat_dma_descriptor *hw;
210 dma_cookie_t cookie;
211 LIST_HEAD(new_chain);
212 u32 copy;
213 size_t len;
214 dma_addr_t src, dst;
215 int orig_ack;
216 unsigned int desc_count = 0;
217
218 /* src and dest and len are stored in the initial descriptor */
219 len = first->len;
220 src = first->src;
221 dst = first->dst;
222 orig_ack = first->async_tx.ack;
223 new = first;
224
225 spin_lock_bh(&ioat_chan->desc_lock);
226 prev = to_ioat_desc(ioat_chan->used_desc.prev);
227 prefetch(prev->hw);
228 do {
229 copy = min_t(size_t, len, ioat_chan->xfercap);
230
231 new->async_tx.ack = 1;
232
233 hw = new->hw;
234 hw->size = copy;
235 hw->ctl = 0;
236 hw->src_addr = src;
237 hw->dst_addr = dst;
238 hw->next = 0;
239
240 /* chain together the physical address list for the HW */
241 wmb();
242 prev->hw->next = (u64) new->async_tx.phys;
243
244 len -= copy;
245 dst += copy;
246 src += copy;
247
248 list_add_tail(&new->node, &new_chain);
249 desc_count++;
250 prev = new;
251 } while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan)));
252
253 hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
254 if (new->async_tx.callback) {
255 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
256 if (first != new) {
257 /* move callback into to last desc */
258 new->async_tx.callback = first->async_tx.callback;
259 new->async_tx.callback_param
260 = first->async_tx.callback_param;
261 first->async_tx.callback = NULL;
262 first->async_tx.callback_param = NULL;
263 }
264 }
265
266 new->tx_cnt = desc_count;
267 new->async_tx.ack = orig_ack; /* client is in control of this ack */
268
269 /* store the original values for use in later cleanup */
270 if (new != first) {
271 new->src = first->src;
272 new->dst = first->dst;
273 new->len = first->len;
274 }
275
276 /* cookie incr and addition to used_list must be atomic */
277 cookie = ioat_chan->common.cookie;
278 cookie++;
279 if (cookie < 0)
280 cookie = 1;
281 ioat_chan->common.cookie = new->async_tx.cookie = cookie;
282
283 /* write address into NextDescriptor field of last desc in chain */
284 to_ioat_desc(ioat_chan->used_desc.prev)->hw->next =
285 first->async_tx.phys;
286 __list_splice(&new_chain, ioat_chan->used_desc.prev);
287
288 ioat_chan->dmacount += desc_count;
289 ioat_chan->pending += desc_count;
290 if (ioat_chan->pending >= ioat_pending_level)
291 __ioat1_dma_memcpy_issue_pending(ioat_chan);
292 spin_unlock_bh(&ioat_chan->desc_lock);
293
294 return cookie;
295 }
296
297 static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
298 {
299 struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
300 struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
301 struct ioat_desc_sw *new;
302 struct ioat_dma_descriptor *hw;
303 dma_cookie_t cookie;
304 u32 copy;
305 size_t len;
306 dma_addr_t src, dst;
307 int orig_ack;
308 unsigned int desc_count = 0;
309
310 /* src and dest and len are stored in the initial descriptor */
311 len = first->len;
312 src = first->src;
313 dst = first->dst;
314 orig_ack = first->async_tx.ack;
315 new = first;
316
317 /*
318 * ioat_chan->desc_lock is still in force in version 2 path
319 * it gets unlocked at end of this function
320 */
321 do {
322 copy = min_t(size_t, len, ioat_chan->xfercap);
323
324 new->async_tx.ack = 1;
325
326 hw = new->hw;
327 hw->size = copy;
328 hw->ctl = 0;
329 hw->src_addr = src;
330 hw->dst_addr = dst;
331
332 len -= copy;
333 dst += copy;
334 src += copy;
335 desc_count++;
336 } while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan)));
337
338 hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
339 if (new->async_tx.callback) {
340 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
341 if (first != new) {
342 /* move callback into to last desc */
343 new->async_tx.callback = first->async_tx.callback;
344 new->async_tx.callback_param
345 = first->async_tx.callback_param;
346 first->async_tx.callback = NULL;
347 first->async_tx.callback_param = NULL;
348 }
349 }
350
351 new->tx_cnt = desc_count;
352 new->async_tx.ack = orig_ack; /* client is in control of this ack */
353
354 /* store the original values for use in later cleanup */
355 if (new != first) {
356 new->src = first->src;
357 new->dst = first->dst;
358 new->len = first->len;
359 }
360
361 /* cookie incr and addition to used_list must be atomic */
362 cookie = ioat_chan->common.cookie;
363 cookie++;
364 if (cookie < 0)
365 cookie = 1;
366 ioat_chan->common.cookie = new->async_tx.cookie = cookie;
367
368 ioat_chan->dmacount += desc_count;
369 ioat_chan->pending += desc_count;
370 if (ioat_chan->pending >= ioat_pending_level)
371 __ioat2_dma_memcpy_issue_pending(ioat_chan);
372 spin_unlock_bh(&ioat_chan->desc_lock);
373
374 return cookie;
375 }
376
377 /**
378 * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
379 * @ioat_chan: the channel supplying the memory pool for the descriptors
380 * @flags: allocation flags
381 */
382 static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
383 struct ioat_dma_chan *ioat_chan,
384 gfp_t flags)
385 {
386 struct ioat_dma_descriptor *desc;
387 struct ioat_desc_sw *desc_sw;
388 struct ioatdma_device *ioatdma_device;
389 dma_addr_t phys;
390
391 ioatdma_device = to_ioatdma_device(ioat_chan->common.device);
392 desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
393 if (unlikely(!desc))
394 return NULL;
395
396 desc_sw = kzalloc(sizeof(*desc_sw), flags);
397 if (unlikely(!desc_sw)) {
398 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
399 return NULL;
400 }
401
402 memset(desc, 0, sizeof(*desc));
403 dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common);
404 switch (ioat_chan->device->version) {
405 case IOAT_VER_1_2:
406 desc_sw->async_tx.tx_submit = ioat1_tx_submit;
407 break;
408 case IOAT_VER_2_0:
409 desc_sw->async_tx.tx_submit = ioat2_tx_submit;
410 break;
411 }
412 INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
413
414 desc_sw->hw = desc;
415 desc_sw->async_tx.phys = phys;
416
417 return desc_sw;
418 }
419
420 static int ioat_initial_desc_count = 256;
421 module_param(ioat_initial_desc_count, int, 0644);
422 MODULE_PARM_DESC(ioat_initial_desc_count,
423 "initial descriptors per channel (default: 256)");
424
425 /**
426 * ioat2_dma_massage_chan_desc - link the descriptors into a circle
427 * @ioat_chan: the channel to be massaged
428 */
429 static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan)
430 {
431 struct ioat_desc_sw *desc, *_desc;
432
433 /* setup used_desc */
434 ioat_chan->used_desc.next = ioat_chan->free_desc.next;
435 ioat_chan->used_desc.prev = NULL;
436
437 /* pull free_desc out of the circle so that every node is a hw
438 * descriptor, but leave it pointing to the list
439 */
440 ioat_chan->free_desc.prev->next = ioat_chan->free_desc.next;
441 ioat_chan->free_desc.next->prev = ioat_chan->free_desc.prev;
442
443 /* circle link the hw descriptors */
444 desc = to_ioat_desc(ioat_chan->free_desc.next);
445 desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
446 list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) {
447 desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
448 }
449 }
450
451 /**
452 * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors
453 * @chan: the channel to be filled out
454 */
455 static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
456 {
457 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
458 struct ioat_desc_sw *desc;
459 u16 chanctrl;
460 u32 chanerr;
461 int i;
462 LIST_HEAD(tmp_list);
463
464 /* have we already been set up? */
465 if (!list_empty(&ioat_chan->free_desc))
466 return ioat_chan->desccount;
467
468 /* Setup register to interrupt and write completion status on error */
469 chanctrl = IOAT_CHANCTRL_ERR_INT_EN |
470 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
471 IOAT_CHANCTRL_ERR_COMPLETION_EN;
472 writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
473
474 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
475 if (chanerr) {
476 dev_err(&ioat_chan->device->pdev->dev,
477 "CHANERR = %x, clearing\n", chanerr);
478 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
479 }
480
481 /* Allocate descriptors */
482 for (i = 0; i < ioat_initial_desc_count; i++) {
483 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
484 if (!desc) {
485 dev_err(&ioat_chan->device->pdev->dev,
486 "Only %d initial descriptors\n", i);
487 break;
488 }
489 list_add_tail(&desc->node, &tmp_list);
490 }
491 spin_lock_bh(&ioat_chan->desc_lock);
492 ioat_chan->desccount = i;
493 list_splice(&tmp_list, &ioat_chan->free_desc);
494 if (ioat_chan->device->version != IOAT_VER_1_2)
495 ioat2_dma_massage_chan_desc(ioat_chan);
496 spin_unlock_bh(&ioat_chan->desc_lock);
497
498 /* allocate a completion writeback area */
499 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
500 ioat_chan->completion_virt =
501 pci_pool_alloc(ioat_chan->device->completion_pool,
502 GFP_KERNEL,
503 &ioat_chan->completion_addr);
504 memset(ioat_chan->completion_virt, 0,
505 sizeof(*ioat_chan->completion_virt));
506 writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF,
507 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
508 writel(((u64) ioat_chan->completion_addr) >> 32,
509 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
510
511 tasklet_enable(&ioat_chan->cleanup_task);
512 ioat_dma_start_null_desc(ioat_chan); /* give chain to dma device */
513 return ioat_chan->desccount;
514 }
515
516 /**
517 * ioat_dma_free_chan_resources - release all the descriptors
518 * @chan: the channel to be cleaned
519 */
520 static void ioat_dma_free_chan_resources(struct dma_chan *chan)
521 {
522 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
523 struct ioatdma_device *ioatdma_device = to_ioatdma_device(chan->device);
524 struct ioat_desc_sw *desc, *_desc;
525 int in_use_descs = 0;
526
527 tasklet_disable(&ioat_chan->cleanup_task);
528 ioat_dma_memcpy_cleanup(ioat_chan);
529
530 /* Delay 100ms after reset to allow internal DMA logic to quiesce
531 * before removing DMA descriptor resources.
532 */
533 writeb(IOAT_CHANCMD_RESET,
534 ioat_chan->reg_base
535 + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
536 mdelay(100);
537
538 spin_lock_bh(&ioat_chan->desc_lock);
539 switch (ioat_chan->device->version) {
540 case IOAT_VER_1_2:
541 list_for_each_entry_safe(desc, _desc,
542 &ioat_chan->used_desc, node) {
543 in_use_descs++;
544 list_del(&desc->node);
545 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
546 desc->async_tx.phys);
547 kfree(desc);
548 }
549 list_for_each_entry_safe(desc, _desc,
550 &ioat_chan->free_desc, node) {
551 list_del(&desc->node);
552 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
553 desc->async_tx.phys);
554 kfree(desc);
555 }
556 break;
557 case IOAT_VER_2_0:
558 list_for_each_entry_safe(desc, _desc,
559 ioat_chan->free_desc.next, node) {
560 list_del(&desc->node);
561 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
562 desc->async_tx.phys);
563 kfree(desc);
564 }
565 desc = to_ioat_desc(ioat_chan->free_desc.next);
566 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
567 desc->async_tx.phys);
568 kfree(desc);
569 INIT_LIST_HEAD(&ioat_chan->free_desc);
570 INIT_LIST_HEAD(&ioat_chan->used_desc);
571 break;
572 }
573 spin_unlock_bh(&ioat_chan->desc_lock);
574
575 pci_pool_free(ioatdma_device->completion_pool,
576 ioat_chan->completion_virt,
577 ioat_chan->completion_addr);
578
579 /* one is ok since we left it on there on purpose */
580 if (in_use_descs > 1)
581 dev_err(&ioat_chan->device->pdev->dev,
582 "Freeing %d in use descriptors!\n",
583 in_use_descs - 1);
584
585 ioat_chan->last_completion = ioat_chan->completion_addr = 0;
586 ioat_chan->pending = 0;
587 ioat_chan->dmacount = 0;
588 }
589
590 /**
591 * ioat_dma_get_next_descriptor - return the next available descriptor
592 * @ioat_chan: IOAT DMA channel handle
593 *
594 * Gets the next descriptor from the chain, and must be called with the
595 * channel's desc_lock held. Allocates more descriptors if the channel
596 * has run out.
597 */
598 static struct ioat_desc_sw *
599 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
600 {
601 struct ioat_desc_sw *new;
602
603 if (!list_empty(&ioat_chan->free_desc)) {
604 new = to_ioat_desc(ioat_chan->free_desc.next);
605 list_del(&new->node);
606 } else {
607 /* try to get another desc */
608 new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
609 if (!new) {
610 dev_err(&ioat_chan->device->pdev->dev,
611 "alloc failed\n");
612 return NULL;
613 }
614 }
615
616 prefetch(new->hw);
617 return new;
618 }
619
620 static struct ioat_desc_sw *
621 ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
622 {
623 struct ioat_desc_sw *new;
624
625 /*
626 * used.prev points to where to start processing
627 * used.next points to next free descriptor
628 * if used.prev == NULL, there are none waiting to be processed
629 * if used.next == used.prev.prev, there is only one free descriptor,
630 * and we need to use it to as a noop descriptor before
631 * linking in a new set of descriptors, since the device
632 * has probably already read the pointer to it
633 */
634 if (ioat_chan->used_desc.prev &&
635 ioat_chan->used_desc.next == ioat_chan->used_desc.prev->prev) {
636
637 struct ioat_desc_sw *desc;
638 struct ioat_desc_sw *noop_desc;
639 int i;
640
641 /* set up the noop descriptor */
642 noop_desc = to_ioat_desc(ioat_chan->used_desc.next);
643 noop_desc->hw->size = 0;
644 noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL;
645 noop_desc->hw->src_addr = 0;
646 noop_desc->hw->dst_addr = 0;
647
648 ioat_chan->used_desc.next = ioat_chan->used_desc.next->next;
649 ioat_chan->pending++;
650 ioat_chan->dmacount++;
651
652 /* try to get a few more descriptors */
653 for (i = 16; i; i--) {
654 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
655 if (!desc) {
656 dev_err(&ioat_chan->device->pdev->dev,
657 "alloc failed\n");
658 break;
659 }
660 list_add_tail(&desc->node, ioat_chan->used_desc.next);
661
662 desc->hw->next
663 = to_ioat_desc(desc->node.next)->async_tx.phys;
664 to_ioat_desc(desc->node.prev)->hw->next
665 = desc->async_tx.phys;
666 ioat_chan->desccount++;
667 }
668
669 ioat_chan->used_desc.next = noop_desc->node.next;
670 }
671 new = to_ioat_desc(ioat_chan->used_desc.next);
672 prefetch(new);
673 ioat_chan->used_desc.next = new->node.next;
674
675 if (ioat_chan->used_desc.prev == NULL)
676 ioat_chan->used_desc.prev = &new->node;
677
678 prefetch(new->hw);
679 return new;
680 }
681
682 static struct ioat_desc_sw *ioat_dma_get_next_descriptor(
683 struct ioat_dma_chan *ioat_chan)
684 {
685 if (!ioat_chan)
686 return NULL;
687
688 switch (ioat_chan->device->version) {
689 case IOAT_VER_1_2:
690 return ioat1_dma_get_next_descriptor(ioat_chan);
691 break;
692 case IOAT_VER_2_0:
693 return ioat2_dma_get_next_descriptor(ioat_chan);
694 break;
695 }
696 return NULL;
697 }
698
699 static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy(
700 struct dma_chan *chan,
701 dma_addr_t dma_dest,
702 dma_addr_t dma_src,
703 size_t len,
704 unsigned long flags)
705 {
706 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
707 struct ioat_desc_sw *new;
708
709 spin_lock_bh(&ioat_chan->desc_lock);
710 new = ioat_dma_get_next_descriptor(ioat_chan);
711 spin_unlock_bh(&ioat_chan->desc_lock);
712
713 if (new) {
714 new->len = len;
715 new->dst = dma_dest;
716 new->src = dma_src;
717 new->async_tx.ack = 0;
718 return &new->async_tx;
719 } else
720 return NULL;
721 }
722
723 static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy(
724 struct dma_chan *chan,
725 dma_addr_t dma_dest,
726 dma_addr_t dma_src,
727 size_t len,
728 unsigned long flags)
729 {
730 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
731 struct ioat_desc_sw *new;
732
733 spin_lock_bh(&ioat_chan->desc_lock);
734 new = ioat2_dma_get_next_descriptor(ioat_chan);
735
736 /*
737 * leave ioat_chan->desc_lock set in ioat 2 path
738 * it will get unlocked at end of tx_submit
739 */
740
741 if (new) {
742 new->len = len;
743 new->dst = dma_dest;
744 new->src = dma_src;
745 new->async_tx.ack = 0;
746 return &new->async_tx;
747 } else
748 return NULL;
749 }
750
751 static void ioat_dma_cleanup_tasklet(unsigned long data)
752 {
753 struct ioat_dma_chan *chan = (void *)data;
754 ioat_dma_memcpy_cleanup(chan);
755 writew(IOAT_CHANCTRL_INT_DISABLE,
756 chan->reg_base + IOAT_CHANCTRL_OFFSET);
757 }
758
759 /**
760 * ioat_dma_memcpy_cleanup - cleanup up finished descriptors
761 * @chan: ioat channel to be cleaned up
762 */
763 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
764 {
765 unsigned long phys_complete;
766 struct ioat_desc_sw *desc, *_desc;
767 dma_cookie_t cookie = 0;
768 unsigned long desc_phys;
769 struct ioat_desc_sw *latest_desc;
770
771 prefetch(ioat_chan->completion_virt);
772
773 if (!spin_trylock_bh(&ioat_chan->cleanup_lock))
774 return;
775
776 /* The completion writeback can happen at any time,
777 so reads by the driver need to be atomic operations
778 The descriptor physical addresses are limited to 32-bits
779 when the CPU can only do a 32-bit mov */
780
781 #if (BITS_PER_LONG == 64)
782 phys_complete =
783 ioat_chan->completion_virt->full
784 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
785 #else
786 phys_complete =
787 ioat_chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
788 #endif
789
790 if ((ioat_chan->completion_virt->full
791 & IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
792 IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
793 dev_err(&ioat_chan->device->pdev->dev,
794 "Channel halted, chanerr = %x\n",
795 readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET));
796
797 /* TODO do something to salvage the situation */
798 }
799
800 if (phys_complete == ioat_chan->last_completion) {
801 spin_unlock_bh(&ioat_chan->cleanup_lock);
802 return;
803 }
804
805 cookie = 0;
806 spin_lock_bh(&ioat_chan->desc_lock);
807 switch (ioat_chan->device->version) {
808 case IOAT_VER_1_2:
809 list_for_each_entry_safe(desc, _desc,
810 &ioat_chan->used_desc, node) {
811
812 /*
813 * Incoming DMA requests may use multiple descriptors,
814 * due to exceeding xfercap, perhaps. If so, only the
815 * last one will have a cookie, and require unmapping.
816 */
817 if (desc->async_tx.cookie) {
818 cookie = desc->async_tx.cookie;
819
820 /*
821 * yes we are unmapping both _page and _single
822 * alloc'd regions with unmap_page. Is this
823 * *really* that bad?
824 */
825 pci_unmap_page(ioat_chan->device->pdev,
826 pci_unmap_addr(desc, dst),
827 pci_unmap_len(desc, len),
828 PCI_DMA_FROMDEVICE);
829 pci_unmap_page(ioat_chan->device->pdev,
830 pci_unmap_addr(desc, src),
831 pci_unmap_len(desc, len),
832 PCI_DMA_TODEVICE);
833
834 if (desc->async_tx.callback) {
835 desc->async_tx.callback(desc->async_tx.callback_param);
836 desc->async_tx.callback = NULL;
837 }
838 }
839
840 if (desc->async_tx.phys != phys_complete) {
841 /*
842 * a completed entry, but not the last, so clean
843 * up if the client is done with the descriptor
844 */
845 if (desc->async_tx.ack) {
846 list_del(&desc->node);
847 list_add_tail(&desc->node,
848 &ioat_chan->free_desc);
849 } else
850 desc->async_tx.cookie = 0;
851 } else {
852 /*
853 * last used desc. Do not remove, so we can
854 * append from it, but don't look at it next
855 * time, either
856 */
857 desc->async_tx.cookie = 0;
858
859 /* TODO check status bits? */
860 break;
861 }
862 }
863 break;
864 case IOAT_VER_2_0:
865 /* has some other thread has already cleaned up? */
866 if (ioat_chan->used_desc.prev == NULL)
867 break;
868
869 /* work backwards to find latest finished desc */
870 desc = to_ioat_desc(ioat_chan->used_desc.next);
871 latest_desc = NULL;
872 do {
873 desc = to_ioat_desc(desc->node.prev);
874 desc_phys = (unsigned long)desc->async_tx.phys
875 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
876 if (desc_phys == phys_complete) {
877 latest_desc = desc;
878 break;
879 }
880 } while (&desc->node != ioat_chan->used_desc.prev);
881
882 if (latest_desc != NULL) {
883
884 /* work forwards to clear finished descriptors */
885 for (desc = to_ioat_desc(ioat_chan->used_desc.prev);
886 &desc->node != latest_desc->node.next &&
887 &desc->node != ioat_chan->used_desc.next;
888 desc = to_ioat_desc(desc->node.next)) {
889 if (desc->async_tx.cookie) {
890 cookie = desc->async_tx.cookie;
891 desc->async_tx.cookie = 0;
892
893 pci_unmap_page(ioat_chan->device->pdev,
894 pci_unmap_addr(desc, dst),
895 pci_unmap_len(desc, len),
896 PCI_DMA_FROMDEVICE);
897 pci_unmap_page(ioat_chan->device->pdev,
898 pci_unmap_addr(desc, src),
899 pci_unmap_len(desc, len),
900 PCI_DMA_TODEVICE);
901
902 if (desc->async_tx.callback) {
903 desc->async_tx.callback(desc->async_tx.callback_param);
904 desc->async_tx.callback = NULL;
905 }
906 }
907 }
908
909 /* move used.prev up beyond those that are finished */
910 if (&desc->node == ioat_chan->used_desc.next)
911 ioat_chan->used_desc.prev = NULL;
912 else
913 ioat_chan->used_desc.prev = &desc->node;
914 }
915 break;
916 }
917
918 spin_unlock_bh(&ioat_chan->desc_lock);
919
920 ioat_chan->last_completion = phys_complete;
921 if (cookie != 0)
922 ioat_chan->completed_cookie = cookie;
923
924 spin_unlock_bh(&ioat_chan->cleanup_lock);
925 }
926
927 static void ioat_dma_dependency_added(struct dma_chan *chan)
928 {
929 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
930 spin_lock_bh(&ioat_chan->desc_lock);
931 if (ioat_chan->pending == 0) {
932 spin_unlock_bh(&ioat_chan->desc_lock);
933 ioat_dma_memcpy_cleanup(ioat_chan);
934 } else
935 spin_unlock_bh(&ioat_chan->desc_lock);
936 }
937
938 /**
939 * ioat_dma_is_complete - poll the status of a IOAT DMA transaction
940 * @chan: IOAT DMA channel handle
941 * @cookie: DMA transaction identifier
942 * @done: if not %NULL, updated with last completed transaction
943 * @used: if not %NULL, updated with last used transaction
944 */
945 static enum dma_status ioat_dma_is_complete(struct dma_chan *chan,
946 dma_cookie_t cookie,
947 dma_cookie_t *done,
948 dma_cookie_t *used)
949 {
950 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
951 dma_cookie_t last_used;
952 dma_cookie_t last_complete;
953 enum dma_status ret;
954
955 last_used = chan->cookie;
956 last_complete = ioat_chan->completed_cookie;
957
958 if (done)
959 *done = last_complete;
960 if (used)
961 *used = last_used;
962
963 ret = dma_async_is_complete(cookie, last_complete, last_used);
964 if (ret == DMA_SUCCESS)
965 return ret;
966
967 ioat_dma_memcpy_cleanup(ioat_chan);
968
969 last_used = chan->cookie;
970 last_complete = ioat_chan->completed_cookie;
971
972 if (done)
973 *done = last_complete;
974 if (used)
975 *used = last_used;
976
977 return dma_async_is_complete(cookie, last_complete, last_used);
978 }
979
980 static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
981 {
982 struct ioat_desc_sw *desc;
983
984 spin_lock_bh(&ioat_chan->desc_lock);
985
986 desc = ioat_dma_get_next_descriptor(ioat_chan);
987 desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL
988 | IOAT_DMA_DESCRIPTOR_CTL_INT_GN
989 | IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
990 desc->hw->size = 0;
991 desc->hw->src_addr = 0;
992 desc->hw->dst_addr = 0;
993 desc->async_tx.ack = 1;
994 switch (ioat_chan->device->version) {
995 case IOAT_VER_1_2:
996 desc->hw->next = 0;
997 list_add_tail(&desc->node, &ioat_chan->used_desc);
998
999 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1000 ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
1001 writel(((u64) desc->async_tx.phys) >> 32,
1002 ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
1003
1004 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
1005 + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
1006 break;
1007 case IOAT_VER_2_0:
1008 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1009 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
1010 writel(((u64) desc->async_tx.phys) >> 32,
1011 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
1012
1013 ioat_chan->dmacount++;
1014 __ioat2_dma_memcpy_issue_pending(ioat_chan);
1015 break;
1016 }
1017 spin_unlock_bh(&ioat_chan->desc_lock);
1018 }
1019
1020 /*
1021 * Perform a IOAT transaction to verify the HW works.
1022 */
1023 #define IOAT_TEST_SIZE 2000
1024
1025 static void ioat_dma_test_callback(void *dma_async_param)
1026 {
1027 printk(KERN_ERR "ioatdma: ioat_dma_test_callback(%p)\n",
1028 dma_async_param);
1029 }
1030
1031 /**
1032 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
1033 * @device: device to be tested
1034 */
1035 static int ioat_dma_self_test(struct ioatdma_device *device)
1036 {
1037 int i;
1038 u8 *src;
1039 u8 *dest;
1040 struct dma_chan *dma_chan;
1041 struct dma_async_tx_descriptor *tx;
1042 dma_addr_t dma_dest, dma_src;
1043 dma_cookie_t cookie;
1044 int err = 0;
1045
1046 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1047 if (!src)
1048 return -ENOMEM;
1049 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1050 if (!dest) {
1051 kfree(src);
1052 return -ENOMEM;
1053 }
1054
1055 /* Fill in src buffer */
1056 for (i = 0; i < IOAT_TEST_SIZE; i++)
1057 src[i] = (u8)i;
1058
1059 /* Start copy, using first DMA channel */
1060 dma_chan = container_of(device->common.channels.next,
1061 struct dma_chan,
1062 device_node);
1063 if (device->common.device_alloc_chan_resources(dma_chan) < 1) {
1064 dev_err(&device->pdev->dev,
1065 "selftest cannot allocate chan resource\n");
1066 err = -ENODEV;
1067 goto out;
1068 }
1069
1070 dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE,
1071 DMA_TO_DEVICE);
1072 dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE,
1073 DMA_FROM_DEVICE);
1074 tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
1075 IOAT_TEST_SIZE, 0);
1076 if (!tx) {
1077 dev_err(&device->pdev->dev,
1078 "Self-test prep failed, disabling\n");
1079 err = -ENODEV;
1080 goto free_resources;
1081 }
1082
1083 async_tx_ack(tx);
1084 tx->callback = ioat_dma_test_callback;
1085 tx->callback_param = (void *)0x8086;
1086 cookie = tx->tx_submit(tx);
1087 if (cookie < 0) {
1088 dev_err(&device->pdev->dev,
1089 "Self-test setup failed, disabling\n");
1090 err = -ENODEV;
1091 goto free_resources;
1092 }
1093 device->common.device_issue_pending(dma_chan);
1094 msleep(1);
1095
1096 if (device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL)
1097 != DMA_SUCCESS) {
1098 dev_err(&device->pdev->dev,
1099 "Self-test copy timed out, disabling\n");
1100 err = -ENODEV;
1101 goto free_resources;
1102 }
1103 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
1104 dev_err(&device->pdev->dev,
1105 "Self-test copy failed compare, disabling\n");
1106 err = -ENODEV;
1107 goto free_resources;
1108 }
1109
1110 free_resources:
1111 device->common.device_free_chan_resources(dma_chan);
1112 out:
1113 kfree(src);
1114 kfree(dest);
1115 return err;
1116 }
1117
1118 static char ioat_interrupt_style[32] = "msix";
1119 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
1120 sizeof(ioat_interrupt_style), 0644);
1121 MODULE_PARM_DESC(ioat_interrupt_style,
1122 "set ioat interrupt style: msix (default), "
1123 "msix-single-vector, msi, intx)");
1124
1125 /**
1126 * ioat_dma_setup_interrupts - setup interrupt handler
1127 * @device: ioat device
1128 */
1129 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
1130 {
1131 struct ioat_dma_chan *ioat_chan;
1132 int err, i, j, msixcnt;
1133 u8 intrctrl = 0;
1134
1135 if (!strcmp(ioat_interrupt_style, "msix"))
1136 goto msix;
1137 if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
1138 goto msix_single_vector;
1139 if (!strcmp(ioat_interrupt_style, "msi"))
1140 goto msi;
1141 if (!strcmp(ioat_interrupt_style, "intx"))
1142 goto intx;
1143 dev_err(&device->pdev->dev, "invalid ioat_interrupt_style %s\n",
1144 ioat_interrupt_style);
1145 goto err_no_irq;
1146
1147 msix:
1148 /* The number of MSI-X vectors should equal the number of channels */
1149 msixcnt = device->common.chancnt;
1150 for (i = 0; i < msixcnt; i++)
1151 device->msix_entries[i].entry = i;
1152
1153 err = pci_enable_msix(device->pdev, device->msix_entries, msixcnt);
1154 if (err < 0)
1155 goto msi;
1156 if (err > 0)
1157 goto msix_single_vector;
1158
1159 for (i = 0; i < msixcnt; i++) {
1160 ioat_chan = ioat_lookup_chan_by_index(device, i);
1161 err = request_irq(device->msix_entries[i].vector,
1162 ioat_dma_do_interrupt_msix,
1163 0, "ioat-msix", ioat_chan);
1164 if (err) {
1165 for (j = 0; j < i; j++) {
1166 ioat_chan =
1167 ioat_lookup_chan_by_index(device, j);
1168 free_irq(device->msix_entries[j].vector,
1169 ioat_chan);
1170 }
1171 goto msix_single_vector;
1172 }
1173 }
1174 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
1175 device->irq_mode = msix_multi_vector;
1176 goto done;
1177
1178 msix_single_vector:
1179 device->msix_entries[0].entry = 0;
1180 err = pci_enable_msix(device->pdev, device->msix_entries, 1);
1181 if (err)
1182 goto msi;
1183
1184 err = request_irq(device->msix_entries[0].vector, ioat_dma_do_interrupt,
1185 0, "ioat-msix", device);
1186 if (err) {
1187 pci_disable_msix(device->pdev);
1188 goto msi;
1189 }
1190 device->irq_mode = msix_single_vector;
1191 goto done;
1192
1193 msi:
1194 err = pci_enable_msi(device->pdev);
1195 if (err)
1196 goto intx;
1197
1198 err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1199 0, "ioat-msi", device);
1200 if (err) {
1201 pci_disable_msi(device->pdev);
1202 goto intx;
1203 }
1204 /*
1205 * CB 1.2 devices need a bit set in configuration space to enable MSI
1206 */
1207 if (device->version == IOAT_VER_1_2) {
1208 u32 dmactrl;
1209 pci_read_config_dword(device->pdev,
1210 IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1211 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1212 pci_write_config_dword(device->pdev,
1213 IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1214 }
1215 device->irq_mode = msi;
1216 goto done;
1217
1218 intx:
1219 err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1220 IRQF_SHARED, "ioat-intx", device);
1221 if (err)
1222 goto err_no_irq;
1223 device->irq_mode = intx;
1224
1225 done:
1226 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
1227 writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
1228 return 0;
1229
1230 err_no_irq:
1231 /* Disable all interrupt generation */
1232 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1233 dev_err(&device->pdev->dev, "no usable interrupts\n");
1234 device->irq_mode = none;
1235 return -1;
1236 }
1237
1238 /**
1239 * ioat_dma_remove_interrupts - remove whatever interrupts were set
1240 * @device: ioat device
1241 */
1242 static void ioat_dma_remove_interrupts(struct ioatdma_device *device)
1243 {
1244 struct ioat_dma_chan *ioat_chan;
1245 int i;
1246
1247 /* Disable all interrupt generation */
1248 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1249
1250 switch (device->irq_mode) {
1251 case msix_multi_vector:
1252 for (i = 0; i < device->common.chancnt; i++) {
1253 ioat_chan = ioat_lookup_chan_by_index(device, i);
1254 free_irq(device->msix_entries[i].vector, ioat_chan);
1255 }
1256 pci_disable_msix(device->pdev);
1257 break;
1258 case msix_single_vector:
1259 free_irq(device->msix_entries[0].vector, device);
1260 pci_disable_msix(device->pdev);
1261 break;
1262 case msi:
1263 free_irq(device->pdev->irq, device);
1264 pci_disable_msi(device->pdev);
1265 break;
1266 case intx:
1267 free_irq(device->pdev->irq, device);
1268 break;
1269 case none:
1270 dev_warn(&device->pdev->dev,
1271 "call to %s without interrupts setup\n", __func__);
1272 }
1273 device->irq_mode = none;
1274 }
1275
1276 struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
1277 void __iomem *iobase)
1278 {
1279 int err;
1280 struct ioatdma_device *device;
1281
1282 device = kzalloc(sizeof(*device), GFP_KERNEL);
1283 if (!device) {
1284 err = -ENOMEM;
1285 goto err_kzalloc;
1286 }
1287 device->pdev = pdev;
1288 device->reg_base = iobase;
1289 device->version = readb(device->reg_base + IOAT_VER_OFFSET);
1290
1291 /* DMA coherent memory pool for DMA descriptor allocations */
1292 device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1293 sizeof(struct ioat_dma_descriptor),
1294 64, 0);
1295 if (!device->dma_pool) {
1296 err = -ENOMEM;
1297 goto err_dma_pool;
1298 }
1299
1300 device->completion_pool = pci_pool_create("completion_pool", pdev,
1301 sizeof(u64), SMP_CACHE_BYTES,
1302 SMP_CACHE_BYTES);
1303 if (!device->completion_pool) {
1304 err = -ENOMEM;
1305 goto err_completion_pool;
1306 }
1307
1308 INIT_LIST_HEAD(&device->common.channels);
1309 ioat_dma_enumerate_channels(device);
1310
1311 device->common.device_alloc_chan_resources =
1312 ioat_dma_alloc_chan_resources;
1313 device->common.device_free_chan_resources =
1314 ioat_dma_free_chan_resources;
1315 device->common.dev = &pdev->dev;
1316
1317 dma_cap_set(DMA_MEMCPY, device->common.cap_mask);
1318 device->common.device_is_tx_complete = ioat_dma_is_complete;
1319 device->common.device_dependency_added = ioat_dma_dependency_added;
1320 switch (device->version) {
1321 case IOAT_VER_1_2:
1322 device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1323 device->common.device_issue_pending =
1324 ioat1_dma_memcpy_issue_pending;
1325 break;
1326 case IOAT_VER_2_0:
1327 device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy;
1328 device->common.device_issue_pending =
1329 ioat2_dma_memcpy_issue_pending;
1330 break;
1331 }
1332
1333 dev_err(&device->pdev->dev,
1334 "Intel(R) I/OAT DMA Engine found,"
1335 " %d channels, device version 0x%02x, driver version %s\n",
1336 device->common.chancnt, device->version, IOAT_DMA_VERSION);
1337
1338 err = ioat_dma_setup_interrupts(device);
1339 if (err)
1340 goto err_setup_interrupts;
1341
1342 err = ioat_dma_self_test(device);
1343 if (err)
1344 goto err_self_test;
1345
1346 dma_async_device_register(&device->common);
1347
1348 return device;
1349
1350 err_self_test:
1351 ioat_dma_remove_interrupts(device);
1352 err_setup_interrupts:
1353 pci_pool_destroy(device->completion_pool);
1354 err_completion_pool:
1355 pci_pool_destroy(device->dma_pool);
1356 err_dma_pool:
1357 kfree(device);
1358 err_kzalloc:
1359 dev_err(&pdev->dev,
1360 "Intel(R) I/OAT DMA Engine initialization failed\n");
1361 return NULL;
1362 }
1363
1364 void ioat_dma_remove(struct ioatdma_device *device)
1365 {
1366 struct dma_chan *chan, *_chan;
1367 struct ioat_dma_chan *ioat_chan;
1368
1369 ioat_dma_remove_interrupts(device);
1370
1371 dma_async_device_unregister(&device->common);
1372
1373 pci_pool_destroy(device->dma_pool);
1374 pci_pool_destroy(device->completion_pool);
1375
1376 iounmap(device->reg_base);
1377 pci_release_regions(device->pdev);
1378 pci_disable_device(device->pdev);
1379
1380 list_for_each_entry_safe(chan, _chan,
1381 &device->common.channels, device_node) {
1382 ioat_chan = to_ioat_chan(chan);
1383 list_del(&chan->device_node);
1384 kfree(ioat_chan);
1385 }
1386 kfree(device);
1387 }
1388
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