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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / char / drm / radeon_drv.h
blob173ae620223a052238a0a212711e25290bff4f0c
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 /* General customization:
35 */
36
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20060524"
42
43 /* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2
101 */
102 #define DRIVER_MAJOR 1
103 #define DRIVER_MINOR 28
104 #define DRIVER_PATCHLEVEL 0
105
106 /*
107 * Radeon chip families
108 */
109 enum radeon_family {
110 CHIP_R100,
111 CHIP_RV100,
112 CHIP_RS100,
113 CHIP_RV200,
114 CHIP_RS200,
115 CHIP_R200,
116 CHIP_RV250,
117 CHIP_RS300,
118 CHIP_RV280,
119 CHIP_R300,
120 CHIP_R350,
121 CHIP_RV350,
122 CHIP_RV380,
123 CHIP_R420,
124 CHIP_RV410,
125 CHIP_RS400,
126 CHIP_RS690,
127 CHIP_RV515,
128 CHIP_R520,
129 CHIP_RV530,
130 CHIP_RV560,
131 CHIP_RV570,
132 CHIP_R580,
133 CHIP_LAST,
134 };
135
136 enum radeon_cp_microcode_version {
137 UCODE_R100,
138 UCODE_R200,
139 UCODE_R300,
140 };
141
142 /*
143 * Chip flags
144 */
145 enum radeon_chip_flags {
146 RADEON_FAMILY_MASK = 0x0000ffffUL,
147 RADEON_FLAGS_MASK = 0xffff0000UL,
148 RADEON_IS_MOBILITY = 0x00010000UL,
149 RADEON_IS_IGP = 0x00020000UL,
150 RADEON_SINGLE_CRTC = 0x00040000UL,
151 RADEON_IS_AGP = 0x00080000UL,
152 RADEON_HAS_HIERZ = 0x00100000UL,
153 RADEON_IS_PCIE = 0x00200000UL,
154 RADEON_NEW_MEMMAP = 0x00400000UL,
155 RADEON_IS_PCI = 0x00800000UL,
156 RADEON_IS_IGPGART = 0x01000000UL,
157 };
158
159 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
160 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
161 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
162
163 typedef struct drm_radeon_freelist {
164 unsigned int age;
165 struct drm_buf *buf;
166 struct drm_radeon_freelist *next;
167 struct drm_radeon_freelist *prev;
168 } drm_radeon_freelist_t;
169
170 typedef struct drm_radeon_ring_buffer {
171 u32 *start;
172 u32 *end;
173 int size;
174 int size_l2qw;
175
176 int rptr_update; /* Double Words */
177 int rptr_update_l2qw; /* log2 Quad Words */
178
179 int fetch_size; /* Double Words */
180 int fetch_size_l2ow; /* log2 Oct Words */
181
182 u32 tail;
183 u32 tail_mask;
184 int space;
185
186 int high_mark;
187 } drm_radeon_ring_buffer_t;
188
189 typedef struct drm_radeon_depth_clear_t {
190 u32 rb3d_cntl;
191 u32 rb3d_zstencilcntl;
192 u32 se_cntl;
193 } drm_radeon_depth_clear_t;
194
195 struct drm_radeon_driver_file_fields {
196 int64_t radeon_fb_delta;
197 };
198
199 struct mem_block {
200 struct mem_block *next;
201 struct mem_block *prev;
202 int start;
203 int size;
204 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
205 };
206
207 struct radeon_surface {
208 int refcount;
209 u32 lower;
210 u32 upper;
211 u32 flags;
212 };
213
214 struct radeon_virt_surface {
215 int surface_index;
216 u32 lower;
217 u32 upper;
218 u32 flags;
219 struct drm_file *file_priv;
220 };
221
222 typedef struct drm_radeon_private {
223 drm_radeon_ring_buffer_t ring;
224 drm_radeon_sarea_t *sarea_priv;
225
226 u32 fb_location;
227 u32 fb_size;
228 int new_memmap;
229
230 int gart_size;
231 u32 gart_vm_start;
232 unsigned long gart_buffers_offset;
233
234 int cp_mode;
235 int cp_running;
236
237 drm_radeon_freelist_t *head;
238 drm_radeon_freelist_t *tail;
239 int last_buf;
240 volatile u32 *scratch;
241 int writeback_works;
242
243 int usec_timeout;
244
245 int microcode_version;
246
247 struct {
248 u32 boxes;
249 int freelist_timeouts;
250 int freelist_loops;
251 int requested_bufs;
252 int last_frame_reads;
253 int last_clear_reads;
254 int clears;
255 int texture_uploads;
256 } stats;
257
258 int do_boxes;
259 int page_flipping;
260
261 u32 color_fmt;
262 unsigned int front_offset;
263 unsigned int front_pitch;
264 unsigned int back_offset;
265 unsigned int back_pitch;
266
267 u32 depth_fmt;
268 unsigned int depth_offset;
269 unsigned int depth_pitch;
270
271 u32 front_pitch_offset;
272 u32 back_pitch_offset;
273 u32 depth_pitch_offset;
274
275 drm_radeon_depth_clear_t depth_clear;
276
277 unsigned long ring_offset;
278 unsigned long ring_rptr_offset;
279 unsigned long buffers_offset;
280 unsigned long gart_textures_offset;
281
282 drm_local_map_t *sarea;
283 drm_local_map_t *mmio;
284 drm_local_map_t *cp_ring;
285 drm_local_map_t *ring_rptr;
286 drm_local_map_t *gart_textures;
287
288 struct mem_block *gart_heap;
289 struct mem_block *fb_heap;
290
291 /* SW interrupt */
292 wait_queue_head_t swi_queue;
293 atomic_t swi_emitted;
294 int vblank_crtc;
295 uint32_t irq_enable_reg;
296 int irq_enabled;
297
298 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
299 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
300
301 unsigned long pcigart_offset;
302 unsigned int pcigart_offset_set;
303 struct drm_ati_pcigart_info gart_info;
304
305 u32 scratch_ages[5];
306
307 /* starting from here on, data is preserved accross an open */
308 uint32_t flags; /* see radeon_chip_flags */
309 unsigned long fb_aper_offset;
310 } drm_radeon_private_t;
311
312 typedef struct drm_radeon_buf_priv {
313 u32 age;
314 } drm_radeon_buf_priv_t;
315
316 typedef struct drm_radeon_kcmd_buffer {
317 int bufsz;
318 char *buf;
319 int nbox;
320 struct drm_clip_rect __user *boxes;
321 } drm_radeon_kcmd_buffer_t;
322
323 extern int radeon_no_wb;
324 extern struct drm_ioctl_desc radeon_ioctls[];
325 extern int radeon_max_ioctl;
326
327 /* Check whether the given hardware address is inside the framebuffer or the
328 * GART area.
329 */
330 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
331 u64 off)
332 {
333 u32 fb_start = dev_priv->fb_location;
334 u32 fb_end = fb_start + dev_priv->fb_size - 1;
335 u32 gart_start = dev_priv->gart_vm_start;
336 u32 gart_end = gart_start + dev_priv->gart_size - 1;
337
338 return ((off >= fb_start && off <= fb_end) ||
339 (off >= gart_start && off <= gart_end));
340 }
341
342 /* radeon_cp.c */
343 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
344 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
345 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
346 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
347 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
348 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
349 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
350 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
351 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
352 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
353
354 extern void radeon_freelist_reset(struct drm_device * dev);
355 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
356
357 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
358
359 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
360
361 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
362 extern int radeon_presetup(struct drm_device *dev);
363 extern int radeon_driver_postcleanup(struct drm_device *dev);
364
365 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
366 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
367 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
368 extern void radeon_mem_takedown(struct mem_block **heap);
369 extern void radeon_mem_release(struct drm_file *file_priv,
370 struct mem_block *heap);
371
372 /* radeon_irq.c */
373 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
374 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
375
376 extern void radeon_do_release(struct drm_device * dev);
377 extern int radeon_driver_vblank_wait(struct drm_device * dev,
378 unsigned int *sequence);
379 extern int radeon_driver_vblank_wait2(struct drm_device * dev,
380 unsigned int *sequence);
381 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
382 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
383 extern void radeon_driver_irq_postinstall(struct drm_device * dev);
384 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
385 extern int radeon_vblank_crtc_get(struct drm_device *dev);
386 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
387
388 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
389 extern int radeon_driver_unload(struct drm_device *dev);
390 extern int radeon_driver_firstopen(struct drm_device *dev);
391 extern void radeon_driver_preclose(struct drm_device * dev, struct drm_file *file_priv);
392 extern void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp);
393 extern void radeon_driver_lastclose(struct drm_device * dev);
394 extern int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv);
395 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
396 unsigned long arg);
397
398 /* r300_cmdbuf.c */
399 extern void r300_init_reg_flags(struct drm_device *dev);
400
401 extern int r300_do_cp_cmdbuf(struct drm_device * dev,
402 struct drm_file *file_priv,
403 drm_radeon_kcmd_buffer_t * cmdbuf);
404
405 /* Flags for stats.boxes
406 */
407 #define RADEON_BOX_DMA_IDLE 0x1
408 #define RADEON_BOX_RING_FULL 0x2
409 #define RADEON_BOX_FLIP 0x4
410 #define RADEON_BOX_WAIT_IDLE 0x8
411 #define RADEON_BOX_TEXTURE_LOAD 0x10
412
413 /* Register definitions, register access macros and drmAddMap constants
414 * for Radeon kernel driver.
415 */
416
417 #define RADEON_AGP_COMMAND 0x0f60
418 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
419 # define RADEON_AGP_ENABLE (1<<8)
420 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
421 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
422 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
423 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
424 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
425 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
426 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
427
428 #define RADEON_BUS_CNTL 0x0030
429 # define RADEON_BUS_MASTER_DIS (1 << 6)
430
431 #define RADEON_CLOCK_CNTL_DATA 0x000c
432 # define RADEON_PLL_WR_EN (1 << 7)
433 #define RADEON_CLOCK_CNTL_INDEX 0x0008
434 #define RADEON_CONFIG_APER_SIZE 0x0108
435 #define RADEON_CONFIG_MEMSIZE 0x00f8
436 #define RADEON_CRTC_OFFSET 0x0224
437 #define RADEON_CRTC_OFFSET_CNTL 0x0228
438 # define RADEON_CRTC_TILE_EN (1 << 15)
439 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
440 #define RADEON_CRTC2_OFFSET 0x0324
441 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
442
443 #define RADEON_PCIE_INDEX 0x0030
444 #define RADEON_PCIE_DATA 0x0034
445 #define RADEON_PCIE_TX_GART_CNTL 0x10
446 # define RADEON_PCIE_TX_GART_EN (1 << 0)
447 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
448 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
449 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
450 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
451 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
452 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
453 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
454 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
455 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
456 #define RADEON_PCIE_TX_GART_BASE 0x13
457 #define RADEON_PCIE_TX_GART_START_LO 0x14
458 #define RADEON_PCIE_TX_GART_START_HI 0x15
459 #define RADEON_PCIE_TX_GART_END_LO 0x16
460 #define RADEON_PCIE_TX_GART_END_HI 0x17
461
462 #define RADEON_IGPGART_INDEX 0x168
463 #define RADEON_IGPGART_DATA 0x16c
464 #define RADEON_IGPGART_UNK_18 0x18
465 #define RADEON_IGPGART_CTRL 0x2b
466 #define RADEON_IGPGART_BASE_ADDR 0x2c
467 #define RADEON_IGPGART_FLUSH 0x2e
468 #define RADEON_IGPGART_ENABLE 0x38
469 #define RADEON_IGPGART_UNK_39 0x39
470
471 #define RS690_MC_INDEX 0x78
472 # define RS690_MC_INDEX_MASK 0x1ff
473 # define RS690_MC_INDEX_WR_EN (1 << 9)
474 # define RS690_MC_INDEX_WR_ACK 0x7f
475 #define RS690_MC_DATA 0x7c
476
477 #define RS690_MC_MISC_CNTL 0x18
478 #define RS690_MC_GART_FEATURE_ID 0x2b
479 #define RS690_MC_GART_BASE 0x2c
480 #define RS690_MC_GART_CACHE_CNTL 0x2e
481 # define RS690_MC_GART_CC_NO_CHANGE 0x0
482 # define RS690_MC_GART_CC_CLEAR 0x1
483 # define RS690_MC_GART_CLEAR_STATUS (1 << 1)
484 # define RS690_MC_GART_CLEAR_DONE (0 << 1)
485 # define RS690_MC_GART_CLEAR_PENDING (1 << 1)
486 #define RS690_MC_AGP_SIZE 0x38
487 # define RS690_MC_GART_DIS 0x0
488 # define RS690_MC_GART_EN 0x1
489 # define RS690_MC_AGP_SIZE_32MB (0 << 1)
490 # define RS690_MC_AGP_SIZE_64MB (1 << 1)
491 # define RS690_MC_AGP_SIZE_128MB (2 << 1)
492 # define RS690_MC_AGP_SIZE_256MB (3 << 1)
493 # define RS690_MC_AGP_SIZE_512MB (4 << 1)
494 # define RS690_MC_AGP_SIZE_1GB (5 << 1)
495 # define RS690_MC_AGP_SIZE_2GB (6 << 1)
496 #define RS690_MC_AGP_MODE_CONTROL 0x39
497 #define RS690_MC_FB_LOCATION 0x100
498 #define RS690_MC_AGP_LOCATION 0x101
499 #define RS690_MC_AGP_BASE 0x102
500
501 #define R520_MC_IND_INDEX 0x70
502 #define R520_MC_IND_WR_EN (1<<24)
503 #define R520_MC_IND_DATA 0x74
504
505 #define RV515_MC_FB_LOCATION 0x01
506 #define RV515_MC_AGP_LOCATION 0x02
507
508 #define R520_MC_FB_LOCATION 0x04
509 #define R520_MC_AGP_LOCATION 0x05
510
511 #define RADEON_MPP_TB_CONFIG 0x01c0
512 #define RADEON_MEM_CNTL 0x0140
513 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
514 #define RADEON_AGP_BASE 0x0170
515
516 #define RADEON_RB3D_COLOROFFSET 0x1c40
517 #define RADEON_RB3D_COLORPITCH 0x1c48
518
519 #define RADEON_SRC_X_Y 0x1590
520
521 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
522 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
523 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
524 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
525 # define RADEON_GMC_BRUSH_NONE (15 << 4)
526 # define RADEON_GMC_DST_16BPP (4 << 8)
527 # define RADEON_GMC_DST_24BPP (5 << 8)
528 # define RADEON_GMC_DST_32BPP (6 << 8)
529 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
530 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
531 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
532 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
533 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
534 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
535 # define RADEON_ROP3_S 0x00cc0000
536 # define RADEON_ROP3_P 0x00f00000
537 #define RADEON_DP_WRITE_MASK 0x16cc
538 #define RADEON_SRC_PITCH_OFFSET 0x1428
539 #define RADEON_DST_PITCH_OFFSET 0x142c
540 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
541 # define RADEON_DST_TILE_LINEAR (0 << 30)
542 # define RADEON_DST_TILE_MACRO (1 << 30)
543 # define RADEON_DST_TILE_MICRO (2 << 30)
544 # define RADEON_DST_TILE_BOTH (3 << 30)
545
546 #define RADEON_SCRATCH_REG0 0x15e0
547 #define RADEON_SCRATCH_REG1 0x15e4
548 #define RADEON_SCRATCH_REG2 0x15e8
549 #define RADEON_SCRATCH_REG3 0x15ec
550 #define RADEON_SCRATCH_REG4 0x15f0
551 #define RADEON_SCRATCH_REG5 0x15f4
552 #define RADEON_SCRATCH_UMSK 0x0770
553 #define RADEON_SCRATCH_ADDR 0x0774
554
555 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
556
557 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
558 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
559 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
560
561 #define RADEON_GEN_INT_CNTL 0x0040
562 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
563 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
564 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
565 # define RADEON_SW_INT_ENABLE (1 << 25)
566
567 #define RADEON_GEN_INT_STATUS 0x0044
568 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
569 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
570 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
571 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
572 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
573 # define RADEON_SW_INT_TEST (1 << 25)
574 # define RADEON_SW_INT_TEST_ACK (1 << 25)
575 # define RADEON_SW_INT_FIRE (1 << 26)
576
577 #define RADEON_HOST_PATH_CNTL 0x0130
578 # define RADEON_HDP_SOFT_RESET (1 << 26)
579 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
580 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
581
582 #define RADEON_ISYNC_CNTL 0x1724
583 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
584 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
585 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
586 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
587 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
588 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
589
590 #define RADEON_RBBM_GUICNTL 0x172c
591 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
592 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
593 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
594 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
595
596 #define RADEON_MC_AGP_LOCATION 0x014c
597 #define RADEON_MC_FB_LOCATION 0x0148
598 #define RADEON_MCLK_CNTL 0x0012
599 # define RADEON_FORCEON_MCLKA (1 << 16)
600 # define RADEON_FORCEON_MCLKB (1 << 17)
601 # define RADEON_FORCEON_YCLKA (1 << 18)
602 # define RADEON_FORCEON_YCLKB (1 << 19)
603 # define RADEON_FORCEON_MC (1 << 20)
604 # define RADEON_FORCEON_AIC (1 << 21)
605
606 #define RADEON_PP_BORDER_COLOR_0 0x1d40
607 #define RADEON_PP_BORDER_COLOR_1 0x1d44
608 #define RADEON_PP_BORDER_COLOR_2 0x1d48
609 #define RADEON_PP_CNTL 0x1c38
610 # define RADEON_SCISSOR_ENABLE (1 << 1)
611 #define RADEON_PP_LUM_MATRIX 0x1d00
612 #define RADEON_PP_MISC 0x1c14
613 #define RADEON_PP_ROT_MATRIX_0 0x1d58
614 #define RADEON_PP_TXFILTER_0 0x1c54
615 #define RADEON_PP_TXOFFSET_0 0x1c5c
616 #define RADEON_PP_TXFILTER_1 0x1c6c
617 #define RADEON_PP_TXFILTER_2 0x1c84
618
619 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
620 # define RADEON_RB2D_DC_FLUSH (3 << 0)
621 # define RADEON_RB2D_DC_FREE (3 << 2)
622 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
623 # define RADEON_RB2D_DC_BUSY (1 << 31)
624 #define RADEON_RB3D_CNTL 0x1c3c
625 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
626 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
627 # define RADEON_DITHER_ENABLE (1 << 2)
628 # define RADEON_ROUND_ENABLE (1 << 3)
629 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
630 # define RADEON_DITHER_INIT (1 << 5)
631 # define RADEON_ROP_ENABLE (1 << 6)
632 # define RADEON_STENCIL_ENABLE (1 << 7)
633 # define RADEON_Z_ENABLE (1 << 8)
634 # define RADEON_ZBLOCK16 (1 << 15)
635 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
636 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
637 #define RADEON_RB3D_DEPTHPITCH 0x1c28
638 #define RADEON_RB3D_PLANEMASK 0x1d84
639 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
640 #define RADEON_RB3D_ZCACHE_MODE 0x3250
641 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
642 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
643 # define RADEON_RB3D_ZC_FREE (1 << 2)
644 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
645 # define RADEON_RB3D_ZC_BUSY (1 << 31)
646 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
647 # define RADEON_RB3D_DC_FLUSH (3 << 0)
648 # define RADEON_RB3D_DC_FREE (3 << 2)
649 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
650 # define RADEON_RB3D_DC_BUSY (1 << 31)
651 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
652 # define RADEON_Z_TEST_MASK (7 << 4)
653 # define RADEON_Z_TEST_ALWAYS (7 << 4)
654 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
655 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
656 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
657 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
658 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
659 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
660 # define RADEON_FORCE_Z_DIRTY (1 << 29)
661 # define RADEON_Z_WRITE_ENABLE (1 << 30)
662 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
663 #define RADEON_RBBM_SOFT_RESET 0x00f0
664 # define RADEON_SOFT_RESET_CP (1 << 0)
665 # define RADEON_SOFT_RESET_HI (1 << 1)
666 # define RADEON_SOFT_RESET_SE (1 << 2)
667 # define RADEON_SOFT_RESET_RE (1 << 3)
668 # define RADEON_SOFT_RESET_PP (1 << 4)
669 # define RADEON_SOFT_RESET_E2 (1 << 5)
670 # define RADEON_SOFT_RESET_RB (1 << 6)
671 # define RADEON_SOFT_RESET_HDP (1 << 7)
672 /*
673 * 6:0 Available slots in the FIFO
674 * 8 Host Interface active
675 * 9 CP request active
676 * 10 FIFO request active
677 * 11 Host Interface retry active
678 * 12 CP retry active
679 * 13 FIFO retry active
680 * 14 FIFO pipeline busy
681 * 15 Event engine busy
682 * 16 CP command stream busy
683 * 17 2D engine busy
684 * 18 2D portion of render backend busy
685 * 20 3D setup engine busy
686 * 26 GA engine busy
687 * 27 CBA 2D engine busy
688 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
689 * command stream queue not empty or Ring Buffer not empty
690 */
691 #define RADEON_RBBM_STATUS 0x0e40
692 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
693 /* #define RADEON_RBBM_STATUS 0x1740 */
694 /* bits 6:0 are dword slots available in the cmd fifo */
695 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
696 # define RADEON_HIRQ_ON_RBB (1 << 8)
697 # define RADEON_CPRQ_ON_RBB (1 << 9)
698 # define RADEON_CFRQ_ON_RBB (1 << 10)
699 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
700 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
701 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
702 # define RADEON_PIPE_BUSY (1 << 14)
703 # define RADEON_ENG_EV_BUSY (1 << 15)
704 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
705 # define RADEON_E2_BUSY (1 << 17)
706 # define RADEON_RB2D_BUSY (1 << 18)
707 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
708 # define RADEON_VAP_BUSY (1 << 20)
709 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
710 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
711 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
712 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
713 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
714 # define RADEON_GA_BUSY (1 << 26)
715 # define RADEON_CBA2D_BUSY (1 << 27)
716 # define RADEON_RBBM_ACTIVE (1 << 31)
717 #define RADEON_RE_LINE_PATTERN 0x1cd0
718 #define RADEON_RE_MISC 0x26c4
719 #define RADEON_RE_TOP_LEFT 0x26c0
720 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
721 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
722 #define RADEON_RE_STIPPLE_DATA 0x1ccc
723
724 #define RADEON_SCISSOR_TL_0 0x1cd8
725 #define RADEON_SCISSOR_BR_0 0x1cdc
726 #define RADEON_SCISSOR_TL_1 0x1ce0
727 #define RADEON_SCISSOR_BR_1 0x1ce4
728 #define RADEON_SCISSOR_TL_2 0x1ce8
729 #define RADEON_SCISSOR_BR_2 0x1cec
730 #define RADEON_SE_COORD_FMT 0x1c50
731 #define RADEON_SE_CNTL 0x1c4c
732 # define RADEON_FFACE_CULL_CW (0 << 0)
733 # define RADEON_BFACE_SOLID (3 << 1)
734 # define RADEON_FFACE_SOLID (3 << 3)
735 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
736 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
737 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
738 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
739 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
740 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
741 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
742 # define RADEON_FOG_SHADE_FLAT (1 << 14)
743 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
744 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
745 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
746 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
747 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
748 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
749 #define RADEON_SE_CNTL_STATUS 0x2140
750 #define RADEON_SE_LINE_WIDTH 0x1db8
751 #define RADEON_SE_VPORT_XSCALE 0x1d98
752 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
753 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
754 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
755 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
756 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
757 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
758 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
759 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
760 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
761 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
762 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
763 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
764 #define RADEON_SURFACE_CNTL 0x0b00
765 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
766 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
767 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
768 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
769 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
770 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
771 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
772 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
773 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
774 #define RADEON_SURFACE0_INFO 0x0b0c
775 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
776 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
777 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
778 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
779 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
780 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
781 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
782 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
783 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
784 #define RADEON_SURFACE1_INFO 0x0b1c
785 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
786 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
787 #define RADEON_SURFACE2_INFO 0x0b2c
788 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
789 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
790 #define RADEON_SURFACE3_INFO 0x0b3c
791 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
792 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
793 #define RADEON_SURFACE4_INFO 0x0b4c
794 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
795 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
796 #define RADEON_SURFACE5_INFO 0x0b5c
797 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
798 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
799 #define RADEON_SURFACE6_INFO 0x0b6c
800 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
801 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
802 #define RADEON_SURFACE7_INFO 0x0b7c
803 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
804 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
805 #define RADEON_SW_SEMAPHORE 0x013c
806
807 #define RADEON_WAIT_UNTIL 0x1720
808 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
809 # define RADEON_WAIT_2D_IDLE (1 << 14)
810 # define RADEON_WAIT_3D_IDLE (1 << 15)
811 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
812 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
813 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
814
815 #define RADEON_RB3D_ZMASKOFFSET 0x3234
816 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
817 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
818 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
819
820 /* CP registers */
821 #define RADEON_CP_ME_RAM_ADDR 0x07d4
822 #define RADEON_CP_ME_RAM_RADDR 0x07d8
823 #define RADEON_CP_ME_RAM_DATAH 0x07dc
824 #define RADEON_CP_ME_RAM_DATAL 0x07e0
825
826 #define RADEON_CP_RB_BASE 0x0700
827 #define RADEON_CP_RB_CNTL 0x0704
828 # define RADEON_BUF_SWAP_32BIT (2 << 16)
829 # define RADEON_RB_NO_UPDATE (1 << 27)
830 #define RADEON_CP_RB_RPTR_ADDR 0x070c
831 #define RADEON_CP_RB_RPTR 0x0710
832 #define RADEON_CP_RB_WPTR 0x0714
833
834 #define RADEON_CP_RB_WPTR_DELAY 0x0718
835 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
836 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
837
838 #define RADEON_CP_IB_BASE 0x0738
839
840 #define RADEON_CP_CSQ_CNTL 0x0740
841 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
842 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
843 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
844 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
845 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
846 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
847 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
848
849 #define RADEON_AIC_CNTL 0x01d0
850 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
851 #define RADEON_AIC_STAT 0x01d4
852 #define RADEON_AIC_PT_BASE 0x01d8
853 #define RADEON_AIC_LO_ADDR 0x01dc
854 #define RADEON_AIC_HI_ADDR 0x01e0
855 #define RADEON_AIC_TLB_ADDR 0x01e4
856 #define RADEON_AIC_TLB_DATA 0x01e8
857
858 /* CP command packets */
859 #define RADEON_CP_PACKET0 0x00000000
860 # define RADEON_ONE_REG_WR (1 << 15)
861 #define RADEON_CP_PACKET1 0x40000000
862 #define RADEON_CP_PACKET2 0x80000000
863 #define RADEON_CP_PACKET3 0xC0000000
864 # define RADEON_CP_NOP 0x00001000
865 # define RADEON_CP_NEXT_CHAR 0x00001900
866 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
867 # define RADEON_CP_SET_SCISSORS 0x00001E00
868 /* GEN_INDX_PRIM is unsupported starting with R300 */
869 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
870 # define RADEON_WAIT_FOR_IDLE 0x00002600
871 # define RADEON_3D_DRAW_VBUF 0x00002800
872 # define RADEON_3D_DRAW_IMMD 0x00002900
873 # define RADEON_3D_DRAW_INDX 0x00002A00
874 # define RADEON_CP_LOAD_PALETTE 0x00002C00
875 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
876 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
877 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
878 # define RADEON_3D_CLEAR_ZMASK 0x00003200
879 # define RADEON_CP_INDX_BUFFER 0x00003300
880 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
881 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
882 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
883 # define RADEON_3D_CLEAR_HIZ 0x00003700
884 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
885 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
886 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
887 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
888 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
889
890 #define RADEON_CP_PACKET_MASK 0xC0000000
891 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
892 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
893 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
894 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
895
896 #define RADEON_VTX_Z_PRESENT (1 << 31)
897 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
898
899 #define RADEON_PRIM_TYPE_NONE (0 << 0)
900 #define RADEON_PRIM_TYPE_POINT (1 << 0)
901 #define RADEON_PRIM_TYPE_LINE (2 << 0)
902 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
903 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
904 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
905 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
906 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
907 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
908 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
909 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
910 #define RADEON_PRIM_TYPE_MASK 0xf
911 #define RADEON_PRIM_WALK_IND (1 << 4)
912 #define RADEON_PRIM_WALK_LIST (2 << 4)
913 #define RADEON_PRIM_WALK_RING (3 << 4)
914 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
915 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
916 #define RADEON_MAOS_ENABLE (1 << 7)
917 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
918 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
919 #define RADEON_NUM_VERTICES_SHIFT 16
920
921 #define RADEON_COLOR_FORMAT_CI8 2
922 #define RADEON_COLOR_FORMAT_ARGB1555 3
923 #define RADEON_COLOR_FORMAT_RGB565 4
924 #define RADEON_COLOR_FORMAT_ARGB8888 6
925 #define RADEON_COLOR_FORMAT_RGB332 7
926 #define RADEON_COLOR_FORMAT_RGB8 9
927 #define RADEON_COLOR_FORMAT_ARGB4444 15
928
929 #define RADEON_TXFORMAT_I8 0
930 #define RADEON_TXFORMAT_AI88 1
931 #define RADEON_TXFORMAT_RGB332 2
932 #define RADEON_TXFORMAT_ARGB1555 3
933 #define RADEON_TXFORMAT_RGB565 4
934 #define RADEON_TXFORMAT_ARGB4444 5
935 #define RADEON_TXFORMAT_ARGB8888 6
936 #define RADEON_TXFORMAT_RGBA8888 7
937 #define RADEON_TXFORMAT_Y8 8
938 #define RADEON_TXFORMAT_VYUY422 10
939 #define RADEON_TXFORMAT_YVYU422 11
940 #define RADEON_TXFORMAT_DXT1 12
941 #define RADEON_TXFORMAT_DXT23 14
942 #define RADEON_TXFORMAT_DXT45 15
943
944 #define R200_PP_TXCBLEND_0 0x2f00
945 #define R200_PP_TXCBLEND_1 0x2f10
946 #define R200_PP_TXCBLEND_2 0x2f20
947 #define R200_PP_TXCBLEND_3 0x2f30
948 #define R200_PP_TXCBLEND_4 0x2f40
949 #define R200_PP_TXCBLEND_5 0x2f50
950 #define R200_PP_TXCBLEND_6 0x2f60
951 #define R200_PP_TXCBLEND_7 0x2f70
952 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
953 #define R200_PP_TFACTOR_0 0x2ee0
954 #define R200_SE_VTX_FMT_0 0x2088
955 #define R200_SE_VAP_CNTL 0x2080
956 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
957 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
958 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
959 #define R200_PP_TXFILTER_5 0x2ca0
960 #define R200_PP_TXFILTER_4 0x2c80
961 #define R200_PP_TXFILTER_3 0x2c60
962 #define R200_PP_TXFILTER_2 0x2c40
963 #define R200_PP_TXFILTER_1 0x2c20
964 #define R200_PP_TXFILTER_0 0x2c00
965 #define R200_PP_TXOFFSET_5 0x2d78
966 #define R200_PP_TXOFFSET_4 0x2d60
967 #define R200_PP_TXOFFSET_3 0x2d48
968 #define R200_PP_TXOFFSET_2 0x2d30
969 #define R200_PP_TXOFFSET_1 0x2d18
970 #define R200_PP_TXOFFSET_0 0x2d00
971
972 #define R200_PP_CUBIC_FACES_0 0x2c18
973 #define R200_PP_CUBIC_FACES_1 0x2c38
974 #define R200_PP_CUBIC_FACES_2 0x2c58
975 #define R200_PP_CUBIC_FACES_3 0x2c78
976 #define R200_PP_CUBIC_FACES_4 0x2c98
977 #define R200_PP_CUBIC_FACES_5 0x2cb8
978 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
979 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
980 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
981 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
982 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
983 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
984 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
985 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
986 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
987 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
988 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
989 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
990 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
991 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
992 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
993 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
994 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
995 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
996 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
997 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
998 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
999 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1000 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1001 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1002 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1003 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1004 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1005 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1006 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1007 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1008
1009 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1010 #define R200_SE_VTE_CNTL 0x20b0
1011 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1012 #define R200_PP_TAM_DEBUG3 0x2d9c
1013 #define R200_PP_CNTL_X 0x2cc4
1014 #define R200_SE_VAP_CNTL_STATUS 0x2140
1015 #define R200_RE_SCISSOR_TL_0 0x1cd8
1016 #define R200_RE_SCISSOR_TL_1 0x1ce0
1017 #define R200_RE_SCISSOR_TL_2 0x1ce8
1018 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1019 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1020 #define R200_SE_VTX_STATE_CNTL 0x2180
1021 #define R200_RE_POINTSIZE 0x2648
1022 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1023
1024 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1025 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1026 #define RADEON_PP_TEX_SIZE_2 0x1d14
1027
1028 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1029 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1030 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1031 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1032 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1033 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1034
1035 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1036
1037 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1038 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1039 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1040 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1041 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1042 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1043 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1044 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1045 #define R200_3D_DRAW_IMMD_2 0xC0003500
1046 #define R200_SE_VTX_FMT_1 0x208c
1047 #define R200_RE_CNTL 0x1c50
1048
1049 #define R200_RB3D_BLENDCOLOR 0x3218
1050
1051 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1052
1053 #define R200_PP_TRI_PERF 0x2cf8
1054
1055 #define R200_PP_AFS_0 0x2f80
1056 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1057
1058 #define R200_VAP_PVS_CNTL_1 0x22D0
1059
1060 /* Constants */
1061 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1062
1063 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1064 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1065 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1066 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1067 #define RADEON_LAST_DISPATCH 1
1068
1069 #define RADEON_MAX_VB_AGE 0x7fffffff
1070 #define RADEON_MAX_VB_VERTS (0xffff)
1071
1072 #define RADEON_RING_HIGH_MARK 128
1073
1074 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1075
1076 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1077 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1078 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1079 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1080
1081 #define RADEON_WRITE_PLL( addr, val ) \
1082 do { \
1083 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
1084 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1085 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
1086 } while (0)
1087
1088 #define RADEON_WRITE_IGPGART( addr, val ) \
1089 do { \
1090 RADEON_WRITE( RADEON_IGPGART_INDEX, \
1091 ((addr) & 0x7f) | (1 << 8)); \
1092 RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \
1093 RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
1094 } while (0)
1095
1096 #define RADEON_WRITE_PCIE( addr, val ) \
1097 do { \
1098 RADEON_WRITE8( RADEON_PCIE_INDEX, \
1099 ((addr) & 0xff)); \
1100 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
1101 } while (0)
1102
1103 #define RADEON_WRITE_MCIND( addr, val ) \
1104 do { \
1105 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1106 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1107 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1108 } while (0)
1109
1110 #define RS690_WRITE_MCIND( addr, val ) \
1111 do { \
1112 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1113 RADEON_WRITE(RS690_MC_DATA, val); \
1114 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1115 } while (0)
1116
1117 #define CP_PACKET0( reg, n ) \
1118 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1119 #define CP_PACKET0_TABLE( reg, n ) \
1120 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1121 #define CP_PACKET1( reg0, reg1 ) \
1122 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1123 #define CP_PACKET2() \
1124 (RADEON_CP_PACKET2)
1125 #define CP_PACKET3( pkt, n ) \
1126 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1127
1128 /* ================================================================
1129 * Engine control helper macros
1130 */
1131
1132 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1133 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1134 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1135 RADEON_WAIT_HOST_IDLECLEAN) ); \
1136 } while (0)
1137
1138 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1139 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1140 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1141 RADEON_WAIT_HOST_IDLECLEAN) ); \
1142 } while (0)
1143
1144 #define RADEON_WAIT_UNTIL_IDLE() do { \
1145 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1146 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1147 RADEON_WAIT_3D_IDLECLEAN | \
1148 RADEON_WAIT_HOST_IDLECLEAN) ); \
1149 } while (0)
1150
1151 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1152 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1153 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1154 } while (0)
1155
1156 #define RADEON_FLUSH_CACHE() do { \
1157 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1158 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
1159 } while (0)
1160
1161 #define RADEON_PURGE_CACHE() do { \
1162 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1163 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
1164 } while (0)
1165
1166 #define RADEON_FLUSH_ZCACHE() do { \
1167 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1168 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1169 } while (0)
1170
1171 #define RADEON_PURGE_ZCACHE() do { \
1172 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1173 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1174 } while (0)
1175
1176 /* ================================================================
1177 * Misc helper macros
1178 */
1179
1180 /* Perfbox functionality only.
1181 */
1182 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1183 do { \
1184 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1185 u32 head = GET_RING_HEAD( dev_priv ); \
1186 if (head == dev_priv->ring.tail) \
1187 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1188 } \
1189 } while (0)
1190
1191 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1192 do { \
1193 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1194 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1195 int __ret = radeon_do_cp_idle( dev_priv ); \
1196 if ( __ret ) return __ret; \
1197 sarea_priv->last_dispatch = 0; \
1198 radeon_freelist_reset( dev ); \
1199 } \
1200 } while (0)
1201
1202 #define RADEON_DISPATCH_AGE( age ) do { \
1203 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1204 OUT_RING( age ); \
1205 } while (0)
1206
1207 #define RADEON_FRAME_AGE( age ) do { \
1208 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1209 OUT_RING( age ); \
1210 } while (0)
1211
1212 #define RADEON_CLEAR_AGE( age ) do { \
1213 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1214 OUT_RING( age ); \
1215 } while (0)
1216
1217 /* ================================================================
1218 * Ring control
1219 */
1220
1221 #define RADEON_VERBOSE 0
1222
1223 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1224
1225 #define BEGIN_RING( n ) do { \
1226 if ( RADEON_VERBOSE ) { \
1227 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1228 } \
1229 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1230 COMMIT_RING(); \
1231 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1232 } \
1233 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1234 ring = dev_priv->ring.start; \
1235 write = dev_priv->ring.tail; \
1236 mask = dev_priv->ring.tail_mask; \
1237 } while (0)
1238
1239 #define ADVANCE_RING() do { \
1240 if ( RADEON_VERBOSE ) { \
1241 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1242 write, dev_priv->ring.tail ); \
1243 } \
1244 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1245 DRM_ERROR( \
1246 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1247 ((dev_priv->ring.tail + _nr) & mask), \
1248 write, __LINE__); \
1249 } else \
1250 dev_priv->ring.tail = write; \
1251 } while (0)
1252
1253 #define COMMIT_RING() do { \
1254 /* Flush writes to ring */ \
1255 DRM_MEMORYBARRIER(); \
1256 GET_RING_HEAD( dev_priv ); \
1257 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1258 /* read from PCI bus to ensure correct posting */ \
1259 RADEON_READ( RADEON_CP_RB_RPTR ); \
1260 } while (0)
1261
1262 #define OUT_RING( x ) do { \
1263 if ( RADEON_VERBOSE ) { \
1264 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1265 (unsigned int)(x), write ); \
1266 } \
1267 ring[write++] = (x); \
1268 write &= mask; \
1269 } while (0)
1270
1271 #define OUT_RING_REG( reg, val ) do { \
1272 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1273 OUT_RING( val ); \
1274 } while (0)
1275
1276 #define OUT_RING_TABLE( tab, sz ) do { \
1277 int _size = (sz); \
1278 int *_tab = (int *)(tab); \
1279 \
1280 if (write + _size > mask) { \
1281 int _i = (mask+1) - write; \
1282 _size -= _i; \
1283 while (_i > 0 ) { \
1284 *(int *)(ring + write) = *_tab++; \
1285 write++; \
1286 _i--; \
1287 } \
1288 write = 0; \
1289 _tab += _i; \
1290 } \
1291 while (_size > 0) { \
1292 *(ring + write) = *_tab++; \
1293 write++; \
1294 _size--; \
1295 } \
1296 write &= mask; \
1297 } while (0)
1298
1299 #endif /* __RADEON_DRV_H__ */
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