drivers/char/agp/parisc-agp.c

   1 /*
   2  * HP Quicksilver AGP GART routines
   3  *
   4  * Copyright (c) 2006, Kyle McMartin <kyle@parisc-linux.org>
   5  *
   6  * Based on drivers/char/agpgart/hp-agp.c which is
   7  * (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P.
   8  *      Bjorn Helgaas <bjorn.helgaas@hp.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/klist.h>
  20 #include <linux/agp_backend.h>
  21 #include <linux/log2.h>
  22
  23 #include <asm-parisc/parisc-device.h>
  24 #include <asm-parisc/ropes.h>
  25
  26 #include "agp.h"
  27
  28 #define DRVNAME "quicksilver"
  29 #define DRVPFX  DRVNAME ": "
  30
  31 #define AGP8X_MODE_BIT          3
  32 #define AGP8X_MODE              (1 << AGP8X_MODE_BIT)
  33
  34 static struct _parisc_agp_info {
  35         void __iomem *ioc_regs;
  36         void __iomem *lba_regs;
  37
  38         int lba_cap_offset;
  39
  40         u64 *gatt;
  41         u64 gatt_entries;
  42
  43         u64 gart_base;
  44         u64 gart_size;
  45
  46         int io_page_size;
  47         int io_pages_per_kpage;
  48 } parisc_agp_info;
  49
  50 static struct gatt_mask parisc_agp_masks[] =
  51 {
  52         {
  53                 .mask = SBA_PDIR_VALID_BIT,
  54                 .type = 0
  55         }
  56 };
  57
  58 static struct aper_size_info_fixed parisc_agp_sizes[] =
  59 {
  60         {0, 0, 0},              /* filled in by parisc_agp_fetch_size() */
  61 };
  62
  63 static int
  64 parisc_agp_fetch_size(void)
  65 {
  66         int size;
  67
  68         size = parisc_agp_info.gart_size / MB(1);
  69         parisc_agp_sizes[0].size = size;
  70         agp_bridge->current_size = (void *) &parisc_agp_sizes[0];
  71
  72         return size;
  73 }
  74
  75 static int
  76 parisc_agp_configure(void)
  77 {
  78         struct _parisc_agp_info *info = &parisc_agp_info;
  79
  80         agp_bridge->gart_bus_addr = info->gart_base;
  81         agp_bridge->capndx = info->lba_cap_offset;
  82         agp_bridge->mode = readl(info->lba_regs+info->lba_cap_offset+PCI_AGP_STATUS);
  83
  84         return 0;
  85 }
  86
  87 static void
  88 parisc_agp_tlbflush(struct agp_memory *mem)
  89 {
  90         struct _parisc_agp_info *info = &parisc_agp_info;
  91
  92         writeq(info->gart_base | ilog2(info->gart_size), info->ioc_regs+IOC_PCOM);
  93         readq(info->ioc_regs+IOC_PCOM); /* flush */
  94 }
  95
  96 static int
  97 parisc_agp_create_gatt_table(struct agp_bridge_data *bridge)
  98 {
  99         struct _parisc_agp_info *info = &parisc_agp_info;
 100         int i;
 101
 102         for (i = 0; i < info->gatt_entries; i++) {
 103                 info->gatt[i] = (unsigned long)agp_bridge->scratch_page;
 104         }
 105
 106         return 0;
 107 }
 108
 109 static int
 110 parisc_agp_free_gatt_table(struct agp_bridge_data *bridge)
 111 {
 112         struct _parisc_agp_info *info = &parisc_agp_info;
 113
 114         info->gatt[0] = SBA_AGPGART_COOKIE;
 115
 116         return 0;
 117 }
 118
 119 static int
 120 parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
 121 {
 122         struct _parisc_agp_info *info = &parisc_agp_info;
 123         int i, k;
 124         off_t j, io_pg_start;
 125         int io_pg_count;
 126
 127         if (type != 0 || mem->type != 0) {
 128                 return -EINVAL;
 129         }
 130
 131         io_pg_start = info->io_pages_per_kpage * pg_start;
 132         io_pg_count = info->io_pages_per_kpage * mem->page_count;
 133         if ((io_pg_start + io_pg_count) > info->gatt_entries) {
 134                 return -EINVAL;
 135         }
 136
 137         j = io_pg_start;
 138         while (j < (io_pg_start + io_pg_count)) {
 139                 if (info->gatt[j])
 140                         return -EBUSY;
 141                 j++;
 142         }
 143
 144         if (mem->is_flushed == FALSE) {
 145                 global_cache_flush();
 146                 mem->is_flushed = TRUE;
 147         }
 148
 149         for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
 150                 unsigned long paddr;
 151
 152                 paddr = mem->memory[i];
 153                 for (k = 0;
 154                      k < info->io_pages_per_kpage;
 155                      k++, j++, paddr += info->io_page_size) {
 156                         info->gatt[j] =
 157                                 agp_bridge->driver->mask_memory(agp_bridge,
 158                                         paddr, type);
 159                 }
 160         }
 161
 162         agp_bridge->driver->tlb_flush(mem);
 163
 164         return 0;
 165 }
 166
 167 static int
 168 parisc_agp_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
 169 {
 170         struct _parisc_agp_info *info = &parisc_agp_info;
 171         int i, io_pg_start, io_pg_count;
 172
 173         if (type != 0 || mem->type != 0) {
 174                 return -EINVAL;
 175         }
 176
 177         io_pg_start = info->io_pages_per_kpage * pg_start;
 178         io_pg_count = info->io_pages_per_kpage * mem->page_count;
 179         for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
 180                 info->gatt[i] = agp_bridge->scratch_page;
 181         }
 182
 183         agp_bridge->driver->tlb_flush(mem);
 184         return 0;
 185 }
 186
 187 static unsigned long
 188 parisc_agp_mask_memory(struct agp_bridge_data *bridge,
 189                     unsigned long addr, int type)
 190 {
 191         return SBA_PDIR_VALID_BIT | addr;
 192 }
 193
 194 static void
 195 parisc_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 196 {
 197         struct _parisc_agp_info *info = &parisc_agp_info;
 198         u32 command;
 199
 200         command = readl(info->lba_regs + info->lba_cap_offset + PCI_AGP_STATUS);
 201
 202         command = agp_collect_device_status(bridge, mode, command);
 203         command |= 0x00000100;
 204
 205         writel(command, info->lba_regs + info->lba_cap_offset + PCI_AGP_COMMAND);
 206
 207         agp_device_command(command, (mode & AGP8X_MODE) != 0);
 208 }
 209
 210 static const struct agp_bridge_driver parisc_agp_driver = {
 211         .owner                  = THIS_MODULE,
 212         .size_type              = FIXED_APER_SIZE,
 213         .configure              = parisc_agp_configure,
 214         .fetch_size             = parisc_agp_fetch_size,
 215         .tlb_flush              = parisc_agp_tlbflush,
 216         .mask_memory            = parisc_agp_mask_memory,
 217         .masks                  = parisc_agp_masks,
 218         .agp_enable             = parisc_agp_enable,
 219         .cache_flush            = global_cache_flush,
 220         .create_gatt_table      = parisc_agp_create_gatt_table,
 221         .free_gatt_table        = parisc_agp_free_gatt_table,
 222         .insert_memory          = parisc_agp_insert_memory,
 223         .remove_memory          = parisc_agp_remove_memory,
 224         .alloc_by_type          = agp_generic_alloc_by_type,
 225         .free_by_type           = agp_generic_free_by_type,
 226         .agp_alloc_page         = agp_generic_alloc_page,
 227         .agp_destroy_page       = agp_generic_destroy_page,
 228         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 229         .cant_use_aperture      = 1,
 230 };
 231
 232 static int __init
 233 agp_ioc_init(void __iomem *ioc_regs)
 234 {
 235         struct _parisc_agp_info *info = &parisc_agp_info;
 236         u64 iova_base, *io_pdir, io_tlb_ps;
 237         int io_tlb_shift;
 238
 239         printk(KERN_INFO DRVPFX "IO PDIR shared with sba_iommu\n");
 240
 241         info->ioc_regs = ioc_regs;
 242
 243         io_tlb_ps = readq(info->ioc_regs+IOC_TCNFG);
 244         switch (io_tlb_ps) {
 245         case 0: io_tlb_shift = 12; break;
 246         case 1: io_tlb_shift = 13; break;
 247         case 2: io_tlb_shift = 14; break;
 248         case 3: io_tlb_shift = 16; break;
 249         default:
 250                 printk(KERN_ERR DRVPFX "Invalid IOTLB page size "
 251                        "configuration 0x%llx\n", io_tlb_ps);
 252                 info->gatt = NULL;
 253                 info->gatt_entries = 0;
 254                 return -ENODEV;
 255         }
 256         info->io_page_size = 1 << io_tlb_shift;
 257         info->io_pages_per_kpage = PAGE_SIZE / info->io_page_size;
 258
 259         iova_base = readq(info->ioc_regs+IOC_IBASE) & ~0x1;
 260         info->gart_base = iova_base + PLUTO_IOVA_SIZE - PLUTO_GART_SIZE;
 261
 262         info->gart_size = PLUTO_GART_SIZE;
 263         info->gatt_entries = info->gart_size / info->io_page_size;
 264
 265         io_pdir = phys_to_virt(readq(info->ioc_regs+IOC_PDIR_BASE));
 266         info->gatt = &io_pdir[(PLUTO_IOVA_SIZE/2) >> PAGE_SHIFT];
 267
 268         if (info->gatt[0] != SBA_AGPGART_COOKIE) {
 269                 info->gatt = NULL;
 270                 info->gatt_entries = 0;
 271                 printk(KERN_ERR DRVPFX "No reserved IO PDIR entry found; "
 272                        "GART disabled\n");
 273                 return -ENODEV;
 274         }
 275
 276         return 0;
 277 }
 278
 279 static int
 280 lba_find_capability(int cap)
 281 {
 282         struct _parisc_agp_info *info = &parisc_agp_info;
 283         u16 status;
 284         u8 pos, id;
 285         int ttl = 48;
 286
 287         status = readw(info->lba_regs + PCI_STATUS);
 288         if (!(status & PCI_STATUS_CAP_LIST))
 289                 return 0;
 290         pos = readb(info->lba_regs + PCI_CAPABILITY_LIST);
 291         while (ttl-- && pos >= 0x40) {
 292                 pos &= ~3;
 293                 id = readb(info->lba_regs + pos + PCI_CAP_LIST_ID);
 294                 if (id == 0xff)
 295                         break;
 296                 if (id == cap)
 297                         return pos;
 298                 pos = readb(info->lba_regs + pos + PCI_CAP_LIST_NEXT);
 299         }
 300         return 0;
 301 }
 302
 303 static int __init
 304 agp_lba_init(void __iomem *lba_hpa)
 305 {
 306         struct _parisc_agp_info *info = &parisc_agp_info;
 307         int cap;
 308
 309         info->lba_regs = lba_hpa;
 310         info->lba_cap_offset = lba_find_capability(PCI_CAP_ID_AGP);
 311
 312         cap = readl(lba_hpa + info->lba_cap_offset) & 0xff;
 313         if (cap != PCI_CAP_ID_AGP) {
 314                 printk(KERN_ERR DRVPFX "Invalid capability ID 0x%02x at 0x%x\n",
 315                        cap, info->lba_cap_offset);
 316                 return -ENODEV;
 317         }
 318
 319         return 0;
 320 }
 321
 322 static int __init
 323 parisc_agp_setup(void __iomem *ioc_hpa, void __iomem *lba_hpa)
 324 {
 325         struct pci_dev *fake_bridge_dev = NULL;
 326         struct agp_bridge_data *bridge;
 327         int error = 0;
 328
 329         fake_bridge_dev = alloc_pci_dev();
 330         if (!fake_bridge_dev) {
 331                 error = -ENOMEM;
 332                 goto fail;
 333         }
 334
 335         error = agp_ioc_init(ioc_hpa);
 336         if (error)
 337                 goto fail;
 338
 339         error = agp_lba_init(lba_hpa);
 340         if (error)
 341                 goto fail;
 342
 343         bridge = agp_alloc_bridge();
 344         if (!bridge) {
 345                 error = -ENOMEM;
 346                 goto fail;
 347         }
 348         bridge->driver = &parisc_agp_driver;
 349
 350         fake_bridge_dev->vendor = PCI_VENDOR_ID_HP;
 351         fake_bridge_dev->device = PCI_DEVICE_ID_HP_PCIX_LBA;
 352         bridge->dev = fake_bridge_dev;
 353
 354         error = agp_add_bridge(bridge);
 355
 356 fail:
 357         return error;
 358 }
 359
 360 static struct device *next_device(struct klist_iter *i) {
 361         struct klist_node * n = klist_next(i);
 362         return n ? container_of(n, struct device, knode_parent) : NULL;
 363 }
 364
 365 static int
 366 parisc_agp_init(void)
 367 {
 368         extern struct sba_device *sba_list;
 369
 370         int err = -1;
 371         struct parisc_device *sba = NULL, *lba = NULL;
 372         struct lba_device *lbadev = NULL;
 373         struct device *dev = NULL;
 374         struct klist_iter i;
 375
 376         if (!sba_list)
 377                 goto out;
 378
 379         /* Find our parent Pluto */
 380         sba = sba_list->dev;
 381         if (!IS_PLUTO(sba)) {
 382                 printk(KERN_INFO DRVPFX "No Pluto found, so no AGPGART for you.\n");
 383                 goto out;
 384         }
 385
 386         /* Now search our Pluto for our precious AGP device... */
 387         klist_iter_init(&sba->dev.klist_children, &i);
 388         while ((dev = next_device(&i))) {
 389                 struct parisc_device *padev = to_parisc_device(dev);
 390                 if (IS_QUICKSILVER(padev))
 391                         lba = padev;
 392         }
 393         klist_iter_exit(&i);
 394
 395         if (!lba) {
 396                 printk(KERN_INFO DRVPFX "No AGP devices found.\n");
 397                 goto out;
 398         }
 399
 400         lbadev = parisc_get_drvdata(lba);
 401
 402         /* w00t, let's go find our cookies... */
 403         parisc_agp_setup(sba_list->ioc[0].ioc_hpa, lbadev->hba.base_addr);
 404
 405         return 0;
 406
 407 out:
 408         return err;
 409 }
 410
 411 module_init(parisc_agp_init);
 412
 413 MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>");
 414 MODULE_LICENSE("GPL");