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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / drivers / ata / pata_sil680.c
blob7c5b2dd9a1a1fdd851775cb462414f1dd8bc7457
1 /*
2 * pata_sil680.c - SIL680 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon
7 *
8 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
9 *
10 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat <alan@redhat.com>
12 *
13 * May be copied or modified under the terms of the GNU General Public License
14 *
15 * Documentation publically available.
16 *
17 * If you have strange problems with nVidia chipset systems please
18 * see the SI support documentation and update your system BIOS
19 * if necessary
20 *
21 * TODO
22 * If we know all our devices are LBA28 (or LBA28 sized) we could use
23 * the command fifo mode.
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/blkdev.h>
31 #include <linux/delay.h>
32 #include <scsi/scsi_host.h>
33 #include <linux/libata.h>
34
35 #define DRV_NAME "pata_sil680"
36 #define DRV_VERSION "0.4.8"
37
38 #define SIL680_MMIO_BAR 5
39
40 /**
41 * sil680_selreg - return register base
42 * @hwif: interface
43 * @r: config offset
44 *
45 * Turn a config register offset into the right address in either
46 * PCI space or MMIO space to access the control register in question
47 * Thankfully this is a configuration operation so isnt performance
48 * criticial.
49 */
50
51 static unsigned long sil680_selreg(struct ata_port *ap, int r)
52 {
53 unsigned long base = 0xA0 + r;
54 base += (ap->port_no << 4);
55 return base;
56 }
57
58 /**
59 * sil680_seldev - return register base
60 * @hwif: interface
61 * @r: config offset
62 *
63 * Turn a config register offset into the right address in either
64 * PCI space or MMIO space to access the control register in question
65 * including accounting for the unit shift.
66 */
67
68 static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
69 {
70 unsigned long base = 0xA0 + r;
71 base += (ap->port_no << 4);
72 base |= adev->devno ? 2 : 0;
73 return base;
74 }
75
76
77 /**
78 * sil680_cable_detect - cable detection
79 * @ap: ATA port
80 *
81 * Perform cable detection. The SIL680 stores this in PCI config
82 * space for us.
83 */
84
85 static int sil680_cable_detect(struct ata_port *ap) {
86 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
87 unsigned long addr = sil680_selreg(ap, 0);
88 u8 ata66;
89 pci_read_config_byte(pdev, addr, &ata66);
90 if (ata66 & 1)
91 return ATA_CBL_PATA80;
92 else
93 return ATA_CBL_PATA40;
94 }
95
96 /**
97 * sil680_set_piomode - set initial PIO mode data
98 * @ap: ATA interface
99 * @adev: ATA device
100 *
101 * Program the SIL680 registers for PIO mode. Note that the task speed
102 * registers are shared between the devices so we must pick the lowest
103 * mode for command work.
104 */
105
106 static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
107 {
108 static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
109 static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 };
110
111 unsigned long tfaddr = sil680_selreg(ap, 0x02);
112 unsigned long addr = sil680_seldev(ap, adev, 0x04);
113 unsigned long addr_mask = 0x80 + 4 * ap->port_no;
114 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
115 int pio = adev->pio_mode - XFER_PIO_0;
116 int lowest_pio = pio;
117 int port_shift = 4 * adev->devno;
118 u16 reg;
119 u8 mode;
120
121 struct ata_device *pair = ata_dev_pair(adev);
122
123 if (pair != NULL && adev->pio_mode > pair->pio_mode)
124 lowest_pio = pair->pio_mode - XFER_PIO_0;
125
126 pci_write_config_word(pdev, addr, speed_p[pio]);
127 pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
128
129 pci_read_config_word(pdev, tfaddr-2, &reg);
130 pci_read_config_byte(pdev, addr_mask, &mode);
131
132 reg &= ~0x0200; /* Clear IORDY */
133 mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */
134
135 if (ata_pio_need_iordy(adev)) {
136 reg |= 0x0200; /* Enable IORDY */
137 mode |= 1 << port_shift;
138 }
139 pci_write_config_word(pdev, tfaddr-2, reg);
140 pci_write_config_byte(pdev, addr_mask, mode);
141 }
142
143 /**
144 * sil680_set_dmamode - set initial DMA mode data
145 * @ap: ATA interface
146 * @adev: ATA device
147 *
148 * Program the MWDMA/UDMA modes for the sil680 k
149 * chipset. The MWDMA mode values are pulled from a lookup table
150 * while the chipset uses mode number for UDMA.
151 */
152
153 static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
154 {
155 static u8 ultra_table[2][7] = {
156 { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
157 { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
158 };
159 static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
160
161 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
162 unsigned long ma = sil680_seldev(ap, adev, 0x08);
163 unsigned long ua = sil680_seldev(ap, adev, 0x0C);
164 unsigned long addr_mask = 0x80 + 4 * ap->port_no;
165 int port_shift = adev->devno * 4;
166 u8 scsc, mode;
167 u16 multi, ultra;
168
169 pci_read_config_byte(pdev, 0x8A, &scsc);
170 pci_read_config_byte(pdev, addr_mask, &mode);
171 pci_read_config_word(pdev, ma, &multi);
172 pci_read_config_word(pdev, ua, &ultra);
173
174 /* Mask timing bits */
175 ultra &= ~0x3F;
176 mode &= ~(0x03 << port_shift);
177
178 /* Extract scsc */
179 scsc = (scsc & 0x30) ? 1: 0;
180
181 if (adev->dma_mode >= XFER_UDMA_0) {
182 multi = 0x10C1;
183 ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
184 mode |= (0x03 << port_shift);
185 } else {
186 multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
187 mode |= (0x02 << port_shift);
188 }
189 pci_write_config_byte(pdev, addr_mask, mode);
190 pci_write_config_word(pdev, ma, multi);
191 pci_write_config_word(pdev, ua, ultra);
192 }
193
194 static struct scsi_host_template sil680_sht = {
195 .module = THIS_MODULE,
196 .name = DRV_NAME,
197 .ioctl = ata_scsi_ioctl,
198 .queuecommand = ata_scsi_queuecmd,
199 .can_queue = ATA_DEF_QUEUE,
200 .this_id = ATA_SHT_THIS_ID,
201 .sg_tablesize = LIBATA_MAX_PRD,
202 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
203 .emulated = ATA_SHT_EMULATED,
204 .use_clustering = ATA_SHT_USE_CLUSTERING,
205 .proc_name = DRV_NAME,
206 .dma_boundary = ATA_DMA_BOUNDARY,
207 .slave_configure = ata_scsi_slave_config,
208 .slave_destroy = ata_scsi_slave_destroy,
209 .bios_param = ata_std_bios_param,
210 };
211
212 static struct ata_port_operations sil680_port_ops = {
213 .set_piomode = sil680_set_piomode,
214 .set_dmamode = sil680_set_dmamode,
215 .mode_filter = ata_pci_default_filter,
216 .tf_load = ata_tf_load,
217 .tf_read = ata_tf_read,
218 .check_status = ata_check_status,
219 .exec_command = ata_exec_command,
220 .dev_select = ata_std_dev_select,
221
222 .freeze = ata_bmdma_freeze,
223 .thaw = ata_bmdma_thaw,
224 .error_handler = ata_bmdma_error_handler,
225 .post_internal_cmd = ata_bmdma_post_internal_cmd,
226 .cable_detect = sil680_cable_detect,
227
228 .bmdma_setup = ata_bmdma_setup,
229 .bmdma_start = ata_bmdma_start,
230 .bmdma_stop = ata_bmdma_stop,
231 .bmdma_status = ata_bmdma_status,
232
233 .qc_prep = ata_qc_prep,
234 .qc_issue = ata_qc_issue_prot,
235
236 .data_xfer = ata_data_xfer,
237
238 .irq_handler = ata_interrupt,
239 .irq_clear = ata_bmdma_irq_clear,
240 .irq_on = ata_irq_on,
241
242 .port_start = ata_sff_port_start,
243 };
244
245 /**
246 * sil680_init_chip - chip setup
247 * @pdev: PCI device
248 *
249 * Perform all the chip setup which must be done both when the device
250 * is powered up on boot and when we resume in case we resumed from RAM.
251 * Returns the final clock settings.
252 */
253
254 static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)
255 {
256 u32 class_rev = 0;
257 u8 tmpbyte = 0;
258
259 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
260 class_rev &= 0xff;
261 /* FIXME: double check */
262 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
263
264 pci_write_config_byte(pdev, 0x80, 0x00);
265 pci_write_config_byte(pdev, 0x84, 0x00);
266
267 pci_read_config_byte(pdev, 0x8A, &tmpbyte);
268
269 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
270 tmpbyte & 1, tmpbyte & 0x30);
271
272 *try_mmio = 0;
273 #ifdef CONFIG_PPC_MERGE
274 if (machine_is(cell))
275 *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5);
276 #endif
277
278 switch(tmpbyte & 0x30) {
279 case 0x00:
280 /* 133 clock attempt to force it on */
281 pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
282 break;
283 case 0x30:
284 /* if clocking is disabled */
285 /* 133 clock attempt to force it on */
286 pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
287 break;
288 case 0x10:
289 /* 133 already */
290 break;
291 case 0x20:
292 /* BIOS set PCI x2 clocking */
293 break;
294 }
295
296 pci_read_config_byte(pdev, 0x8A, &tmpbyte);
297 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
298 tmpbyte & 1, tmpbyte & 0x30);
299
300 pci_write_config_byte(pdev, 0xA1, 0x72);
301 pci_write_config_word(pdev, 0xA2, 0x328A);
302 pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
303 pci_write_config_dword(pdev, 0xA8, 0x43924392);
304 pci_write_config_dword(pdev, 0xAC, 0x40094009);
305 pci_write_config_byte(pdev, 0xB1, 0x72);
306 pci_write_config_word(pdev, 0xB2, 0x328A);
307 pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
308 pci_write_config_dword(pdev, 0xB8, 0x43924392);
309 pci_write_config_dword(pdev, 0xBC, 0x40094009);
310
311 switch(tmpbyte & 0x30) {
312 case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
313 case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
314 case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
315 /* This last case is _NOT_ ok */
316 case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
317 }
318 return tmpbyte & 0x30;
319 }
320
321 static int __devinit sil680_init_one(struct pci_dev *pdev,
322 const struct pci_device_id *id)
323 {
324 static const struct ata_port_info info = {
325 .sht = &sil680_sht,
326 .flags = ATA_FLAG_SLAVE_POSS,
327 .pio_mask = 0x1f,
328 .mwdma_mask = 0x07,
329 .udma_mask = ATA_UDMA6,
330 .port_ops = &sil680_port_ops
331 };
332 static const struct ata_port_info info_slow = {
333 .sht = &sil680_sht,
334 .flags = ATA_FLAG_SLAVE_POSS,
335 .pio_mask = 0x1f,
336 .mwdma_mask = 0x07,
337 .udma_mask = ATA_UDMA5,
338 .port_ops = &sil680_port_ops
339 };
340 const struct ata_port_info *ppi[] = { &info, NULL };
341 static int printed_version;
342 struct ata_host *host;
343 void __iomem *mmio_base;
344 int rc, try_mmio;
345
346 if (!printed_version++)
347 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
348
349 switch (sil680_init_chip(pdev, &try_mmio)) {
350 case 0:
351 ppi[0] = &info_slow;
352 break;
353 case 0x30:
354 return -ENODEV;
355 }
356
357 if (!try_mmio)
358 goto use_ioports;
359
360 /* Try to acquire MMIO resources and fallback to PIO if
361 * that fails
362 */
363 rc = pcim_enable_device(pdev);
364 if (rc)
365 return rc;
366 rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
367 if (rc)
368 goto use_ioports;
369
370 /* Allocate host and set it up */
371 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
372 if (!host)
373 return -ENOMEM;
374 host->iomap = pcim_iomap_table(pdev);
375
376 /* Setup DMA masks */
377 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
378 if (rc)
379 return rc;
380 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
381 if (rc)
382 return rc;
383 pci_set_master(pdev);
384
385 /* Get MMIO base and initialize port addresses */
386 mmio_base = host->iomap[SIL680_MMIO_BAR];
387 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
388 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
389 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
390 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
391 ata_std_ports(&host->ports[0]->ioaddr);
392 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
393 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
394 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
395 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
396 ata_std_ports(&host->ports[1]->ioaddr);
397
398 /* Register & activate */
399 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
400 &sil680_sht);
401
402 use_ioports:
403 return ata_pci_init_one(pdev, ppi);
404 }
405
406 #ifdef CONFIG_PM
407 static int sil680_reinit_one(struct pci_dev *pdev)
408 {
409 int try_mmio;
410
411 sil680_init_chip(pdev, &try_mmio);
412 return ata_pci_device_resume(pdev);
413 }
414 #endif
415
416 static const struct pci_device_id sil680[] = {
417 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
418
419 { },
420 };
421
422 static struct pci_driver sil680_pci_driver = {
423 .name = DRV_NAME,
424 .id_table = sil680,
425 .probe = sil680_init_one,
426 .remove = ata_pci_remove_one,
427 #ifdef CONFIG_PM
428 .suspend = ata_pci_device_suspend,
429 .resume = sil680_reinit_one,
430 #endif
431 };
432
433 static int __init sil680_init(void)
434 {
435 return pci_register_driver(&sil680_pci_driver);
436 }
437
438 static void __exit sil680_exit(void)
439 {
440 pci_unregister_driver(&sil680_pci_driver);
441 }
442
443 MODULE_AUTHOR("Alan Cox");
444 MODULE_DESCRIPTION("low-level driver for SI680 PATA");
445 MODULE_LICENSE("GPL");
446 MODULE_DEVICE_TABLE(pci, sil680);
447 MODULE_VERSION(DRV_VERSION);
448
449 module_init(sil680_init);
450 module_exit(sil680_exit);
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