arch/x86/kernel/pci-dma_64.c

   1 /*
   2  * Dynamic DMA mapping support.
   3  */
   4
   5 #include <linux/types.h>
   6 #include <linux/mm.h>
   7 #include <linux/string.h>
   8 #include <linux/pci.h>
   9 #include <linux/module.h>
  10 #include <linux/dmar.h>
  11 #include <asm/io.h>
  12 #include <asm/gart.h>
  13 #include <asm/calgary.h>
  14
  15 int iommu_merge __read_mostly = 0;
  16
  17 dma_addr_t bad_dma_address __read_mostly;
  18 EXPORT_SYMBOL(bad_dma_address);
  19
  20 /* This tells the BIO block layer to assume merging. Default to off
  21    because we cannot guarantee merging later. */
  22 int iommu_bio_merge __read_mostly = 0;
  23 EXPORT_SYMBOL(iommu_bio_merge);
  24
  25 static int iommu_sac_force __read_mostly = 0;
  26
  27 int no_iommu __read_mostly;
  28 #ifdef CONFIG_IOMMU_DEBUG
  29 int panic_on_overflow __read_mostly = 1;
  30 int force_iommu __read_mostly = 1;
  31 #else
  32 int panic_on_overflow __read_mostly = 0;
  33 int force_iommu __read_mostly= 0;
  34 #endif
  35
  36 /* Set this to 1 if there is a HW IOMMU in the system */
  37 int iommu_detected __read_mostly = 0;
  38
  39 /* Dummy device used for NULL arguments (normally ISA). Better would
  40    be probably a smaller DMA mask, but this is bug-to-bug compatible
  41    to i386. */
  42 struct device fallback_dev = {
  43         .bus_id = "fallback device",
  44         .coherent_dma_mask = DMA_32BIT_MASK,
  45         .dma_mask = &fallback_dev.coherent_dma_mask,
  46 };
  47
  48 /* Allocate DMA memory on node near device */
  49 noinline static void *
  50 dma_alloc_pages(struct device *dev, gfp_t gfp, unsigned order)
  51 {
  52         struct page *page;
  53         int node;
  54
  55         node = dev_to_node(dev);
  56
  57         page = alloc_pages_node(node, gfp, order);
  58         return page ? page_address(page) : NULL;
  59 }
  60
  61 /*
  62  * Allocate memory for a coherent mapping.
  63  */
  64 void *
  65 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
  66                    gfp_t gfp)
  67 {
  68         void *memory;
  69         unsigned long dma_mask = 0;
  70         u64 bus;
  71
  72         if (!dev)
  73                 dev = &fallback_dev;
  74         dma_mask = dev->coherent_dma_mask;
  75         if (dma_mask == 0)
  76                 dma_mask = DMA_32BIT_MASK;
  77
  78         /* Device not DMA able */
  79         if (dev->dma_mask == NULL)
  80                 return NULL;
  81
  82         /* Don't invoke OOM killer */
  83         gfp |= __GFP_NORETRY;
  84
  85         /* Kludge to make it bug-to-bug compatible with i386. i386
  86            uses the normal dma_mask for alloc_coherent. */
  87         dma_mask &= *dev->dma_mask;
  88
  89         /* Why <=? Even when the mask is smaller than 4GB it is often
  90            larger than 16MB and in this case we have a chance of
  91            finding fitting memory in the next higher zone first. If
  92            not retry with true GFP_DMA. -AK */
  93         if (dma_mask <= DMA_32BIT_MASK)
  94                 gfp |= GFP_DMA32;
  95
  96  again:
  97         memory = dma_alloc_pages(dev, gfp, get_order(size));
  98         if (memory == NULL)
  99                 return NULL;
 100
 101         {
 102                 int high, mmu;
 103                 bus = virt_to_bus(memory);
 104                 high = (bus + size) >= dma_mask;
 105                 mmu = high;
 106                 if (force_iommu && !(gfp & GFP_DMA))
 107                         mmu = 1;
 108                 else if (high) {
 109                         free_pages((unsigned long)memory,
 110                                    get_order(size));
 111
 112                         /* Don't use the 16MB ZONE_DMA unless absolutely
 113                            needed. It's better to use remapping first. */
 114                         if (dma_mask < DMA_32BIT_MASK && !(gfp & GFP_DMA)) {
 115                                 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
 116                                 goto again;
 117                         }
 118
 119                         /* Let low level make its own zone decisions */
 120                         gfp &= ~(GFP_DMA32|GFP_DMA);
 121
 122                         if (dma_ops->alloc_coherent)
 123                                 return dma_ops->alloc_coherent(dev, size,
 124                                                            dma_handle, gfp);
 125                         return NULL;
 126                 }
 127
 128                 memset(memory, 0, size);
 129                 if (!mmu) {
 130                         *dma_handle = virt_to_bus(memory);
 131                         return memory;
 132                 }
 133         }
 134
 135         if (dma_ops->alloc_coherent) {
 136                 free_pages((unsigned long)memory, get_order(size));
 137                 gfp &= ~(GFP_DMA|GFP_DMA32);
 138                 return dma_ops->alloc_coherent(dev, size, dma_handle, gfp);
 139         }
 140
 141         if (dma_ops->map_simple) {
 142                 *dma_handle = dma_ops->map_simple(dev, memory,
 143                                               size,
 144                                               PCI_DMA_BIDIRECTIONAL);
 145                 if (*dma_handle != bad_dma_address)
 146                         return memory;
 147         }
 148
 149         if (panic_on_overflow)
 150                 panic("dma_alloc_coherent: IOMMU overflow by %lu bytes\n",size);
 151         free_pages((unsigned long)memory, get_order(size));
 152         return NULL;
 153 }
 154 EXPORT_SYMBOL(dma_alloc_coherent);
 155
 156 /*
 157  * Unmap coherent memory.
 158  * The caller must ensure that the device has finished accessing the mapping.
 159  */
 160 void dma_free_coherent(struct device *dev, size_t size,
 161                          void *vaddr, dma_addr_t bus)
 162 {
 163         WARN_ON(irqs_disabled());       /* for portability */
 164         if (dma_ops->unmap_single)
 165                 dma_ops->unmap_single(dev, bus, size, 0);
 166         free_pages((unsigned long)vaddr, get_order(size));
 167 }
 168 EXPORT_SYMBOL(dma_free_coherent);
 169
 170 static int forbid_dac __read_mostly;
 171
 172 int dma_supported(struct device *dev, u64 mask)
 173 {
 174 #ifdef CONFIG_PCI
 175         if (mask > 0xffffffff && forbid_dac > 0) {
 176
 177
 178
 179                 printk(KERN_INFO "PCI: Disallowing DAC for device %s\n", dev->bus_id);
 180                 return 0;
 181         }
 182 #endif
 183
 184         if (dma_ops->dma_supported)
 185                 return dma_ops->dma_supported(dev, mask);
 186
 187         /* Copied from i386. Doesn't make much sense, because it will
 188            only work for pci_alloc_coherent.
 189            The caller just has to use GFP_DMA in this case. */
 190         if (mask < DMA_24BIT_MASK)
 191                 return 0;
 192
 193         /* Tell the device to use SAC when IOMMU force is on.  This
 194            allows the driver to use cheaper accesses in some cases.
 195
 196            Problem with this is that if we overflow the IOMMU area and
 197            return DAC as fallback address the device may not handle it
 198            correctly.
 199
 200            As a special case some controllers have a 39bit address
 201            mode that is as efficient as 32bit (aic79xx). Don't force
 202            SAC for these.  Assume all masks <= 40 bits are of this
 203            type. Normally this doesn't make any difference, but gives
 204            more gentle handling of IOMMU overflow. */
 205         if (iommu_sac_force && (mask >= DMA_40BIT_MASK)) {
 206                 printk(KERN_INFO "%s: Force SAC with mask %Lx\n", dev->bus_id,mask);
 207                 return 0;
 208         }
 209
 210         return 1;
 211 }
 212 EXPORT_SYMBOL(dma_supported);
 213
 214 int dma_set_mask(struct device *dev, u64 mask)
 215 {
 216         if (!dev->dma_mask || !dma_supported(dev, mask))
 217                 return -EIO;
 218         *dev->dma_mask = mask;
 219         return 0;
 220 }
 221 EXPORT_SYMBOL(dma_set_mask);
 222
 223 /*
 224  * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
 225  * documentation.
 226  */
 227 static __init int iommu_setup(char *p)
 228 {
 229         iommu_merge = 1;
 230
 231         if (!p)
 232                 return -EINVAL;
 233
 234         while (*p) {
 235                 if (!strncmp(p,"off",3))
 236                         no_iommu = 1;
 237                 /* gart_parse_options has more force support */
 238                 if (!strncmp(p,"force",5))
 239                         force_iommu = 1;
 240                 if (!strncmp(p,"noforce",7)) {
 241                         iommu_merge = 0;
 242                         force_iommu = 0;
 243                 }
 244
 245                 if (!strncmp(p, "biomerge",8)) {
 246                         iommu_bio_merge = 4096;
 247                         iommu_merge = 1;
 248                         force_iommu = 1;
 249                 }
 250                 if (!strncmp(p, "panic",5))
 251                         panic_on_overflow = 1;
 252                 if (!strncmp(p, "nopanic",7))
 253                         panic_on_overflow = 0;
 254                 if (!strncmp(p, "merge",5)) {
 255                         iommu_merge = 1;
 256                         force_iommu = 1;
 257                 }
 258                 if (!strncmp(p, "nomerge",7))
 259                         iommu_merge = 0;
 260                 if (!strncmp(p, "forcesac",8))
 261                         iommu_sac_force = 1;
 262                 if (!strncmp(p, "allowdac", 8))
 263                         forbid_dac = 0;
 264                 if (!strncmp(p, "nodac", 5))
 265                         forbid_dac = -1;
 266
 267 #ifdef CONFIG_SWIOTLB
 268                 if (!strncmp(p, "soft",4))
 269                         swiotlb = 1;
 270 #endif
 271
 272 #ifdef CONFIG_GART_IOMMU
 273                 gart_parse_options(p);
 274 #endif
 275
 276 #ifdef CONFIG_CALGARY_IOMMU
 277                 if (!strncmp(p, "calgary", 7))
 278                         use_calgary = 1;
 279 #endif /* CONFIG_CALGARY_IOMMU */
 280
 281                 p += strcspn(p, ",");
 282                 if (*p == ',')
 283                         ++p;
 284         }
 285         return 0;
 286 }
 287 early_param("iommu", iommu_setup);
 288
 289 void __init pci_iommu_alloc(void)
 290 {
 291         /*
 292          * The order of these functions is important for
 293          * fall-back/fail-over reasons
 294          */
 295 #ifdef CONFIG_GART_IOMMU
 296         gart_iommu_hole_init();
 297 #endif
 298
 299 #ifdef CONFIG_CALGARY_IOMMU
 300         detect_calgary();
 301 #endif
 302
 303         detect_intel_iommu();
 304
 305 #ifdef CONFIG_SWIOTLB
 306         pci_swiotlb_init();
 307 #endif
 308 }
 309
 310 static int __init pci_iommu_init(void)
 311 {
 312 #ifdef CONFIG_CALGARY_IOMMU
 313         calgary_iommu_init();
 314 #endif
 315
 316         intel_iommu_init();
 317
 318 #ifdef CONFIG_GART_IOMMU
 319         gart_iommu_init();
 320 #endif
 321
 322         no_iommu_init();
 323         return 0;
 324 }
 325
 326 void pci_iommu_shutdown(void)
 327 {
 328         gart_iommu_shutdown();
 329 }
 330
 331 #ifdef CONFIG_PCI
 332 /* Many VIA bridges seem to corrupt data for DAC. Disable it here */
 333
 334 static __devinit void via_no_dac(struct pci_dev *dev)
 335 {
 336         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
 337                 printk(KERN_INFO "PCI: VIA PCI bridge detected. Disabling DAC.\n");
 338                 forbid_dac = 1;
 339         }
 340 }
 341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
 342 #endif
 343 /* Must execute after PCI subsystem */
 344 fs_initcall(pci_iommu_init);