1 /* $Id: rtrap.S,v 1.61 2002/02/09 19:49:31 davem Exp $
2 * rtrap.S: Preparing for return from trap on Sparc V9.
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
10 #include <asm/pstate.h>
11 #include <asm/ptrace.h>
12 #include <asm/spitfire.h>
14 #include <asm/visasm.h>
15 #include <asm/processor.h>
17 #define RTRAP_PSTATE (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
18 #define RTRAP_PSTATE_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV)
19 #define RTRAP_PSTATE_AG_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
21 /* Register %l6 keeps track of whether we are returning
22 * from a system call or not. It is cleared if we call
23 * do_notify_resume, and it must not be otherwise modified
24 * until we fully commit to returning to userspace.
32 ba,a,pt %xcc, __handle_softirq_continue
36 wrpr %g0, RTRAP_PSTATE, %pstate
37 ba,pt %xcc, __handle_preemption_continue
38 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
40 __handle_user_windows:
41 call fault_in_user_windows
42 wrpr %g0, RTRAP_PSTATE, %pstate
43 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
44 /* Redo sched+sig checks */
45 ldx [%g6 + TI_FLAGS], %l0
46 andcc %l0, _TIF_NEED_RESCHED, %g0
51 wrpr %g0, RTRAP_PSTATE, %pstate
52 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
53 ldx [%g6 + TI_FLAGS], %l0
55 1: andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
56 be,pt %xcc, __handle_user_windows_continue
60 add %sp, PTREGS_OFF, %o0
64 wrpr %g0, RTRAP_PSTATE, %pstate
65 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
67 /* Signal delivery can modify pt_regs tstate, so we must
70 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
71 sethi %hi(0xf << 20), %l4
73 ba,pt %xcc, __handle_user_windows_continue
78 wrpr %g0, RTRAP_PSTATE, %pstate
79 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
80 ldub [%g6 + TI_WSAVED], %o2
83 /* Redo userwin+sched+sig checks */
84 call fault_in_user_windows
86 wrpr %g0, RTRAP_PSTATE, %pstate
87 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
88 ldx [%g6 + TI_FLAGS], %l0
89 andcc %l0, _TIF_NEED_RESCHED, %g0
94 wrpr %g0, RTRAP_PSTATE, %pstate
95 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
96 ldx [%g6 + TI_FLAGS], %l0
97 1: andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
99 be,pt %xcc, __handle_perfctrs_continue
100 sethi %hi(TSTATE_PEF), %o0
103 add %sp, PTREGS_OFF, %o0
105 call do_notify_resume
107 wrpr %g0, RTRAP_PSTATE, %pstate
108 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
110 /* Signal delivery can modify pt_regs tstate, so we must
113 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
114 sethi %hi(0xf << 20), %l4
117 ba,pt %xcc, __handle_perfctrs_continue
119 sethi %hi(TSTATE_PEF), %o0
122 andcc %l5, FPRS_FEF, %g0
123 sethi %hi(TSTATE_PEF), %o0
124 be,a,pn %icc, __handle_userfpu_continue
126 ba,a,pt %xcc, __handle_userfpu_continue
131 add %sp, PTREGS_OFF, %o0
133 call do_notify_resume
134 wrpr %g0, RTRAP_PSTATE, %pstate
135 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
138 /* Signal delivery can modify pt_regs tstate, so we must
141 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
142 sethi %hi(0xf << 20), %l4
144 ba,pt %xcc, __handle_signal_continue
148 .globl rtrap_irq, rtrap_clr_l6, rtrap, irqsz_patchme, rtrap_xcall
150 rtrap_clr_l6: clr %l6
153 sethi %hi(per_cpu____cpu_data), %l0
154 lduw [%l0 + %lo(per_cpu____cpu_data)], %l1
156 sethi %hi(per_cpu____cpu_data), %l0
157 or %l0, %lo(per_cpu____cpu_data), %l0
158 lduw [%l0 + %g5], %l1
162 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
163 bne,pn %icc, __handle_softirq
164 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
165 __handle_softirq_continue:
167 sethi %hi(0xf << 20), %l4
171 #ifdef CONFIG_TRACE_IRQFLAGS
172 brnz,pn %l4, rtrap_no_irq_enable
174 call trace_hardirqs_on
179 andcc %l1, TSTATE_PRIV, %l3
180 bne,pn %icc, to_kernel
183 /* We must hold IRQs off and atomically test schedule+signal
184 * state, then hold them off all the way back to userspace.
185 * If we are returning to kernel, none of this matters. Note
186 * that we are disabling interrupts via PSTATE_IE, not using
189 * If we do not do this, there is a window where we would do
190 * the tests, later the signal/resched event arrives but we do
191 * not process it since we are still in kernel mode. It would
192 * take until the next local IRQ before the signal/resched
193 * event would be handled.
195 * This also means that if we have to deal with performance
196 * counters or user windows, we have to redo all of these
197 * sched+signal checks with IRQs disabled.
199 to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
201 __handle_preemption_continue:
202 ldx [%g6 + TI_FLAGS], %l0
203 sethi %hi(_TIF_USER_WORK_MASK), %o0
204 or %o0, %lo(_TIF_USER_WORK_MASK), %o0
206 sethi %hi(TSTATE_PEF), %o0
207 be,pt %xcc, user_nowork
209 andcc %l0, _TIF_NEED_RESCHED, %g0
210 bne,pn %xcc, __handle_preemption
211 andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
212 bne,pn %xcc, __handle_signal
213 __handle_signal_continue:
214 ldub [%g6 + TI_WSAVED], %o2
215 brnz,pn %o2, __handle_user_windows
217 __handle_user_windows_continue:
218 ldx [%g6 + TI_FLAGS], %l5
219 andcc %l5, _TIF_PERFCTR, %g0
220 sethi %hi(TSTATE_PEF), %o0
221 bne,pn %xcc, __handle_perfctrs
222 __handle_perfctrs_continue:
225 /* This fpdepth clear is necessary for non-syscall rtraps only */
227 bne,pn %xcc, __handle_userfpu
228 stb %g0, [%g6 + TI_FPDEPTH]
229 __handle_userfpu_continue:
231 rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
232 ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
234 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
235 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
236 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
240 /* Must do this before thread reg is clobbered below. */
241 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
243 ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
244 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
246 /* Normal globals are restored, go to trap globals. */
247 661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
249 .section .sun4v_2insn_patch, "ax"
251 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
257 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
258 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
260 ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
261 ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
262 ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
263 ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
264 ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
265 ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
266 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
267 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
269 ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
273 andn %l1, TSTATE_SYSCALL, %l1
274 wrpr %l1, %g0, %tstate
278 brnz,pn %l3, kern_rtt
279 mov PRIMARY_CONTEXT, %l7
281 661: ldxa [%l7 + %l7] ASI_DMMU, %l0
282 .section .sun4v_1insn_patch, "ax"
284 ldxa [%l7 + %l7] ASI_MMU, %l0
287 sethi %hi(sparc64_kern_pri_nuc_bits), %l1
288 ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
291 661: stxa %l0, [%l7] ASI_DMMU
292 .section .sun4v_1insn_patch, "ax"
294 stxa %l0, [%l7] ASI_MMU
297 sethi %hi(KERNBASE), %l7
303 wrpr %l2, %g0, %canrestore
304 wrpr %l1, %g0, %wstate
305 brnz,pt %l2, user_rtt_restore
306 wrpr %g0, %g0, %otherwin
308 ldx [%g6 + TI_FLAGS], %g3
309 wr %g0, ASI_AIUP, %asi
311 andcc %g3, _TIF_32BIT, %g0
313 bne,pt %xcc, user_rtt_fill_32bit
315 ba,a,pt %xcc, user_rtt_fill_64bit
324 wrpr %g2, 0x0, %wstate
326 /* We know %canrestore and %otherwin are both zero. */
328 sethi %hi(sparc64_kern_pri_context), %g2
329 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
330 mov PRIMARY_CONTEXT, %g1
332 661: stxa %g2, [%g1] ASI_DMMU
333 .section .sun4v_1insn_patch, "ax"
335 stxa %g2, [%g1] ASI_MMU
338 sethi %hi(KERNBASE), %g1
341 or %g4, FAULT_CODE_WINFIXUP, %g4
342 stb %g4, [%g6 + TI_FAULT_CODE]
343 stx %g5, [%g6 + TI_FAULT_ADDR]
349 .section .sun4v_1insn_patch, "ax"
354 wrpr %g0, RTRAP_PSTATE, %pstate
357 ldx [%g6 + TI_TASK], %g4
358 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
359 call do_sparc64_fault
360 add %sp, PTREGS_OFF, %o0
364 user_rtt_pre_restore:
370 rdpr %canrestore, %g1
371 wrpr %g1, 0x0, %cleanwin
375 kern_rtt: rdpr %canrestore, %g1
376 brz,pn %g1, kern_rtt_fill
383 #ifdef CONFIG_PREEMPT
384 ldsw [%g6 + TI_PRE_COUNT], %l5
385 brnz %l5, kern_fpucheck
386 ldx [%g6 + TI_FLAGS], %l5
387 andcc %l5, _TIF_NEED_RESCHED, %g0
388 be,pt %xcc, kern_fpucheck
391 bne,pn %xcc, kern_fpucheck
392 sethi %hi(PREEMPT_ACTIVE), %l6
393 stw %l6, [%g6 + TI_PRE_COUNT]
397 stw %g0, [%g6 + TI_PRE_COUNT]
399 kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
400 brz,pt %l5, rt_continue
402 add %g6, TI_FPSAVED, %l6
403 ldub [%l6 + %o0], %l2
407 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
409 and %l2, FPRS_DL, %l6
410 andcc %l2, FPRS_FEF, %g0
415 wr %g1, FPRS_FEF, %fprs
417 add %g6, TI_XFSR, %o1
419 add %g6, TI_FPREGS, %o3
421 add %g6, TI_FPREGS+0x40, %o4
424 ldda [%o3 + %o2] ASI_BLK_P, %f0
425 ldda [%o4 + %o2] ASI_BLK_P, %f16
427 1: andcc %l2, FPRS_DU, %g0
432 ldda [%o3 + %o2] ASI_BLK_P, %f32
433 ldda [%o4 + %o2] ASI_BLK_P, %f48
435 ldx [%o1 + %o5], %fsr
436 2: stb %l5, [%g6 + TI_FPDEPTH]
437 ba,pt %xcc, rt_continue
439 5: wr %g0, FPRS_FEF, %fprs
442 add %g6, TI_FPREGS+0x80, %o3
443 add %g6, TI_FPREGS+0xc0, %o4
445 ldda [%o3 + %o2] ASI_BLK_P, %f32
446 ldda [%o4 + %o2] ASI_BLK_P, %f48
448 wr %g0, FPRS_DU, %fprs
449 ba,pt %xcc, rt_continue
450 stb %l5, [%g6 + TI_FPDEPTH]