?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / arch / sparc64 / kernel / pci.c
blob39f0c46949371d73b325b413e88ca08d83e90366
1 /* pci.c: UltraSparc PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
9 */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/pci.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
21
22 #include <asm/uaccess.h>
23 #include <asm/pgtable.h>
24 #include <asm/irq.h>
25 #include <asm/ebus.h>
26 #include <asm/isa.h>
27 #include <asm/prom.h>
28 #include <asm/apb.h>
29
30 #include "pci_impl.h"
31
32 #ifndef CONFIG_PCI
33 /* A "nop" PCI implementation. */
34 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
35 unsigned long off, unsigned long len,
36 unsigned char *buf)
37 {
38 return 0;
39 }
40 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
41 unsigned long off, unsigned long len,
42 unsigned char *buf)
43 {
44 return 0;
45 }
46 #else
47
48 /* List of all PCI controllers found in the system. */
49 struct pci_pbm_info *pci_pbm_root = NULL;
50
51 /* Each PBM found gets a unique index. */
52 int pci_num_pbms = 0;
53
54 volatile int pci_poke_in_progress;
55 volatile int pci_poke_cpu = -1;
56 volatile int pci_poke_faulted;
57
58 static DEFINE_SPINLOCK(pci_poke_lock);
59
60 void pci_config_read8(u8 *addr, u8 *ret)
61 {
62 unsigned long flags;
63 u8 byte;
64
65 spin_lock_irqsave(&pci_poke_lock, flags);
66 pci_poke_cpu = smp_processor_id();
67 pci_poke_in_progress = 1;
68 pci_poke_faulted = 0;
69 __asm__ __volatile__("membar #Sync\n\t"
70 "lduba [%1] %2, %0\n\t"
71 "membar #Sync"
72 : "=r" (byte)
73 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
74 : "memory");
75 pci_poke_in_progress = 0;
76 pci_poke_cpu = -1;
77 if (!pci_poke_faulted)
78 *ret = byte;
79 spin_unlock_irqrestore(&pci_poke_lock, flags);
80 }
81
82 void pci_config_read16(u16 *addr, u16 *ret)
83 {
84 unsigned long flags;
85 u16 word;
86
87 spin_lock_irqsave(&pci_poke_lock, flags);
88 pci_poke_cpu = smp_processor_id();
89 pci_poke_in_progress = 1;
90 pci_poke_faulted = 0;
91 __asm__ __volatile__("membar #Sync\n\t"
92 "lduha [%1] %2, %0\n\t"
93 "membar #Sync"
94 : "=r" (word)
95 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
96 : "memory");
97 pci_poke_in_progress = 0;
98 pci_poke_cpu = -1;
99 if (!pci_poke_faulted)
100 *ret = word;
101 spin_unlock_irqrestore(&pci_poke_lock, flags);
102 }
103
104 void pci_config_read32(u32 *addr, u32 *ret)
105 {
106 unsigned long flags;
107 u32 dword;
108
109 spin_lock_irqsave(&pci_poke_lock, flags);
110 pci_poke_cpu = smp_processor_id();
111 pci_poke_in_progress = 1;
112 pci_poke_faulted = 0;
113 __asm__ __volatile__("membar #Sync\n\t"
114 "lduwa [%1] %2, %0\n\t"
115 "membar #Sync"
116 : "=r" (dword)
117 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
118 : "memory");
119 pci_poke_in_progress = 0;
120 pci_poke_cpu = -1;
121 if (!pci_poke_faulted)
122 *ret = dword;
123 spin_unlock_irqrestore(&pci_poke_lock, flags);
124 }
125
126 void pci_config_write8(u8 *addr, u8 val)
127 {
128 unsigned long flags;
129
130 spin_lock_irqsave(&pci_poke_lock, flags);
131 pci_poke_cpu = smp_processor_id();
132 pci_poke_in_progress = 1;
133 pci_poke_faulted = 0;
134 __asm__ __volatile__("membar #Sync\n\t"
135 "stba %0, [%1] %2\n\t"
136 "membar #Sync"
137 : /* no outputs */
138 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
139 : "memory");
140 pci_poke_in_progress = 0;
141 pci_poke_cpu = -1;
142 spin_unlock_irqrestore(&pci_poke_lock, flags);
143 }
144
145 void pci_config_write16(u16 *addr, u16 val)
146 {
147 unsigned long flags;
148
149 spin_lock_irqsave(&pci_poke_lock, flags);
150 pci_poke_cpu = smp_processor_id();
151 pci_poke_in_progress = 1;
152 pci_poke_faulted = 0;
153 __asm__ __volatile__("membar #Sync\n\t"
154 "stha %0, [%1] %2\n\t"
155 "membar #Sync"
156 : /* no outputs */
157 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
158 : "memory");
159 pci_poke_in_progress = 0;
160 pci_poke_cpu = -1;
161 spin_unlock_irqrestore(&pci_poke_lock, flags);
162 }
163
164 void pci_config_write32(u32 *addr, u32 val)
165 {
166 unsigned long flags;
167
168 spin_lock_irqsave(&pci_poke_lock, flags);
169 pci_poke_cpu = smp_processor_id();
170 pci_poke_in_progress = 1;
171 pci_poke_faulted = 0;
172 __asm__ __volatile__("membar #Sync\n\t"
173 "stwa %0, [%1] %2\n\t"
174 "membar #Sync"
175 : /* no outputs */
176 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
177 : "memory");
178 pci_poke_in_progress = 0;
179 pci_poke_cpu = -1;
180 spin_unlock_irqrestore(&pci_poke_lock, flags);
181 }
182
183 /* Probe for all PCI controllers in the system. */
184 extern void sabre_init(struct device_node *, const char *);
185 extern void psycho_init(struct device_node *, const char *);
186 extern void schizo_init(struct device_node *, const char *);
187 extern void schizo_plus_init(struct device_node *, const char *);
188 extern void tomatillo_init(struct device_node *, const char *);
189 extern void sun4v_pci_init(struct device_node *, const char *);
190 extern void fire_pci_init(struct device_node *, const char *);
191
192 static struct {
193 char *model_name;
194 void (*init)(struct device_node *, const char *);
195 } pci_controller_table[] __initdata = {
196 { "SUNW,sabre", sabre_init },
197 { "pci108e,a000", sabre_init },
198 { "pci108e,a001", sabre_init },
199 { "SUNW,psycho", psycho_init },
200 { "pci108e,8000", psycho_init },
201 { "SUNW,schizo", schizo_init },
202 { "pci108e,8001", schizo_init },
203 { "SUNW,schizo+", schizo_plus_init },
204 { "pci108e,8002", schizo_plus_init },
205 { "SUNW,tomatillo", tomatillo_init },
206 { "pci108e,a801", tomatillo_init },
207 { "SUNW,sun4v-pci", sun4v_pci_init },
208 { "pciex108e,80f0", fire_pci_init },
209 };
210 #define PCI_NUM_CONTROLLER_TYPES ARRAY_SIZE(pci_controller_table)
211
212 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
213 {
214 int i;
215
216 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
217 if (!strncmp(model_name,
218 pci_controller_table[i].model_name,
219 namelen)) {
220 pci_controller_table[i].init(dp, model_name);
221 return 1;
222 }
223 }
224
225 return 0;
226 }
227
228 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
229 {
230 struct device_node *dp;
231 int count = 0;
232
233 for_each_node_by_name(dp, "pci") {
234 struct property *prop;
235 int len;
236
237 prop = of_find_property(dp, "model", &len);
238 if (!prop)
239 prop = of_find_property(dp, "compatible", &len);
240
241 if (prop) {
242 const char *model = prop->value;
243 int item_len = 0;
244
245 /* Our value may be a multi-valued string in the
246 * case of some compatible properties. For sanity,
247 * only try the first one.
248 */
249 while (model[item_len] && len) {
250 len--;
251 item_len++;
252 }
253
254 if (handler(model, item_len, dp))
255 count++;
256 }
257 }
258
259 return count;
260 }
261
262 /* Find each controller in the system, attach and initialize
263 * software state structure for each and link into the
264 * pci_pbm_root. Setup the controller enough such
265 * that bus scanning can be done.
266 */
267 static void __init pci_controller_probe(void)
268 {
269 printk("PCI: Probing for controllers.\n");
270
271 pci_controller_scan(pci_controller_init);
272 }
273
274 static int ofpci_verbose;
275
276 static int __init ofpci_debug(char *str)
277 {
278 int val = 0;
279
280 get_option(&str, &val);
281 if (val)
282 ofpci_verbose = 1;
283 return 1;
284 }
285
286 __setup("ofpci_debug=", ofpci_debug);
287
288 static unsigned long pci_parse_of_flags(u32 addr0)
289 {
290 unsigned long flags = 0;
291
292 if (addr0 & 0x02000000) {
293 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
294 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
295 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
296 if (addr0 & 0x40000000)
297 flags |= IORESOURCE_PREFETCH
298 | PCI_BASE_ADDRESS_MEM_PREFETCH;
299 } else if (addr0 & 0x01000000)
300 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
301 return flags;
302 }
303
304 /* The of_device layer has translated all of the assigned-address properties
305 * into physical address resources, we only have to figure out the register
306 * mapping.
307 */
308 static void pci_parse_of_addrs(struct of_device *op,
309 struct device_node *node,
310 struct pci_dev *dev)
311 {
312 struct resource *op_res;
313 const u32 *addrs;
314 int proplen;
315
316 addrs = of_get_property(node, "assigned-addresses", &proplen);
317 if (!addrs)
318 return;
319 if (ofpci_verbose)
320 printk(" parse addresses (%d bytes) @ %p\n",
321 proplen, addrs);
322 op_res = &op->resource[0];
323 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
324 struct resource *res;
325 unsigned long flags;
326 int i;
327
328 flags = pci_parse_of_flags(addrs[0]);
329 if (!flags)
330 continue;
331 i = addrs[0] & 0xff;
332 if (ofpci_verbose)
333 printk(" start: %lx, end: %lx, i: %x\n",
334 op_res->start, op_res->end, i);
335
336 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
337 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
338 } else if (i == dev->rom_base_reg) {
339 res = &dev->resource[PCI_ROM_RESOURCE];
340 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
341 } else {
342 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
343 continue;
344 }
345 res->start = op_res->start;
346 res->end = op_res->end;
347 res->flags = flags;
348 res->name = pci_name(dev);
349 }
350 }
351
352 struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
353 struct device_node *node,
354 struct pci_bus *bus, int devfn)
355 {
356 struct dev_archdata *sd;
357 struct pci_dev *dev;
358 const char *type;
359 u32 class;
360
361 dev = alloc_pci_dev();
362 if (!dev)
363 return NULL;
364
365 sd = &dev->dev.archdata;
366 sd->iommu = pbm->iommu;
367 sd->stc = &pbm->stc;
368 sd->host_controller = pbm;
369 sd->prom_node = node;
370 sd->op = of_find_device_by_node(node);
371
372 sd = &sd->op->dev.archdata;
373 sd->iommu = pbm->iommu;
374 sd->stc = &pbm->stc;
375
376 type = of_get_property(node, "device_type", NULL);
377 if (type == NULL)
378 type = "";
379
380 if (ofpci_verbose)
381 printk(" create device, devfn: %x, type: %s\n",
382 devfn, type);
383
384 dev->bus = bus;
385 dev->sysdata = node;
386 dev->dev.parent = bus->bridge;
387 dev->dev.bus = &pci_bus_type;
388 dev->devfn = devfn;
389 dev->multifunction = 0; /* maybe a lie? */
390
391 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
392 dev->device = of_getintprop_default(node, "device-id", 0xffff);
393 dev->subsystem_vendor =
394 of_getintprop_default(node, "subsystem-vendor-id", 0);
395 dev->subsystem_device =
396 of_getintprop_default(node, "subsystem-id", 0);
397
398 dev->cfg_size = pci_cfg_space_size(dev);
399
400 /* We can't actually use the firmware value, we have
401 * to read what is in the register right now. One
402 * reason is that in the case of IDE interfaces the
403 * firmware can sample the value before the the IDE
404 * interface is programmed into native mode.
405 */
406 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
407 dev->class = class >> 8;
408 dev->revision = class & 0xff;
409
410 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
411 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
412
413 if (ofpci_verbose)
414 printk(" class: 0x%x device name: %s\n",
415 dev->class, pci_name(dev));
416
417 /* I have seen IDE devices which will not respond to
418 * the bmdma simplex check reads if bus mastering is
419 * disabled.
420 */
421 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
422 pci_set_master(dev);
423
424 dev->current_state = 4; /* unknown power state */
425 dev->error_state = pci_channel_io_normal;
426
427 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
428 /* a PCI-PCI bridge */
429 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
430 dev->rom_base_reg = PCI_ROM_ADDRESS1;
431 } else if (!strcmp(type, "cardbus")) {
432 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
433 } else {
434 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
435 dev->rom_base_reg = PCI_ROM_ADDRESS;
436
437 dev->irq = sd->op->irqs[0];
438 if (dev->irq == 0xffffffff)
439 dev->irq = PCI_IRQ_NONE;
440 }
441
442 pci_parse_of_addrs(sd->op, node, dev);
443
444 if (ofpci_verbose)
445 printk(" adding to system ...\n");
446
447 pci_device_add(dev, bus);
448
449 return dev;
450 }
451
452 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
453 {
454 u32 idx, first, last;
455
456 first = 8;
457 last = 0;
458 for (idx = 0; idx < 8; idx++) {
459 if ((map & (1 << idx)) != 0) {
460 if (first > idx)
461 first = idx;
462 if (last < idx)
463 last = idx;
464 }
465 }
466
467 *first_p = first;
468 *last_p = last;
469 }
470
471 static void pci_resource_adjust(struct resource *res,
472 struct resource *root)
473 {
474 res->start += root->start;
475 res->end += root->start;
476 }
477
478 /* For PCI bus devices which lack a 'ranges' property we interrogate
479 * the config space values to set the resources, just like the generic
480 * Linux PCI probing code does.
481 */
482 static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
483 struct pci_bus *bus,
484 struct pci_pbm_info *pbm)
485 {
486 struct resource *res;
487 u8 io_base_lo, io_limit_lo;
488 u16 mem_base_lo, mem_limit_lo;
489 unsigned long base, limit;
490
491 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
492 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
493 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
494 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
495
496 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
497 u16 io_base_hi, io_limit_hi;
498
499 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
500 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
501 base |= (io_base_hi << 16);
502 limit |= (io_limit_hi << 16);
503 }
504
505 res = bus->resource[0];
506 if (base <= limit) {
507 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
508 if (!res->start)
509 res->start = base;
510 if (!res->end)
511 res->end = limit + 0xfff;
512 pci_resource_adjust(res, &pbm->io_space);
513 }
514
515 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
516 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
517 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
518 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
519
520 res = bus->resource[1];
521 if (base <= limit) {
522 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
523 IORESOURCE_MEM);
524 res->start = base;
525 res->end = limit + 0xfffff;
526 pci_resource_adjust(res, &pbm->mem_space);
527 }
528
529 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
530 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
531 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
532 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
533
534 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
535 u32 mem_base_hi, mem_limit_hi;
536
537 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
538 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
539
540 /*
541 * Some bridges set the base > limit by default, and some
542 * (broken) BIOSes do not initialize them. If we find
543 * this, just assume they are not being used.
544 */
545 if (mem_base_hi <= mem_limit_hi) {
546 base |= ((long) mem_base_hi) << 32;
547 limit |= ((long) mem_limit_hi) << 32;
548 }
549 }
550
551 res = bus->resource[2];
552 if (base <= limit) {
553 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
554 IORESOURCE_MEM | IORESOURCE_PREFETCH);
555 res->start = base;
556 res->end = limit + 0xfffff;
557 pci_resource_adjust(res, &pbm->mem_space);
558 }
559 }
560
561 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
562 * a proper 'ranges' property.
563 */
564 static void __devinit apb_fake_ranges(struct pci_dev *dev,
565 struct pci_bus *bus,
566 struct pci_pbm_info *pbm)
567 {
568 struct resource *res;
569 u32 first, last;
570 u8 map;
571
572 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
573 apb_calc_first_last(map, &first, &last);
574 res = bus->resource[0];
575 res->start = (first << 21);
576 res->end = (last << 21) + ((1 << 21) - 1);
577 res->flags = IORESOURCE_IO;
578 pci_resource_adjust(res, &pbm->io_space);
579
580 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
581 apb_calc_first_last(map, &first, &last);
582 res = bus->resource[1];
583 res->start = (first << 21);
584 res->end = (last << 21) + ((1 << 21) - 1);
585 res->flags = IORESOURCE_MEM;
586 pci_resource_adjust(res, &pbm->mem_space);
587 }
588
589 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
590 struct device_node *node,
591 struct pci_bus *bus);
592
593 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
594
595 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
596 struct device_node *node,
597 struct pci_dev *dev)
598 {
599 struct pci_bus *bus;
600 const u32 *busrange, *ranges;
601 int len, i, simba;
602 struct resource *res;
603 unsigned int flags;
604 u64 size;
605
606 if (ofpci_verbose)
607 printk("of_scan_pci_bridge(%s)\n", node->full_name);
608
609 /* parse bus-range property */
610 busrange = of_get_property(node, "bus-range", &len);
611 if (busrange == NULL || len != 8) {
612 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
613 node->full_name);
614 return;
615 }
616 ranges = of_get_property(node, "ranges", &len);
617 simba = 0;
618 if (ranges == NULL) {
619 const char *model = of_get_property(node, "model", NULL);
620 if (model && !strcmp(model, "SUNW,simba"))
621 simba = 1;
622 }
623
624 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
625 if (!bus) {
626 printk(KERN_ERR "Failed to create pci bus for %s\n",
627 node->full_name);
628 return;
629 }
630
631 bus->primary = dev->bus->number;
632 bus->subordinate = busrange[1];
633 bus->bridge_ctl = 0;
634
635 /* parse ranges property, or cook one up by hand for Simba */
636 /* PCI #address-cells == 3 and #size-cells == 2 always */
637 res = &dev->resource[PCI_BRIDGE_RESOURCES];
638 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
639 res->flags = 0;
640 bus->resource[i] = res;
641 ++res;
642 }
643 if (simba) {
644 apb_fake_ranges(dev, bus, pbm);
645 goto after_ranges;
646 } else if (ranges == NULL) {
647 pci_cfg_fake_ranges(dev, bus, pbm);
648 goto after_ranges;
649 }
650 i = 1;
651 for (; len >= 32; len -= 32, ranges += 8) {
652 struct resource *root;
653
654 flags = pci_parse_of_flags(ranges[0]);
655 size = GET_64BIT(ranges, 6);
656 if (flags == 0 || size == 0)
657 continue;
658 if (flags & IORESOURCE_IO) {
659 res = bus->resource[0];
660 if (res->flags) {
661 printk(KERN_ERR "PCI: ignoring extra I/O range"
662 " for bridge %s\n", node->full_name);
663 continue;
664 }
665 root = &pbm->io_space;
666 } else {
667 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
668 printk(KERN_ERR "PCI: too many memory ranges"
669 " for bridge %s\n", node->full_name);
670 continue;
671 }
672 res = bus->resource[i];
673 ++i;
674 root = &pbm->mem_space;
675 }
676
677 res->start = GET_64BIT(ranges, 1);
678 res->end = res->start + size - 1;
679 res->flags = flags;
680
681 /* Another way to implement this would be to add an of_device
682 * layer routine that can calculate a resource for a given
683 * range property value in a PCI device.
684 */
685 pci_resource_adjust(res, root);
686 }
687 after_ranges:
688 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
689 bus->number);
690 if (ofpci_verbose)
691 printk(" bus name: %s\n", bus->name);
692
693 pci_of_scan_bus(pbm, node, bus);
694 }
695
696 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
697 struct device_node *node,
698 struct pci_bus *bus)
699 {
700 struct device_node *child;
701 const u32 *reg;
702 int reglen, devfn, prev_devfn;
703 struct pci_dev *dev;
704
705 if (ofpci_verbose)
706 printk("PCI: scan_bus[%s] bus no %d\n",
707 node->full_name, bus->number);
708
709 child = NULL;
710 prev_devfn = -1;
711 while ((child = of_get_next_child(node, child)) != NULL) {
712 if (ofpci_verbose)
713 printk(" * %s\n", child->full_name);
714 reg = of_get_property(child, "reg", &reglen);
715 if (reg == NULL || reglen < 20)
716 continue;
717
718 devfn = (reg[0] >> 8) & 0xff;
719
720 /* This is a workaround for some device trees
721 * which list PCI devices twice. On the V100
722 * for example, device number 3 is listed twice.
723 * Once as "pm" and once again as "lomp".
724 */
725 if (devfn == prev_devfn)
726 continue;
727 prev_devfn = devfn;
728
729 /* create a new pci_dev for this device */
730 dev = of_create_pci_dev(pbm, child, bus, devfn);
731 if (!dev)
732 continue;
733 if (ofpci_verbose)
734 printk("PCI: dev header type: %x\n",
735 dev->hdr_type);
736
737 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
738 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
739 of_scan_pci_bridge(pbm, child, dev);
740 }
741 }
742
743 static ssize_t
744 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
745 {
746 struct pci_dev *pdev;
747 struct device_node *dp;
748
749 pdev = to_pci_dev(dev);
750 dp = pdev->dev.archdata.prom_node;
751
752 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
753 }
754
755 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
756
757 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
758 {
759 struct pci_dev *dev;
760 struct pci_bus *child_bus;
761 int err;
762
763 list_for_each_entry(dev, &bus->devices, bus_list) {
764 /* we don't really care if we can create this file or
765 * not, but we need to assign the result of the call
766 * or the world will fall under alien invasion and
767 * everybody will be frozen on a spaceship ready to be
768 * eaten on alpha centauri by some green and jelly
769 * humanoid.
770 */
771 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
772 }
773 list_for_each_entry(child_bus, &bus->children, node)
774 pci_bus_register_of_sysfs(child_bus);
775 }
776
777 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
778 {
779 struct device_node *node = pbm->prom_node;
780 struct pci_bus *bus;
781
782 printk("PCI: Scanning PBM %s\n", node->full_name);
783
784 /* XXX parent device? XXX */
785 bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
786 if (!bus) {
787 printk(KERN_ERR "Failed to create bus for %s\n",
788 node->full_name);
789 return NULL;
790 }
791 bus->secondary = pbm->pci_first_busno;
792 bus->subordinate = pbm->pci_last_busno;
793
794 bus->resource[0] = &pbm->io_space;
795 bus->resource[1] = &pbm->mem_space;
796
797 pci_of_scan_bus(pbm, node, bus);
798 pci_bus_add_devices(bus);
799 pci_bus_register_of_sysfs(bus);
800
801 return bus;
802 }
803
804 static void __init pci_scan_each_controller_bus(void)
805 {
806 struct pci_pbm_info *pbm;
807
808 for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
809 pbm->scan_bus(pbm);
810 }
811
812 extern void power_init(void);
813
814 static int __init pcibios_init(void)
815 {
816 pci_controller_probe();
817 if (pci_pbm_root == NULL)
818 return 0;
819
820 pci_scan_each_controller_bus();
821
822 isa_init();
823 ebus_init();
824 power_init();
825
826 return 0;
827 }
828
829 subsys_initcall(pcibios_init);
830
831 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
832 {
833 struct pci_pbm_info *pbm = pbus->sysdata;
834
835 /* Generic PCI bus probing sets these to point at
836 * &io{port,mem}_resouce which is wrong for us.
837 */
838 pbus->resource[0] = &pbm->io_space;
839 pbus->resource[1] = &pbm->mem_space;
840 }
841
842 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
843 {
844 struct pci_pbm_info *pbm = pdev->bus->sysdata;
845 struct resource *root = NULL;
846
847 if (r->flags & IORESOURCE_IO)
848 root = &pbm->io_space;
849 if (r->flags & IORESOURCE_MEM)
850 root = &pbm->mem_space;
851
852 return root;
853 }
854
855 void pcibios_update_irq(struct pci_dev *pdev, int irq)
856 {
857 }
858
859 void pcibios_align_resource(void *data, struct resource *res,
860 resource_size_t size, resource_size_t align)
861 {
862 }
863
864 int pcibios_enable_device(struct pci_dev *dev, int mask)
865 {
866 u16 cmd, oldcmd;
867 int i;
868
869 pci_read_config_word(dev, PCI_COMMAND, &cmd);
870 oldcmd = cmd;
871
872 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
873 struct resource *res = &dev->resource[i];
874
875 /* Only set up the requested stuff */
876 if (!(mask & (1<<i)))
877 continue;
878
879 if (res->flags & IORESOURCE_IO)
880 cmd |= PCI_COMMAND_IO;
881 if (res->flags & IORESOURCE_MEM)
882 cmd |= PCI_COMMAND_MEMORY;
883 }
884
885 if (cmd != oldcmd) {
886 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
887 pci_name(dev), cmd);
888 /* Enable the appropriate bits in the PCI command register. */
889 pci_write_config_word(dev, PCI_COMMAND, cmd);
890 }
891 return 0;
892 }
893
894 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
895 struct resource *res)
896 {
897 struct pci_pbm_info *pbm = pdev->bus->sysdata;
898 struct resource zero_res, *root;
899
900 zero_res.start = 0;
901 zero_res.end = 0;
902 zero_res.flags = res->flags;
903
904 if (res->flags & IORESOURCE_IO)
905 root = &pbm->io_space;
906 else
907 root = &pbm->mem_space;
908
909 pci_resource_adjust(&zero_res, root);
910
911 region->start = res->start - zero_res.start;
912 region->end = res->end - zero_res.start;
913 }
914 EXPORT_SYMBOL(pcibios_resource_to_bus);
915
916 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
917 struct pci_bus_region *region)
918 {
919 struct pci_pbm_info *pbm = pdev->bus->sysdata;
920 struct resource *root;
921
922 res->start = region->start;
923 res->end = region->end;
924
925 if (res->flags & IORESOURCE_IO)
926 root = &pbm->io_space;
927 else
928 root = &pbm->mem_space;
929
930 pci_resource_adjust(res, root);
931 }
932 EXPORT_SYMBOL(pcibios_bus_to_resource);
933
934 char * __devinit pcibios_setup(char *str)
935 {
936 return str;
937 }
938
939 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
940
941 /* If the user uses a host-bridge as the PCI device, he may use
942 * this to perform a raw mmap() of the I/O or MEM space behind
943 * that controller.
944 *
945 * This can be useful for execution of x86 PCI bios initialization code
946 * on a PCI card, like the xfree86 int10 stuff does.
947 */
948 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
949 enum pci_mmap_state mmap_state)
950 {
951 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
952 unsigned long space_size, user_offset, user_size;
953
954 if (mmap_state == pci_mmap_io) {
955 space_size = (pbm->io_space.end -
956 pbm->io_space.start) + 1;
957 } else {
958 space_size = (pbm->mem_space.end -
959 pbm->mem_space.start) + 1;
960 }
961
962 /* Make sure the request is in range. */
963 user_offset = vma->vm_pgoff << PAGE_SHIFT;
964 user_size = vma->vm_end - vma->vm_start;
965
966 if (user_offset >= space_size ||
967 (user_offset + user_size) > space_size)
968 return -EINVAL;
969
970 if (mmap_state == pci_mmap_io) {
971 vma->vm_pgoff = (pbm->io_space.start +
972 user_offset) >> PAGE_SHIFT;
973 } else {
974 vma->vm_pgoff = (pbm->mem_space.start +
975 user_offset) >> PAGE_SHIFT;
976 }
977
978 return 0;
979 }
980
981 /* Adjust vm_pgoff of VMA such that it is the physical page offset
982 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
983 *
984 * Basically, the user finds the base address for his device which he wishes
985 * to mmap. They read the 32-bit value from the config space base register,
986 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
987 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
988 *
989 * Returns negative error code on failure, zero on success.
990 */
991 static int __pci_mmap_make_offset(struct pci_dev *pdev,
992 struct vm_area_struct *vma,
993 enum pci_mmap_state mmap_state)
994 {
995 unsigned long user_paddr, user_size;
996 int i, err;
997
998 /* First compute the physical address in vma->vm_pgoff,
999 * making sure the user offset is within range in the
1000 * appropriate PCI space.
1001 */
1002 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
1003 if (err)
1004 return err;
1005
1006 /* If this is a mapping on a host bridge, any address
1007 * is OK.
1008 */
1009 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1010 return err;
1011
1012 /* Otherwise make sure it's in the range for one of the
1013 * device's resources.
1014 */
1015 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
1016 user_size = vma->vm_end - vma->vm_start;
1017
1018 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1019 struct resource *rp = &pdev->resource[i];
1020
1021 /* Active? */
1022 if (!rp->flags)
1023 continue;
1024
1025 /* Same type? */
1026 if (i == PCI_ROM_RESOURCE) {
1027 if (mmap_state != pci_mmap_mem)
1028 continue;
1029 } else {
1030 if ((mmap_state == pci_mmap_io &&
1031 (rp->flags & IORESOURCE_IO) == 0) ||
1032 (mmap_state == pci_mmap_mem &&
1033 (rp->flags & IORESOURCE_MEM) == 0))
1034 continue;
1035 }
1036
1037 if ((rp->start <= user_paddr) &&
1038 (user_paddr + user_size) <= (rp->end + 1UL))
1039 break;
1040 }
1041
1042 if (i > PCI_ROM_RESOURCE)
1043 return -EINVAL;
1044
1045 return 0;
1046 }
1047
1048 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1049 * mapping.
1050 */
1051 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1052 enum pci_mmap_state mmap_state)
1053 {
1054 vma->vm_flags |= (VM_IO | VM_RESERVED);
1055 }
1056
1057 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1058 * device mapping.
1059 */
1060 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1061 enum pci_mmap_state mmap_state)
1062 {
1063 /* Our io_remap_pfn_range takes care of this, do nothing. */
1064 }
1065
1066 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1067 * for this architecture. The region in the process to map is described by vm_start
1068 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1069 * The pci device structure is provided so that architectures may make mapping
1070 * decisions on a per-device or per-bus basis.
1071 *
1072 * Returns a negative error code on failure, zero on success.
1073 */
1074 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1075 enum pci_mmap_state mmap_state,
1076 int write_combine)
1077 {
1078 int ret;
1079
1080 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1081 if (ret < 0)
1082 return ret;
1083
1084 __pci_mmap_set_flags(dev, vma, mmap_state);
1085 __pci_mmap_set_pgprot(dev, vma, mmap_state);
1086
1087 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1088 ret = io_remap_pfn_range(vma, vma->vm_start,
1089 vma->vm_pgoff,
1090 vma->vm_end - vma->vm_start,
1091 vma->vm_page_prot);
1092 if (ret)
1093 return ret;
1094
1095 return 0;
1096 }
1097
1098 /* Return the domain nuber for this pci bus */
1099
1100 int pci_domain_nr(struct pci_bus *pbus)
1101 {
1102 struct pci_pbm_info *pbm = pbus->sysdata;
1103 int ret;
1104
1105 if (pbm == NULL || pbm->parent == NULL) {
1106 ret = -ENXIO;
1107 } else {
1108 ret = pbm->index;
1109 }
1110
1111 return ret;
1112 }
1113 EXPORT_SYMBOL(pci_domain_nr);
1114
1115 #ifdef CONFIG_PCI_MSI
1116 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1117 {
1118 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1119 int virt_irq;
1120
1121 if (!pbm->setup_msi_irq)
1122 return -EINVAL;
1123
1124 return pbm->setup_msi_irq(&virt_irq, pdev, desc);
1125 }
1126
1127 void arch_teardown_msi_irq(unsigned int virt_irq)
1128 {
1129 struct msi_desc *entry = get_irq_msi(virt_irq);
1130 struct pci_dev *pdev = entry->dev;
1131 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1132
1133 if (!pbm->teardown_msi_irq)
1134 return;
1135
1136 return pbm->teardown_msi_irq(virt_irq, pdev);
1137 }
1138 #endif /* !(CONFIG_PCI_MSI) */
1139
1140 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1141 {
1142 return pdev->dev.archdata.prom_node;
1143 }
1144 EXPORT_SYMBOL(pci_device_to_OF_node);
1145
1146 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
1147 {
1148 struct pci_dev *ali_isa_bridge;
1149 u8 val;
1150
1151 /* ALI sound chips generate 31-bits of DMA, a special register
1152 * determines what bit 31 is emitted as.
1153 */
1154 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
1155 PCI_DEVICE_ID_AL_M1533,
1156 NULL);
1157
1158 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
1159 if (set_bit)
1160 val |= 0x01;
1161 else
1162 val &= ~0x01;
1163 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
1164 pci_dev_put(ali_isa_bridge);
1165 }
1166
1167 int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
1168 {
1169 u64 dma_addr_mask;
1170
1171 if (pdev == NULL) {
1172 dma_addr_mask = 0xffffffff;
1173 } else {
1174 struct iommu *iommu = pdev->dev.archdata.iommu;
1175
1176 dma_addr_mask = iommu->dma_addr_mask;
1177
1178 if (pdev->vendor == PCI_VENDOR_ID_AL &&
1179 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
1180 device_mask == 0x7fffffff) {
1181 ali_sound_dma_hack(pdev,
1182 (dma_addr_mask & 0x80000000) != 0);
1183 return 1;
1184 }
1185 }
1186
1187 if (device_mask >= (1UL << 32UL))
1188 return 0;
1189
1190 return (device_mask & dma_addr_mask) == dma_addr_mask;
1191 }
1192
1193 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
1194 const struct resource *rp, resource_size_t *start,
1195 resource_size_t *end)
1196 {
1197 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1198 unsigned long offset;
1199
1200 if (rp->flags & IORESOURCE_IO)
1201 offset = pbm->io_space.start;
1202 else
1203 offset = pbm->mem_space.start;
1204
1205 *start = rp->start - offset;
1206 *end = rp->end - offset;
1207 }
1208
1209 #endif /* !(CONFIG_PCI) */
mah project overlay