arch/sh/kernel/cpu/sh4a/setup-sh7722.c

   1 /*
   2  * SH7722 Setup
   3  *
   4  *  Copyright (C) 2006 - 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/mm.h>
  15 #include <asm/mmzone.h>
  16
  17 static struct resource usbf_resources[] = {
  18         [0] = {
  19                 .name   = "m66592_udc",
  20                 .start  = 0xA4480000,
  21                 .end    = 0xA44800FF,
  22                 .flags  = IORESOURCE_MEM,
  23         },
  24         [1] = {
  25                 .name   = "m66592_udc",
  26                 .start  = 65,
  27                 .end    = 65,
  28                 .flags  = IORESOURCE_IRQ,
  29         },
  30 };
  31
  32 static struct platform_device usbf_device = {
  33         .name           = "m66592_udc",
  34         .id             = -1,
  35         .dev = {
  36                 .dma_mask               = NULL,
  37                 .coherent_dma_mask      = 0xffffffff,
  38         },
  39         .num_resources  = ARRAY_SIZE(usbf_resources),
  40         .resource       = usbf_resources,
  41 };
  42
  43 static struct plat_sci_port sci_platform_data[] = {
  44         {
  45                 .mapbase        = 0xffe00000,
  46                 .flags          = UPF_BOOT_AUTOCONF,
  47                 .type           = PORT_SCIF,
  48                 .irqs           = { 80, 80, 80, 80 },
  49         },
  50         {
  51                 .mapbase        = 0xffe10000,
  52                 .flags          = UPF_BOOT_AUTOCONF,
  53                 .type           = PORT_SCIF,
  54                 .irqs           = { 81, 81, 81, 81 },
  55         },
  56         {
  57                 .mapbase        = 0xffe20000,
  58                 .flags          = UPF_BOOT_AUTOCONF,
  59                 .type           = PORT_SCIF,
  60                 .irqs           = { 82, 82, 82, 82 },
  61         },
  62         {
  63                 .flags = 0,
  64         }
  65 };
  66
  67 static struct platform_device sci_device = {
  68         .name           = "sh-sci",
  69         .id             = -1,
  70         .dev            = {
  71                 .platform_data  = sci_platform_data,
  72         },
  73 };
  74
  75 static struct platform_device *sh7722_devices[] __initdata = {
  76         &usbf_device,
  77         &sci_device,
  78 };
  79
  80 static int __init sh7722_devices_setup(void)
  81 {
  82         return platform_add_devices(sh7722_devices,
  83                                     ARRAY_SIZE(sh7722_devices));
  84 }
  85 __initcall(sh7722_devices_setup);
  86
  87 enum {
  88         UNUSED=0,
  89
  90         /* interrupt sources */
  91         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  92         HUDI,
  93         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
  94         RTC_ATI, RTC_PRI, RTC_CUI,
  95         DMAC0, DMAC1, DMAC2, DMAC3,
  96         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
  97         VPU, TPU,
  98         USB_USBI0, USB_USBI1,
  99         DMAC4, DMAC5, DMAC_DADERR,
 100         KEYSC,
 101         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
 102         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 103         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 104         SDHI0, SDHI1, SDHI2, SDHI3,
 105         CMT, TSIF, SIU, TWODG,
 106         TMU0, TMU1, TMU2,
 107         IRDA, JPU, LCDC,
 108
 109         /* interrupt groups */
 110
 111         SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
 112 };
 113
 114 static struct intc_vect vectors[] __initdata = {
 115         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 116         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 117         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 118         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 119         INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
 120         INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
 121         INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
 122         INTC_VECT(RTC_CUI, 0x7c0),
 123         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 124         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 125         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 126         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 127         INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
 128         INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
 129         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 130         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 131         INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
 132         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
 133         INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
 134         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 135         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 136         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 137         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 138         INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
 139         INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
 140         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 141         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
 142         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 143         INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
 144         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 145 };
 146
 147 static struct intc_group groups[] __initdata = {
 148         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
 149         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 150         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 151         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 152         INTC_GROUP(USB, USB_USBI0, USB_USBI1),
 153         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 154         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 155                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 156         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 157         INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 158 };
 159
 160 static struct intc_mask_reg mask_registers[] __initdata = {
 161         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 162           { } },
 163         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 164           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 165         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 166           { 0, 0, 0, VPU, } },
 167         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 168           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 169         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 170           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 171         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 172           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
 173         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 174           { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
 175         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 176           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 177             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 178         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 179           { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
 180         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 181           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
 182         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 183           { } },
 184         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 185           { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
 186         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 187           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 188 };
 189
 190 static struct intc_prio_reg prio_registers[] __initdata = {
 191         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
 192         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 193         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 194         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 195         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
 196         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 197         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
 198         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
 199         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
 200         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 201         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
 202         { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
 203         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 204           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 205 };
 206
 207 static struct intc_sense_reg sense_registers[] __initdata = {
 208         { 0xa414001c, 16, 2, /* ICR1 */
 209           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 210 };
 211
 212 static DECLARE_INTC_DESC(intc_desc, "sh7722", vectors, groups,
 213                          mask_registers, prio_registers, sense_registers);
 214
 215 void __init plat_irq_setup(void)
 216 {
 217         register_intc_controller(&intc_desc);
 218 }
 219
 220 void __init plat_mem_setup(void)
 221 {
 222         /* Register the URAM space as Node 1 */
 223         setup_bootmem_node(1, 0x055f0000, 0x05610000);
 224 }