arch/sh/kernel/cpu/sh4a/clock-shx3.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4/clock-shx3.c
   3  *
   4  * SH-X3 support for the clock framework
   5  *
   6  *  Copyright (C) 2006-2007  Renesas Technology Corp.
   7  *  Copyright (C) 2006-2007  Renesas Solutions Corp.
   8  *  Copyright (C) 2006-2007  Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <asm/clock.h>
  17 #include <asm/freq.h>
  18 #include <asm/io.h>
  19
  20 static int ifc_divisors[] = { 1, 2, 4 ,6 };
  21 static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
  22 static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 };
  23 static int cfc_divisors[] = { 1, 1, 4, 6 };
  24
  25 #define IFC_POS         28
  26 #define IFC_MSK         0x0003
  27 #define BFC_MSK         0x000f
  28 #define PFC_MSK         0x000f
  29 #define CFC_MSK         0x0003
  30 #define BFC_POS         16
  31 #define PFC_POS         0
  32 #define CFC_POS         20
  33
  34 static void master_clk_init(struct clk *clk)
  35 {
  36         clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK];
  37 }
  38
  39 static struct clk_ops shx3_master_clk_ops = {
  40         .init           = master_clk_init,
  41 };
  42
  43 static void module_clk_recalc(struct clk *clk)
  44 {
  45         int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK);
  46         clk->rate = clk->parent->rate / pfc_divisors[idx];
  47 }
  48
  49 static struct clk_ops shx3_module_clk_ops = {
  50         .recalc         = module_clk_recalc,
  51 };
  52
  53 static void bus_clk_recalc(struct clk *clk)
  54 {
  55         int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK);
  56         clk->rate = clk->parent->rate / bfc_divisors[idx];
  57 }
  58
  59 static struct clk_ops shx3_bus_clk_ops = {
  60         .recalc         = bus_clk_recalc,
  61 };
  62
  63 static void cpu_clk_recalc(struct clk *clk)
  64 {
  65         int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK);
  66         clk->rate = clk->parent->rate / ifc_divisors[idx];
  67 }
  68
  69 static struct clk_ops shx3_cpu_clk_ops = {
  70         .recalc         = cpu_clk_recalc,
  71 };
  72
  73 static struct clk_ops *shx3_clk_ops[] = {
  74         &shx3_master_clk_ops,
  75         &shx3_module_clk_ops,
  76         &shx3_bus_clk_ops,
  77         &shx3_cpu_clk_ops,
  78 };
  79
  80 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
  81 {
  82         if (idx < ARRAY_SIZE(shx3_clk_ops))
  83                 *ops = shx3_clk_ops[idx];
  84 }
  85
  86 static void shyway_clk_recalc(struct clk *clk)
  87 {
  88         int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK);
  89         clk->rate = clk->parent->rate / cfc_divisors[idx];
  90 }
  91
  92 static struct clk_ops shx3_shyway_clk_ops = {
  93         .recalc         = shyway_clk_recalc,
  94 };
  95
  96 static struct clk shx3_shyway_clk = {
  97         .name           = "shyway_clk",
  98         .flags          = CLK_ALWAYS_ENABLED,
  99         .ops            = &shx3_shyway_clk_ops,
 100 };
 101
 102 /*
 103  * Additional SHx3-specific on-chip clocks that aren't already part of the
 104  * clock framework
 105  */
 106 static struct clk *shx3_onchip_clocks[] = {
 107         &shx3_shyway_clk,
 108 };
 109
 110 static int __init shx3_clk_init(void)
 111 {
 112         struct clk *clk = clk_get(NULL, "master_clk");
 113         int i;
 114
 115         for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
 116                 struct clk *clkp = shx3_onchip_clocks[i];
 117
 118                 clkp->parent = clk;
 119                 clk_register(clkp);
 120                 clk_enable(clkp);
 121         }
 122
 123         /*
 124          * Now that we have the rest of the clocks registered, we need to
 125          * force the parent clock to propagate so that these clocks will
 126          * automatically figure out their rate. We cheat by handing the
 127          * parent clock its current rate and forcing child propagation.
 128          */
 129         clk_set_rate(clk, clk_get_rate(clk));
 130
 131         clk_put(clk);
 132
 133         return 0;
 134 }
 135 arch_initcall(shx3_clk_init);