arch/sh/kernel/cpu/sh4/setup-sh7760.c

   1 /*
   2  * SH7760 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14
  15 enum {
  16         UNUSED = 0,
  17
  18         /* interrupt sources */
  19         IRL0, IRL1, IRL2, IRL3,
  20         HUDI, GPIOI,
  21         DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
  22         DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
  23         DMAC_DMAE,
  24         IRQ4, IRQ5, IRQ6, IRQ7,
  25         HCAN20, HCAN21,
  26         SSI0, SSI1,
  27         HAC0, HAC1,
  28         I2C0, I2C1,
  29         USB, LCDC,
  30         DMABRG0, DMABRG1, DMABRG2,
  31         SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
  32         SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
  33         SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
  34         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
  35         HSPI,
  36         MMCIF0, MMCIF1, MMCIF2, MMCIF3,
  37         MFI, ADC, CMT,
  38         TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
  39         WDT,
  40         REF_RCMI, REF_ROVI,
  41
  42         /* interrupt groups */
  43         DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF,
  44 };
  45
  46 static struct intc_vect vectors[] __initdata = {
  47         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
  48         INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
  49         INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
  50         INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
  51         INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
  52         INTC_VECT(DMAC_DMAE, 0x6c0),
  53         INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
  54         INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
  55         INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
  56         INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
  57         INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
  58         INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
  59         INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
  60         INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
  61         INTC_VECT(DMABRG2, 0xac0),
  62         INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
  63         INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
  64         INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
  65         INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
  66         INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
  67         INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
  68         INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
  69         INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
  70         INTC_VECT(HSPI, 0xc80),
  71         INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
  72         INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
  73         INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
  74         INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
  75         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  76         INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
  77         INTC_VECT(WDT, 0x560),
  78         INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
  79 };
  80
  81 static struct intc_group groups[] __initdata = {
  82         INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
  83                    DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
  84                    DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
  85         INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
  86         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
  87         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
  88         INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
  89         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
  90         INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
  91         INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
  92         INTC_GROUP(REF, REF_RCMI, REF_ROVI),
  93 };
  94
  95 static struct intc_mask_reg mask_registers[] __initdata = {
  96         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
  97           { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
  98             SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
  99             0, DMABRG0, DMABRG1, DMABRG2,
 100             SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
 101             SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
 102             SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
 103         { 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
 104           { 0, 0, 0, 0, 0, 0, 0, 0,
 105             SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
 106             HSPI, MMCIF0, MMCIF1, MMCIF2,
 107             MMCIF3, 0, 0, 0, 0, 0, 0, 0,
 108             0, MFI, 0, 0, 0, 0, ADC, CMT, } },
 109 };
 110
 111 static struct intc_prio_reg prio_registers[] __initdata = {
 112         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
 113         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
 114         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
 115         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 116         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
 117         { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
 118                                                  HAC0, HAC1, I2C0, I2C1 } },
 119         { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
 120                                                  SCIF1, SCIF2, SIM, HSPI } },
 121         { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
 122                                                  MFI, 0, ADC, CMT } },
 123 };
 124
 125 static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
 126                          mask_registers, prio_registers, NULL);
 127
 128 static struct intc_vect vectors_irq[] __initdata = {
 129         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 130         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 131 };
 132
 133 static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
 134                          mask_registers, prio_registers, NULL);
 135
 136 static struct plat_sci_port sci_platform_data[] = {
 137         {
 138                 .mapbase        = 0xfe600000,
 139                 .flags          = UPF_BOOT_AUTOCONF,
 140                 .type           = PORT_SCIF,
 141                 .irqs           = { 52, 53, 55, 54 },
 142         }, {
 143                 .mapbase        = 0xfe610000,
 144                 .flags          = UPF_BOOT_AUTOCONF,
 145                 .type           = PORT_SCIF,
 146                 .irqs           = { 72, 73, 75, 74 },
 147         }, {
 148                 .mapbase        = 0xfe620000,
 149                 .flags          = UPF_BOOT_AUTOCONF,
 150                 .type           = PORT_SCIF,
 151                 .irqs           = { 76, 77, 79, 78 },
 152         }, {
 153                 .mapbase        = 0xfe480000,
 154                 .flags          = UPF_BOOT_AUTOCONF,
 155                 .type           = PORT_SCI,
 156                 .irqs           = { 80, 81, 82, 0 },
 157         }, {
 158                 .flags = 0,
 159         }
 160 };
 161
 162 static struct platform_device sci_device = {
 163         .name           = "sh-sci",
 164         .id             = -1,
 165         .dev            = {
 166                 .platform_data  = sci_platform_data,
 167         },
 168 };
 169
 170 static struct platform_device *sh7760_devices[] __initdata = {
 171         &sci_device,
 172 };
 173
 174 static int __init sh7760_devices_setup(void)
 175 {
 176         return platform_add_devices(sh7760_devices,
 177                                     ARRAY_SIZE(sh7760_devices));
 178 }
 179 __initcall(sh7760_devices_setup);
 180
 181 void __init plat_irq_setup_pins(int mode)
 182 {
 183         switch (mode) {
 184         case IRQ_MODE_IRQ:
 185                 register_intc_controller(&intc_desc_irq);
 186                 break;
 187         default:
 188                 BUG();
 189         }
 190 }
 191
 192 void __init plat_irq_setup(void)
 193 {
 194         register_intc_controller(&intc_desc);
 195 }