arch/sh/kernel/cpu/sh3/setup-sh7720.c

   1 /*
   2  * SH7720 Setup
   3  *
   4  *  Copyright (C) 2007  Markus Brunner, Mark Jonas
   5  *
   6  *  Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
   7  *
   8  *  Copyright (C) 2006  Paul Mundt
   9  *  Copyright (C) 2006  Jamie Lenehan
  10  *
  11  * This file is subject to the terms and conditions of the GNU General Public
  12  * License.  See the file "COPYING" in the main directory of this archive
  13  * for more details.
  14  */
  15 #include <linux/platform_device.h>
  16 #include <linux/init.h>
  17 #include <linux/serial.h>
  18 #include <linux/io.h>
  19 #include <linux/serial_sci.h>
  20 #include <asm/rtc.h>
  21
  22 #define INTC_ICR1       0xA4140010UL
  23 #define INTC_ICR_IRLM   0x4000
  24 #define INTC_ICR_IRQ    (~INTC_ICR_IRLM)
  25
  26 static struct resource rtc_resources[] = {
  27         [0] = {
  28                 .start  = 0xa413fec0,
  29                 .end    = 0xa413fec0 + 0x28 - 1,
  30                 .flags  = IORESOURCE_IO,
  31         },
  32         [1] = {
  33                 /* Period IRQ */
  34                 .start  = 21,
  35                 .flags  = IORESOURCE_IRQ,
  36         },
  37         [2] = {
  38                 /* Carry IRQ */
  39                 .start  = 22,
  40                 .flags  = IORESOURCE_IRQ,
  41         },
  42         [3] = {
  43                 /* Alarm IRQ */
  44                 .start  = 20,
  45                 .flags  = IORESOURCE_IRQ,
  46         },
  47 };
  48
  49 static struct sh_rtc_platform_info rtc_info = {
  50         .capabilities   = RTC_CAP_4_DIGIT_YEAR,
  51 };
  52
  53 static struct platform_device rtc_device = {
  54         .name           = "sh-rtc",
  55         .id             = -1,
  56         .num_resources  = ARRAY_SIZE(rtc_resources),
  57         .resource       = rtc_resources,
  58         .dev            = {
  59                 .platform_data = &rtc_info,
  60         },
  61 };
  62
  63 static struct plat_sci_port sci_platform_data[] = {
  64         {
  65                 .mapbase        = 0xa4430000,
  66                 .flags          = UPF_BOOT_AUTOCONF,
  67                 .type           = PORT_SCIF,
  68                 .irqs           = { 80, 80, 80, 80 },
  69         }, {
  70                 .mapbase        = 0xa4438000,
  71                 .flags          = UPF_BOOT_AUTOCONF,
  72                 .type           = PORT_SCIF,
  73                 .irqs           = { 81, 81, 81, 81 },
  74         }, {
  75
  76                 .flags = 0,
  77         }
  78 };
  79
  80 static struct platform_device sci_device = {
  81         .name           = "sh-sci",
  82         .id             = -1,
  83         .dev            = {
  84                 .platform_data  = sci_platform_data,
  85         },
  86 };
  87
  88 static struct resource usb_ohci_resources[] = {
  89         [0] = {
  90                 .start  = 0xA4428000,
  91                 .end    = 0xA44280FF,
  92                 .flags  = IORESOURCE_MEM,
  93         },
  94         [1] = {
  95                 .start  = 67,
  96                 .end    = 67,
  97                 .flags  = IORESOURCE_IRQ,
  98         },
  99 };
 100
 101 static u64 usb_ohci_dma_mask = 0xffffffffUL;
 102 static struct platform_device usb_ohci_device = {
 103         .name           = "sh_ohci",
 104         .id             = -1,
 105         .dev = {
 106                 .dma_mask               = &usb_ohci_dma_mask,
 107                 .coherent_dma_mask      = 0xffffffff,
 108         },
 109         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 110         .resource       = usb_ohci_resources,
 111 };
 112
 113 static struct resource usbf_resources[] = {
 114         [0] = {
 115                 .name   = "sh_udc",
 116                 .start  = 0xA4420000,
 117                 .end    = 0xA44200FF,
 118                 .flags  = IORESOURCE_MEM,
 119         },
 120         [1] = {
 121                 .name   = "sh_udc",
 122                 .start  = 65,
 123                 .end    = 65,
 124                 .flags  = IORESOURCE_IRQ,
 125         },
 126 };
 127
 128 static struct platform_device usbf_device = {
 129         .name           = "sh_udc",
 130         .id             = -1,
 131         .dev = {
 132                 .dma_mask               = NULL,
 133                 .coherent_dma_mask      = 0xffffffff,
 134         },
 135         .num_resources  = ARRAY_SIZE(usbf_resources),
 136         .resource       = usbf_resources,
 137 };
 138
 139 static struct platform_device *sh7720_devices[] __initdata = {
 140         &rtc_device,
 141         &sci_device,
 142         &usb_ohci_device,
 143         &usbf_device,
 144 };
 145
 146 static int __init sh7720_devices_setup(void)
 147 {
 148         return platform_add_devices(sh7720_devices,
 149                                     ARRAY_SIZE(sh7720_devices));
 150 }
 151 __initcall(sh7720_devices_setup);
 152
 153 enum {
 154         UNUSED = 0,
 155
 156         /* interrupt sources */
 157         TMU0, TMU1, TMU2, RTC_ATI, RTC_PRI, RTC_CUI,
 158         WDT, REF_RCMI, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
 159         IRQ0, IRQ1, IRQ2, IRQ3,
 160         USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
 161         DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3, LCDC, SSL,
 162         ADC, DMAC2_DEI4, DMAC2_DEI5, USBFI0, USBFI1, CMT,
 163         SCIF0, SCIF1,
 164         PINT07, PINT815, TPU0, TPU1, TPU2, TPU3, IIC,
 165         SIOF0, SIOF1, MMCI0, MMCI1, MMCI2, MMCI3, PCC,
 166         USBHI, AFEIF,
 167         H_UDI,
 168         /* interrupt groups */
 169         TMU, RTC, SIM, DMAC1, USBFI, DMAC2, USB, TPU, MMC,
 170 };
 171
 172 static struct intc_vect vectors[] __initdata = {
 173         INTC_VECT(TMU0, 0x400),       INTC_VECT(TMU1, 0x420),
 174         INTC_VECT(TMU2, 0x440),       INTC_VECT(RTC_ATI, 0x480),
 175         INTC_VECT(RTC_PRI, 0x4a0),    INTC_VECT(RTC_CUI, 0x4c0),
 176         INTC_VECT(SIM_ERI, 0x4e0),    INTC_VECT(SIM_RXI, 0x500),
 177         INTC_VECT(SIM_TXI, 0x520),    INTC_VECT(SIM_TEND, 0x540),
 178         INTC_VECT(WDT, 0x560),        INTC_VECT(REF_RCMI, 0x580),
 179         /* H_UDI cannot be masked */  INTC_VECT(TMU_SUNI, 0x6c0),
 180         INTC_VECT(USBF_SPD, 0x6e0),   INTC_VECT(DMAC1_DEI0, 0x800),
 181         INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840),
 182         INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900),
 183 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
 184         INTC_VECT(SSL, 0x980),
 185 #endif
 186         INTC_VECT(USBFI0, 0xa20),     INTC_VECT(USBFI1, 0xa40),
 187         INTC_VECT(USBHI, 0xa60),
 188         INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0),
 189         INTC_VECT(ADC, 0xbe0),        INTC_VECT(SCIF0, 0xc00),
 190         INTC_VECT(SCIF1, 0xc20),      INTC_VECT(PINT07, 0xc80),
 191         INTC_VECT(PINT815, 0xca0),    INTC_VECT(SIOF0, 0xd00),
 192         INTC_VECT(SIOF1, 0xd20),      INTC_VECT(TPU0, 0xd80),
 193         INTC_VECT(TPU1, 0xda0),       INTC_VECT(TPU2, 0xdc0),
 194         INTC_VECT(TPU3, 0xde0),       INTC_VECT(IIC, 0xe00),
 195         INTC_VECT(MMCI0, 0xe80),      INTC_VECT(MMCI1, 0xea0),
 196         INTC_VECT(MMCI2, 0xec0),      INTC_VECT(MMCI3, 0xee0),
 197         INTC_VECT(CMT, 0xf00),        INTC_VECT(PCC, 0xf60),
 198         INTC_VECT(AFEIF, 0xfe0),
 199 };
 200
 201 static struct intc_group groups[] __initdata = {
 202         INTC_GROUP(TMU, TMU0, TMU1, TMU2),
 203         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 204         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
 205         INTC_GROUP(DMAC1, DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3),
 206         INTC_GROUP(USBFI, USBFI0, USBFI1),
 207         INTC_GROUP(DMAC2, DMAC2_DEI4, DMAC2_DEI5),
 208         INTC_GROUP(TPU, TPU0, TPU1, TPU2, TPU3),
 209         INTC_GROUP(MMC, MMCI0, MMCI1, MMCI2, MMCI3),
 210 };
 211
 212 static struct intc_prio_reg prio_registers[] __initdata = {
 213         { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 214         { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
 215         { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
 216         { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
 217 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
 218         { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
 219 #else
 220         { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, 0 } },
 221 #endif
 222         { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
 223         { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
 224         { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
 225         { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
 226         { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
 227 };
 228
 229 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups,
 230                 NULL, prio_registers, NULL);
 231
 232 static struct intc_sense_reg sense_registers[] __initdata = {
 233         { INTC_ICR1, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
 234 };
 235
 236 static struct intc_vect vectors_irq[] __initdata = {
 237         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 238         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 239         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 240 };
 241
 242 static DECLARE_INTC_DESC(intc_irq_desc, "sh7720-irq", vectors_irq,
 243                 NULL, NULL, prio_registers, sense_registers);
 244
 245 void __init plat_irq_setup_pins(int mode)
 246 {
 247         switch (mode) {
 248         case IRQ_MODE_IRQ:
 249                 ctrl_outw(ctrl_inw(INTC_ICR1) & INTC_ICR_IRQ, INTC_ICR1);
 250                 register_intc_controller(&intc_irq_desc);
 251                 break;
 252         default:
 253                 BUG();
 254         }
 255 }
 256
 257 void __init plat_irq_setup(void)
 258 {
 259         register_intc_controller(&intc_desc);
 260 }