Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / arch / sh / kernel / cpu / sh2 / clock-sh7619.c
blobd2c157917999870078cc79c6b2bdaf431cac76d6
1 /*
2 * arch/sh/kernel/cpu/sh2/clock-sh7619.c
4 * SH7619 support for the clock framework
6 * Copyright (C) 2006 Yoshinori Sato
8 * Based on clock-sh4.c
9 * Copyright (C) 2005 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <asm/clock.h>
18 #include <asm/freq.h>
19 #include <asm/io.h>
21 static const int pll1rate[] = {1,2};
22 static const int pfc_divisors[] = {1,2,0,4};
24 #if (CONFIG_SH_CLK_MD == 1) || (CONFIG_SH_CLK_MD == 2)
25 #define PLL2 (4)
26 #elif (CONFIG_SH_CLK_MD == 5) || (CONFIG_SH_CLK_MD == 6)
27 #define PLL2 (2)
28 #else
29 #error "Illigal Clock Mode!"
30 #endif
32 static void master_clk_init(struct clk *clk)
34 clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
37 static struct clk_ops sh7619_master_clk_ops = {
38 .init = master_clk_init,
41 static void module_clk_recalc(struct clk *clk)
43 int idx = (ctrl_inw(FREQCR) & 0x0007);
44 clk->rate = clk->parent->rate / pfc_divisors[idx];
47 static struct clk_ops sh7619_module_clk_ops = {
48 .recalc = module_clk_recalc,
51 static void bus_clk_recalc(struct clk *clk)
53 clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
56 static struct clk_ops sh7619_bus_clk_ops = {
57 .recalc = bus_clk_recalc,
60 static void cpu_clk_recalc(struct clk *clk)
62 clk->rate = clk->parent->rate;
65 static struct clk_ops sh7619_cpu_clk_ops = {
66 .recalc = cpu_clk_recalc,
69 static struct clk_ops *sh7619_clk_ops[] = {
70 &sh7619_master_clk_ops,
71 &sh7619_module_clk_ops,
72 &sh7619_bus_clk_ops,
73 &sh7619_cpu_clk_ops,
76 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
78 if (idx < ARRAY_SIZE(sh7619_clk_ops))
79 *ops = sh7619_clk_ops[idx];