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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / arch / sh / kernel / cpu / irq / intc.c
blob84806b2027f85525fee1b8569cc898dd1f94ca59
1 /*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007 Magnus Damm
5 *
6 * Based on intc2.c and ipr.c
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
16 * for more details.
17 */
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
21 #include <linux/io.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24
25 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
26 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
27 ((addr_e) << 16) | ((addr_d << 24)))
28
29 #define _INTC_SHIFT(h) (h & 0x1f)
30 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
31 #define _INTC_FN(h) ((h >> 9) & 0xf)
32 #define _INTC_MODE(h) ((h >> 13) & 0x7)
33 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
34 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
35
36 struct intc_handle_int {
37 unsigned int irq;
38 unsigned long handle;
39 };
40
41 struct intc_desc_int {
42 unsigned long *reg;
43 #ifdef CONFIG_SMP
44 unsigned long *smp;
45 #endif
46 unsigned int nr_reg;
47 struct intc_handle_int *prio;
48 unsigned int nr_prio;
49 struct intc_handle_int *sense;
50 unsigned int nr_sense;
51 struct irq_chip chip;
52 };
53
54 #ifdef CONFIG_SMP
55 #define IS_SMP(x) x.smp
56 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
57 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
58 #else
59 #define IS_SMP(x) 0
60 #define INTC_REG(d, x, c) (d->reg[(x)])
61 #define SMP_NR(d, x) 1
62 #endif
63
64 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
65
66 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
67 {
68 struct irq_chip *chip = get_irq_chip(irq);
69 return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
70 }
71
72 static inline unsigned int set_field(unsigned int value,
73 unsigned int field_value,
74 unsigned int handle)
75 {
76 unsigned int width = _INTC_WIDTH(handle);
77 unsigned int shift = _INTC_SHIFT(handle);
78
79 value &= ~(((1 << width) - 1) << shift);
80 value |= field_value << shift;
81 return value;
82 }
83
84 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
85 {
86 ctrl_outb(set_field(0, data, h), addr);
87 }
88
89 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
90 {
91 ctrl_outw(set_field(0, data, h), addr);
92 }
93
94 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
95 {
96 ctrl_outl(set_field(0, data, h), addr);
97 }
98
99 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
100 {
101 ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
102 }
103
104 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
105 {
106 ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
107 }
108
109 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
110 {
111 ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
112 }
113
114 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
115
116 static void (*intc_reg_fns[])(unsigned long addr,
117 unsigned long h,
118 unsigned long data) = {
119 [REG_FN_WRITE_BASE + 0] = write_8,
120 [REG_FN_WRITE_BASE + 1] = write_16,
121 [REG_FN_WRITE_BASE + 3] = write_32,
122 [REG_FN_MODIFY_BASE + 0] = modify_8,
123 [REG_FN_MODIFY_BASE + 1] = modify_16,
124 [REG_FN_MODIFY_BASE + 3] = modify_32,
125 };
126
127 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
128 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
129 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
130 MODE_PRIO_REG, /* Priority value written to enable interrupt */
131 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
132 };
133
134 static void intc_mode_field(unsigned long addr,
135 unsigned long handle,
136 void (*fn)(unsigned long,
137 unsigned long,
138 unsigned long),
139 unsigned int irq)
140 {
141 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
142 }
143
144 static void intc_mode_zero(unsigned long addr,
145 unsigned long handle,
146 void (*fn)(unsigned long,
147 unsigned long,
148 unsigned long),
149 unsigned int irq)
150 {
151 fn(addr, handle, 0);
152 }
153
154 static void intc_mode_prio(unsigned long addr,
155 unsigned long handle,
156 void (*fn)(unsigned long,
157 unsigned long,
158 unsigned long),
159 unsigned int irq)
160 {
161 fn(addr, handle, intc_prio_level[irq]);
162 }
163
164 static void (*intc_enable_fns[])(unsigned long addr,
165 unsigned long handle,
166 void (*fn)(unsigned long,
167 unsigned long,
168 unsigned long),
169 unsigned int irq) = {
170 [MODE_ENABLE_REG] = intc_mode_field,
171 [MODE_MASK_REG] = intc_mode_zero,
172 [MODE_DUAL_REG] = intc_mode_field,
173 [MODE_PRIO_REG] = intc_mode_prio,
174 [MODE_PCLR_REG] = intc_mode_prio,
175 };
176
177 static void (*intc_disable_fns[])(unsigned long addr,
178 unsigned long handle,
179 void (*fn)(unsigned long,
180 unsigned long,
181 unsigned long),
182 unsigned int irq) = {
183 [MODE_ENABLE_REG] = intc_mode_zero,
184 [MODE_MASK_REG] = intc_mode_field,
185 [MODE_DUAL_REG] = intc_mode_field,
186 [MODE_PRIO_REG] = intc_mode_zero,
187 [MODE_PCLR_REG] = intc_mode_field,
188 };
189
190 static inline void _intc_enable(unsigned int irq, unsigned long handle)
191 {
192 struct intc_desc_int *d = get_intc_desc(irq);
193 unsigned long addr;
194 unsigned int cpu;
195
196 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
197 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
198 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
199 [_INTC_FN(handle)], irq);
200 }
201 }
202
203 static void intc_enable(unsigned int irq)
204 {
205 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
206 }
207
208 static void intc_disable(unsigned int irq)
209 {
210 struct intc_desc_int *d = get_intc_desc(irq);
211 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
212 unsigned long addr;
213 unsigned int cpu;
214
215 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
216 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
217 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
218 [_INTC_FN(handle)], irq);
219 }
220 }
221
222 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
223 unsigned int nr_hp,
224 unsigned int irq)
225 {
226 int i;
227
228 /* this doesn't scale well, but...
229 *
230 * this function should only be used for cerain uncommon
231 * operations such as intc_set_priority() and intc_set_sense()
232 * and in those rare cases performance doesn't matter that much.
233 * keeping the memory footprint low is more important.
234 *
235 * one rather simple way to speed this up and still keep the
236 * memory footprint down is to make sure the array is sorted
237 * and then perform a bisect to lookup the irq.
238 */
239
240 for (i = 0; i < nr_hp; i++) {
241 if ((hp + i)->irq != irq)
242 continue;
243
244 return hp + i;
245 }
246
247 return NULL;
248 }
249
250 int intc_set_priority(unsigned int irq, unsigned int prio)
251 {
252 struct intc_desc_int *d = get_intc_desc(irq);
253 struct intc_handle_int *ihp;
254
255 if (!intc_prio_level[irq] || prio <= 1)
256 return -EINVAL;
257
258 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
259 if (ihp) {
260 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
261 return -EINVAL;
262
263 intc_prio_level[irq] = prio;
264
265 /*
266 * only set secondary masking method directly
267 * primary masking method is using intc_prio_level[irq]
268 * priority level will be set during next enable()
269 */
270
271 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
272 _intc_enable(irq, ihp->handle);
273 }
274 return 0;
275 }
276
277 #define VALID(x) (x | 0x80)
278
279 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
280 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
281 [IRQ_TYPE_EDGE_RISING] = VALID(1),
282 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
283 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
284 };
285
286 static int intc_set_sense(unsigned int irq, unsigned int type)
287 {
288 struct intc_desc_int *d = get_intc_desc(irq);
289 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
290 struct intc_handle_int *ihp;
291 unsigned long addr;
292
293 if (!value)
294 return -EINVAL;
295
296 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
297 if (ihp) {
298 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
299 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
300 }
301 return 0;
302 }
303
304 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
305 unsigned long address)
306 {
307 unsigned int k;
308
309 for (k = 0; k < d->nr_reg; k++) {
310 if (d->reg[k] == address)
311 return k;
312 }
313
314 BUG();
315 return 0;
316 }
317
318 static intc_enum __init intc_grp_id(struct intc_desc *desc,
319 intc_enum enum_id)
320 {
321 struct intc_group *g = desc->groups;
322 unsigned int i, j;
323
324 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
325 g = desc->groups + i;
326
327 for (j = 0; g->enum_ids[j]; j++) {
328 if (g->enum_ids[j] != enum_id)
329 continue;
330
331 return g->enum_id;
332 }
333 }
334
335 return 0;
336 }
337
338 static unsigned int __init intc_mask_data(struct intc_desc *desc,
339 struct intc_desc_int *d,
340 intc_enum enum_id, int do_grps)
341 {
342 struct intc_mask_reg *mr = desc->mask_regs;
343 unsigned int i, j, fn, mode;
344 unsigned long reg_e, reg_d;
345
346 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
347 mr = desc->mask_regs + i;
348
349 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
350 if (mr->enum_ids[j] != enum_id)
351 continue;
352
353 if (mr->set_reg && mr->clr_reg) {
354 fn = REG_FN_WRITE_BASE;
355 mode = MODE_DUAL_REG;
356 reg_e = mr->clr_reg;
357 reg_d = mr->set_reg;
358 } else {
359 fn = REG_FN_MODIFY_BASE;
360 if (mr->set_reg) {
361 mode = MODE_ENABLE_REG;
362 reg_e = mr->set_reg;
363 reg_d = mr->set_reg;
364 } else {
365 mode = MODE_MASK_REG;
366 reg_e = mr->clr_reg;
367 reg_d = mr->clr_reg;
368 }
369 }
370
371 fn += (mr->reg_width >> 3) - 1;
372 return _INTC_MK(fn, mode,
373 intc_get_reg(d, reg_e),
374 intc_get_reg(d, reg_d),
375 1,
376 (mr->reg_width - 1) - j);
377 }
378 }
379
380 if (do_grps)
381 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
382
383 return 0;
384 }
385
386 static unsigned int __init intc_prio_data(struct intc_desc *desc,
387 struct intc_desc_int *d,
388 intc_enum enum_id, int do_grps)
389 {
390 struct intc_prio_reg *pr = desc->prio_regs;
391 unsigned int i, j, fn, mode, bit;
392 unsigned long reg_e, reg_d;
393
394 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
395 pr = desc->prio_regs + i;
396
397 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
398 if (pr->enum_ids[j] != enum_id)
399 continue;
400
401 if (pr->set_reg && pr->clr_reg) {
402 fn = REG_FN_WRITE_BASE;
403 mode = MODE_PCLR_REG;
404 reg_e = pr->set_reg;
405 reg_d = pr->clr_reg;
406 } else {
407 fn = REG_FN_MODIFY_BASE;
408 mode = MODE_PRIO_REG;
409 if (!pr->set_reg)
410 BUG();
411 reg_e = pr->set_reg;
412 reg_d = pr->set_reg;
413 }
414
415 fn += (pr->reg_width >> 3) - 1;
416 bit = pr->reg_width - ((j + 1) * pr->field_width);
417
418 BUG_ON(bit < 0);
419
420 return _INTC_MK(fn, mode,
421 intc_get_reg(d, reg_e),
422 intc_get_reg(d, reg_d),
423 pr->field_width, bit);
424 }
425 }
426
427 if (do_grps)
428 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
429
430 return 0;
431 }
432
433 static unsigned int __init intc_sense_data(struct intc_desc *desc,
434 struct intc_desc_int *d,
435 intc_enum enum_id)
436 {
437 struct intc_sense_reg *sr = desc->sense_regs;
438 unsigned int i, j, fn, bit;
439
440 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
441 sr = desc->sense_regs + i;
442
443 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
444 if (sr->enum_ids[j] != enum_id)
445 continue;
446
447 fn = REG_FN_MODIFY_BASE;
448 fn += (sr->reg_width >> 3) - 1;
449 bit = sr->reg_width - ((j + 1) * sr->field_width);
450
451 BUG_ON(bit < 0);
452
453 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
454 0, sr->field_width, bit);
455 }
456 }
457
458 return 0;
459 }
460
461 static void __init intc_register_irq(struct intc_desc *desc,
462 struct intc_desc_int *d,
463 intc_enum enum_id,
464 unsigned int irq)
465 {
466 struct intc_handle_int *hp;
467 unsigned int data[2], primary;
468
469 /* Prefer single interrupt source bitmap over other combinations:
470 * 1. bitmap, single interrupt source
471 * 2. priority, single interrupt source
472 * 3. bitmap, multiple interrupt sources (groups)
473 * 4. priority, multiple interrupt sources (groups)
474 */
475
476 data[0] = intc_mask_data(desc, d, enum_id, 0);
477 data[1] = intc_prio_data(desc, d, enum_id, 0);
478
479 primary = 0;
480 if (!data[0] && data[1])
481 primary = 1;
482
483 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
484 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
485
486 if (!data[primary])
487 primary ^= 1;
488
489 BUG_ON(!data[primary]); /* must have primary masking method */
490
491 disable_irq_nosync(irq);
492 set_irq_chip_and_handler_name(irq, &d->chip,
493 handle_level_irq, "level");
494 set_irq_chip_data(irq, (void *)data[primary]);
495
496 /* set priority level
497 * - this needs to be at least 2 for 5-bit priorities on 7780
498 */
499 intc_prio_level[irq] = 2;
500
501 /* enable secondary masking method if present */
502 if (data[!primary])
503 _intc_enable(irq, data[!primary]);
504
505 /* add irq to d->prio list if priority is available */
506 if (data[1]) {
507 hp = d->prio + d->nr_prio;
508 hp->irq = irq;
509 hp->handle = data[1];
510
511 if (primary) {
512 /*
513 * only secondary priority should access registers, so
514 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
515 */
516
517 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
518 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
519 }
520 d->nr_prio++;
521 }
522
523 /* add irq to d->sense list if sense is available */
524 data[0] = intc_sense_data(desc, d, enum_id);
525 if (data[0]) {
526 (d->sense + d->nr_sense)->irq = irq;
527 (d->sense + d->nr_sense)->handle = data[0];
528 d->nr_sense++;
529 }
530
531 /* irq should be disabled by default */
532 d->chip.mask(irq);
533 }
534
535 static unsigned int __init save_reg(struct intc_desc_int *d,
536 unsigned int cnt,
537 unsigned long value,
538 unsigned int smp)
539 {
540 if (value) {
541 d->reg[cnt] = value;
542 #ifdef CONFIG_SMP
543 d->smp[cnt] = smp;
544 #endif
545 return 1;
546 }
547
548 return 0;
549 }
550
551
552 void __init register_intc_controller(struct intc_desc *desc)
553 {
554 unsigned int i, k, smp;
555 struct intc_desc_int *d;
556
557 d = alloc_bootmem(sizeof(*d));
558
559 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
560 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
561 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
562
563 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
564 #ifdef CONFIG_SMP
565 d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
566 #endif
567 k = 0;
568
569 if (desc->mask_regs) {
570 for (i = 0; i < desc->nr_mask_regs; i++) {
571 smp = IS_SMP(desc->mask_regs[i]);
572 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
573 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
574 }
575 }
576
577 if (desc->prio_regs) {
578 d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
579
580 for (i = 0; i < desc->nr_prio_regs; i++) {
581 smp = IS_SMP(desc->prio_regs[i]);
582 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
583 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
584 }
585 }
586
587 if (desc->sense_regs) {
588 d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
589
590 for (i = 0; i < desc->nr_sense_regs; i++) {
591 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
592 }
593 }
594
595 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
596
597 d->chip.name = desc->name;
598 d->chip.mask = intc_disable;
599 d->chip.unmask = intc_enable;
600 d->chip.mask_ack = intc_disable;
601 d->chip.set_type = intc_set_sense;
602
603 for (i = 0; i < desc->nr_vectors; i++) {
604 struct intc_vect *vect = desc->vectors + i;
605
606 intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
607 }
608 }
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