arch/ppc/platforms/4xx/ibmstbx25.h

   1 /*
   2  * Author: Armin Kuster <akuster@mvista.com>
   3  *
   4  * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
   5  * the terms of the GNU General Public License version 2.  This program
   6  * is licensed "as is" without any warranty of any kind, whether express
   7  * or implied.
   8  */
   9
  10 #ifdef __KERNEL__
  11 #ifndef __ASM_IBMSTBX25_H__
  12 #define __ASM_IBMSTBX25_H__
  13
  14
  15 /* serial port defines */
  16 #define STBx25xx_IO_BASE        ((uint)0xe0000000)
  17 #define PPC4xx_ONB_IO_PADDR     STBx25xx_IO_BASE
  18 #define PPC4xx_ONB_IO_VADDR     ((uint)0xe0000000)
  19 #define PPC4xx_ONB_IO_SIZE      ((uint)14*64*1024)
  20
  21 /*
  22  * map STBxxxx internal i/o address (0x400x00xx) to an address
  23  * which is below the 2GB limit...
  24  *
  25  * 4000 000x    uart1           -> 0xe000 000x
  26  * 4001 00xx    uart2
  27  * 4002 00xx    smart card
  28  * 4003 000x    iic
  29  * 4004 000x    uart0
  30  * 4005 0xxx    timer
  31  * 4006 00xx    gpio
  32  * 4007 00xx    smart card
  33  * 400b 000x    iic
  34  * 400c 000x    scp
  35  * 400d 000x    modem
  36  * 400e 000x    uart2
  37 */
  38 #define STBx25xx_MAP_IO_ADDR(a) (((uint)(a)) + (STBx25xx_IO_BASE - 0x40000000))
  39
  40 #define RS_TABLE_SIZE   3
  41
  42 #define OPB_BASE_START  0x40000000
  43 #define EBIU_BASE_START 0xF0100000
  44 #define DCR_BASE_START  0x0000
  45
  46 #ifdef __BOOTER__
  47 #define UART1_IO_BASE   0x40000000
  48 #define UART2_IO_BASE   0x40010000
  49 #else
  50 #define UART1_IO_BASE   0xe0000000
  51 #define UART2_IO_BASE   0xe0010000
  52 #endif
  53 #define SC0_BASE        0x40020000      /* smart card #0 */
  54 #define IIC0_BASE       0x40030000
  55 #ifdef __BOOTER__
  56 #define UART0_IO_BASE   0x40040000
  57 #else
  58 #define UART0_IO_BASE   0xe0040000
  59 #endif
  60 #define SCC0_BASE       0x40040000      /* Serial 0 controller IrdA */
  61 #define GPT0_BASE       0x40050000      /* General purpose timers */
  62 #define GPIO0_BASE      0x40060000
  63 #define SC1_BASE        0x40070000      /* smart card #1 */
  64 #define SCP0_BASE       0x400C0000      /* Serial Controller Port */
  65 #define SSP0_BASE       0x400D0000      /* Sync serial port */
  66
  67 #define IDE0_BASE               0xf0100000
  68 #define REDWOOD_IDE_CTRL        0xf1100000
  69
  70 #define RTCFPC_IRQ      0
  71 #define XPORT_IRQ       1
  72 #define AUD_IRQ         2
  73 #define AID_IRQ         3
  74 #define DMA0            4
  75 #define DMA1_IRQ        5
  76 #define DMA2_IRQ        6
  77 #define DMA3_IRQ        7
  78 #define SC0_IRQ         8
  79 #define IIC0_IRQ        9
  80 #define IIR0_IRQ        10
  81 #define GPT0_IRQ        11
  82 #define GPT1_IRQ        12
  83 #define SCP0_IRQ        13
  84 #define SSP0_IRQ        14
  85 #define GPT2_IRQ        15      /* count down timer */
  86 #define SC1_IRQ         16
  87 /* IRQ 17 - 19  external */
  88 #define UART0_INT       20
  89 #define UART1_INT       21
  90 #define UART2_INT       22
  91 #define XPTDMA_IRQ      23
  92 #define DCRIDE_IRQ      24
  93 /* IRQ 25 - 30 external */
  94 #define IDE0_IRQ        26
  95
  96 #define IIC_NUMS        1
  97 #define UART_NUMS       3
  98 #define IIC_OWN         0x55
  99 #define IIC_CLOCK       50
 100
 101 #define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
 102
 103 #define STD_UART_OP(num)                                        \
 104         { 0, BASE_BAUD, 0, UART##num##_INT,                     \
 105                 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),        \
 106                 iomem_base: (u8 *)UART##num##_IO_BASE,          \
 107                 io_type: SERIAL_IO_MEM},
 108
 109 #if defined(CONFIG_UART0_TTYS0)
 110 #define SERIAL_DEBUG_IO_BASE    UART0_IO_BASE
 111 #define SERIAL_PORT_DFNS        \
 112         STD_UART_OP(0)          \
 113         STD_UART_OP(1)          \
 114         STD_UART_OP(2)
 115 #endif
 116
 117 #if defined(CONFIG_UART0_TTYS1)
 118 #define SERIAL_DEBUG_IO_BASE    UART2_IO_BASE
 119 #define SERIAL_PORT_DFNS        \
 120         STD_UART_OP(1)          \
 121         STD_UART_OP(0)          \
 122         STD_UART_OP(2)
 123 #endif
 124
 125 #if defined(CONFIG_UART0_TTYS2)
 126 #define SERIAL_DEBUG_IO_BASE    UART2_IO_BASE
 127 #define SERIAL_PORT_DFNS        \
 128         STD_UART_OP(2)          \
 129         STD_UART_OP(0)          \
 130         STD_UART_OP(1)
 131 #endif
 132
 133 #define DCRN_BE_BASE            0x090
 134 #define DCRN_DMA0_BASE          0x0C0
 135 #define DCRN_DMA1_BASE          0x0C8
 136 #define DCRN_DMA2_BASE          0x0D0
 137 #define DCRN_DMA3_BASE          0x0D8
 138 #define DCRNCAP_DMA_CC          1       /* have DMA chained count capability */
 139 #define DCRN_DMASR_BASE         0x0E0
 140 #define DCRN_PLB0_BASE          0x054
 141 #define DCRN_PLB1_BASE          0x064
 142 #define DCRN_POB0_BASE          0x0B0
 143 #define DCRN_SCCR_BASE          0x120
 144 #define DCRN_UIC0_BASE          0x040
 145 #define DCRN_BE_BASE            0x090
 146 #define DCRN_DMA0_BASE          0x0C0
 147 #define DCRN_DMA1_BASE          0x0C8
 148 #define DCRN_DMA2_BASE          0x0D0
 149 #define DCRN_DMA3_BASE          0x0D8
 150 #define DCRN_CIC_BASE           0x030
 151 #define DCRN_DMASR_BASE         0x0E0
 152 #define DCRN_EBIMC_BASE         0x070
 153 #define DCRN_DCRX_BASE          0x020
 154 #define DCRN_CPMFR_BASE         0x102
 155 #define DCRN_SCCR_BASE          0x120
 156 #define DCRN_RTCFP_BASE         0x310
 157
 158 #define UIC0 DCRN_UIC0_BASE
 159
 160 #define IBM_CPM_IIC0    0x80000000      /* IIC 0 interface */
 161 #define IBM_CPM_CPU     0x10000000      /* PPC405B3 clock control */
 162 #define IBM_CPM_AUD     0x08000000      /* Audio Decoder */
 163 #define IBM_CPM_EBIU    0x04000000      /* External Bus Interface Unit */
 164 #define IBM_CPM_IRR     0x02000000      /* Infrared receiver */
 165 #define IBM_CPM_DMA     0x01000000      /* DMA controller */
 166 #define IBM_CPM_UART2   0x00200000      /* Serial Control Port */
 167 #define IBM_CPM_UART1   0x00100000      /* Serial 1 / Infrared */
 168 #define IBM_CPM_UART0   0x00080000      /* Serial 0 / 16550 */
 169 #define IBM_PM_DCRIDE   0x00040000      /* DCR timeout & IDE line Mode clock */
 170 #define IBM_CPM_SC0     0x00020000      /* Smart Card 0 */
 171 #define IBM_CPM_VID     0x00010000      /* reserved */
 172 #define IBM_CPM_SC1     0x00008000      /* Smart Card 0 */
 173 #define IBM_CPM_XPT0    0x00002000      /* Transport - 54 Mhz */
 174 #define IBM_CPM_CBS     0x00001000      /* Cross Bar Switch */
 175 #define IBM_CPM_GPT     0x00000800      /* GPTPWM */
 176 #define IBM_CPM_GPIO0   0x00000400      /* General Purpose IO 0 */
 177 #define IBM_CPM_DENC    0x00000200      /* Digital video Encoder */
 178 #define IBM_CPM_C405T   0x00000100      /* CPU timers */
 179 #define IBM_CPM_XPT27   0x00000080      /* Transport - 27 Mhz */
 180 #define IBM_CPM_UIC     0x00000040      /* Universal Interrupt Controller */
 181 #define IBM_CPM_RTCFPC  0x00000020      /* Realtime clock and front panel */
 182 #define IBM_CPM_SSP     0x00000010      /* Modem Serial Interface (SSP) */
 183 #define IBM_CPM_VID2    0x00000002      /* Video Decoder clock domain 2 */
 184 #define DFLT_IBM4xx_PM  ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_DMA      \
 185                         | IBM_CPM_CBS | IBM_CPM_XPT0 | IBM_CPM_C405T    \
 186                         | IBM_CPM_XPT27 | IBM_CPM_UIC)
 187
 188 #define DCRN_BEAR       (DCRN_BE_BASE + 0x0)    /* Bus Error Address Register */
 189 #define DCRN_BESR       (DCRN_BE_BASE + 0x1)    /* Bus Error Syndrome Register */
 190 /* DCRN_BESR */
 191 #define BESR_DSES       0x80000000      /* Data-Side Error Status */
 192 #define BESR_DMES       0x40000000      /* DMA Error Status */
 193 #define BESR_RWS        0x20000000      /* Read/Write Status */
 194 #define BESR_ETMASK     0x1C000000      /* Error Type */
 195 #define ET_PROT         0
 196 #define ET_PARITY       1
 197 #define ET_NCFG         2
 198 #define ET_BUSERR       4
 199 #define ET_BUSTO        6
 200
 201 #define CHR1_CETE       0x00800000      /* CPU external timer enable */
 202 #define CHR1_PCIPW      0x00008000      /* PCI Int enable/Peripheral Write enable */
 203
 204 #define DCRN_CICCR      (DCRN_CIC_BASE + 0x0)   /* CIC Control Register */
 205 #define DCRN_DMAS1      (DCRN_CIC_BASE + 0x1)   /* DMA Select1 Register */
 206 #define DCRN_DMAS2      (DCRN_CIC_BASE + 0x2)   /* DMA Select2 Register */
 207 #define DCRN_CICVCR     (DCRN_CIC_BASE + 0x3)   /* CIC Video COntro Register */
 208 #define DCRN_CICSEL3    (DCRN_CIC_BASE + 0x5)   /* CIC Select 3 Register */
 209 #define DCRN_SGPO       (DCRN_CIC_BASE + 0x6)   /* CIC GPIO Output Register */
 210 #define DCRN_SGPOD      (DCRN_CIC_BASE + 0x7)   /* CIC GPIO OD Register */
 211 #define DCRN_SGPTC      (DCRN_CIC_BASE + 0x8)   /* CIC GPIO Tristate Ctrl Reg */
 212 #define DCRN_SGPI       (DCRN_CIC_BASE + 0x9)   /* CIC GPIO Input Reg */
 213
 214 #define DCRN_DCRXICR    (DCRN_DCRX_BASE + 0x0)  /* Internal Control Register */
 215 #define DCRN_DCRXISR    (DCRN_DCRX_BASE + 0x1)  /* Internal Status Register */
 216 #define DCRN_DCRXECR    (DCRN_DCRX_BASE + 0x2)  /* External Control Register */
 217 #define DCRN_DCRXESR    (DCRN_DCRX_BASE + 0x3)  /* External Status Register */
 218 #define DCRN_DCRXTAR    (DCRN_DCRX_BASE + 0x4)  /* Target Address Register */
 219 #define DCRN_DCRXTDR    (DCRN_DCRX_BASE + 0x5)  /* Target Data Register */
 220 #define DCRN_DCRXIGR    (DCRN_DCRX_BASE + 0x6)  /* Interrupt Generation Register */
 221 #define DCRN_DCRXBCR    (DCRN_DCRX_BASE + 0x7)  /* Line Buffer Control Register */
 222
 223 #define DCRN_BRCRH0     (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
 224 #define DCRN_BRCRH1     (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
 225 #define DCRN_BRCRH2     (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
 226 #define DCRN_BRCRH3     (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
 227 #define DCRN_BRCRH4     (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
 228 #define DCRN_BRCRH5     (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
 229 #define DCRN_BRCRH6     (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
 230 #define DCRN_BRCRH7     (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
 231 #define DCRN_BRCR0      (DCRN_EBIMC_BASE + 0x10)        /* BRC 0 */
 232 #define DCRN_BRCR1      (DCRN_EBIMC_BASE + 0x11)        /* BRC 1 */
 233 #define DCRN_BRCR2      (DCRN_EBIMC_BASE + 0x12)        /* BRC 2 */
 234 #define DCRN_BRCR3      (DCRN_EBIMC_BASE + 0x13)        /* BRC 3 */
 235 #define DCRN_BRCR4      (DCRN_EBIMC_BASE + 0x14)        /* BRC 4 */
 236 #define DCRN_BRCR5      (DCRN_EBIMC_BASE + 0x15)        /* BRC 5 */
 237 #define DCRN_BRCR6      (DCRN_EBIMC_BASE + 0x16)        /* BRC 6 */
 238 #define DCRN_BRCR7      (DCRN_EBIMC_BASE + 0x17)        /* BRC 7 */
 239 #define DCRN_BEAR0      (DCRN_EBIMC_BASE + 0x20)        /* Bus Error Address Register */
 240 #define DCRN_BESR0      (DCRN_EBIMC_BASE + 0x21)        /* Bus Error Status Register */
 241 #define DCRN_BIUCR      (DCRN_EBIMC_BASE + 0x2A)        /* Bus Interfac Unit Ctrl Reg */
 242
 243 #define DCRN_RTC_FPC0_CNTL      (DCRN_RTCFP_BASE + 0x00)        /* RTC cntl */
 244 #define DCRN_RTC_FPC0_INT       (DCRN_RTCFP_BASE + 0x01)        /* RTC Interrupt */
 245 #define DCRN_RTC_FPC0_TIME      (DCRN_RTCFP_BASE + 0x02)        /* RTC time reg */
 246 #define DCRN_RTC_FPC0_ALRM      (DCRN_RTCFP_BASE + 0x03)        /* RTC Alarm reg */
 247 #define DCRN_RTC_FPC0_D1        (DCRN_RTCFP_BASE + 0x04)        /* LED Data 1 */
 248 #define DCRN_RTC_FPC0_D2        (DCRN_RTCFP_BASE + 0x05)        /* LED Data 2 */
 249 #define DCRN_RTC_FPC0_D3        (DCRN_RTCFP_BASE + 0x06)        /* LED Data 3 */
 250 #define DCRN_RTC_FPC0_D4        (DCRN_RTCFP_BASE + 0x07)        /* LED Data 4 */
 251 #define DCRN_RTC_FPC0_D5        (DCRN_RTCFP_BASE + 0x08)        /* LED Data 5 */
 252 #define DCRN_RTC_FPC0_FCNTL     (DCRN_RTCFP_BASE + 0x09)        /* LED control */
 253 #define DCRN_RTC_FPC0_BRT       (DCRN_RTCFP_BASE + 0x0A)        /* Brightness cntl */
 254
 255 #include <asm/ibm405.h>
 256
 257 #endif                          /* __ASM_IBMSTBX25_H__ */
 258 #endif                          /* __KERNEL__ */