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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / arch / powerpc / sysdev / ppc4xx_pci.c
blob5abfcd157483b509e0f1c99ad0eacd693e05fb72
1 /*
2 * PCI / PCI-X / PCI-Express support for 4xx parts
3 *
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
5 *
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
8 *
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
10 *
11 * Some of that comes itself from a previous implementation for 440SPE only
12 * by Roland Dreier:
13 *
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
16 *
17 */
18
19 #undef DEBUG
20
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/of.h>
25 #include <linux/bootmem.h>
26 #include <linux/delay.h>
27
28 #include <asm/io.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
31 #include <asm/dcr.h>
32 #include <asm/dcr-regs.h>
33
34 #include "ppc4xx_pci.h"
35
36 static int dma_offset_set;
37
38 /* Move that to a useable header */
39 extern unsigned long total_memory;
40
41 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
42 #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
43
44 #ifdef CONFIG_RESOURCES_64BIT
45 #define RES_TO_U32_LOW(val) U64_TO_U32_LOW(val)
46 #define RES_TO_U32_HIGH(val) U64_TO_U32_HIGH(val)
47 #else
48 #define RES_TO_U32_LOW(val) (val)
49 #define RES_TO_U32_HIGH(val) (0)
50 #endif
51
52 static inline int ppc440spe_revA(void)
53 {
54 /* Catch both 440SPe variants, with and without RAID6 support */
55 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
56 return 1;
57 else
58 return 0;
59 }
60
61 static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
62 {
63 struct pci_controller *hose;
64 int i;
65
66 if (dev->devfn != 0 || dev->bus->self != NULL)
67 return;
68
69 hose = pci_bus_to_host(dev->bus);
70 if (hose == NULL)
71 return;
72
73 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
74 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
75 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
76 return;
77
78 /* Hide the PCI host BARs from the kernel as their content doesn't
79 * fit well in the resource management
80 */
81 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
82 dev->resource[i].start = dev->resource[i].end = 0;
83 dev->resource[i].flags = 0;
84 }
85
86 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
87 pci_name(dev));
88 }
89 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
90
91 static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
92 void __iomem *reg,
93 struct resource *res)
94 {
95 u64 size;
96 const u32 *ranges;
97 int rlen;
98 int pna = of_n_addr_cells(hose->dn);
99 int np = pna + 5;
100
101 /* Default */
102 res->start = 0;
103 res->end = size = 0x80000000;
104 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
105
106 /* Get dma-ranges property */
107 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
108 if (ranges == NULL)
109 goto out;
110
111 /* Walk it */
112 while ((rlen -= np * 4) >= 0) {
113 u32 pci_space = ranges[0];
114 u64 pci_addr = of_read_number(ranges + 1, 2);
115 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
116 size = of_read_number(ranges + pna + 3, 2);
117 ranges += np;
118 if (cpu_addr == OF_BAD_ADDR || size == 0)
119 continue;
120
121 /* We only care about memory */
122 if ((pci_space & 0x03000000) != 0x02000000)
123 continue;
124
125 /* We currently only support memory at 0, and pci_addr
126 * within 32 bits space
127 */
128 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
129 printk(KERN_WARNING "%s: Ignored unsupported dma range"
130 " 0x%016llx...0x%016llx -> 0x%016llx\n",
131 hose->dn->full_name,
132 pci_addr, pci_addr + size - 1, cpu_addr);
133 continue;
134 }
135
136 /* Check if not prefetchable */
137 if (!(pci_space & 0x40000000))
138 res->flags &= ~IORESOURCE_PREFETCH;
139
140
141 /* Use that */
142 res->start = pci_addr;
143 #ifndef CONFIG_RESOURCES_64BIT
144 /* Beware of 32 bits resources */
145 if ((pci_addr + size) > 0x100000000ull)
146 res->end = 0xffffffff;
147 else
148 #endif
149 res->end = res->start + size - 1;
150 break;
151 }
152
153 /* We only support one global DMA offset */
154 if (dma_offset_set && pci_dram_offset != res->start) {
155 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
156 hose->dn->full_name);
157 return -ENXIO;
158 }
159
160 /* Check that we can fit all of memory as we don't support
161 * DMA bounce buffers
162 */
163 if (size < total_memory) {
164 printk(KERN_ERR "%s: dma-ranges too small "
165 "(size=%llx total_memory=%lx)\n",
166 hose->dn->full_name, size, total_memory);
167 return -ENXIO;
168 }
169
170 /* Check we are a power of 2 size and that base is a multiple of size*/
171 if (!is_power_of_2(size) ||
172 (res->start & (size - 1)) != 0) {
173 printk(KERN_ERR "%s: dma-ranges unaligned\n",
174 hose->dn->full_name);
175 return -ENXIO;
176 }
177
178 /* Check that we are fully contained within 32 bits space */
179 if (res->end > 0xffffffff) {
180 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
181 hose->dn->full_name);
182 return -ENXIO;
183 }
184 out:
185 dma_offset_set = 1;
186 pci_dram_offset = res->start;
187
188 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
189 pci_dram_offset);
190 return 0;
191 }
192
193 /*
194 * 4xx PCI 2.x part
195 */
196
197 static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
198 void __iomem *reg)
199 {
200 u32 la, ma, pcila, pciha;
201 int i, j;
202
203 /* Setup outbound memory windows */
204 for (i = j = 0; i < 3; i++) {
205 struct resource *res = &hose->mem_resources[i];
206
207 /* we only care about memory windows */
208 if (!(res->flags & IORESOURCE_MEM))
209 continue;
210 if (j > 2) {
211 printk(KERN_WARNING "%s: Too many ranges\n",
212 hose->dn->full_name);
213 break;
214 }
215
216 /* Calculate register values */
217 la = res->start;
218 pciha = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
219 pcila = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
220
221 ma = res->end + 1 - res->start;
222 if (!is_power_of_2(ma) || ma < 0x1000 || ma > 0xffffffffu) {
223 printk(KERN_WARNING "%s: Resource out of range\n",
224 hose->dn->full_name);
225 continue;
226 }
227 ma = (0xffffffffu << ilog2(ma)) | 0x1;
228 if (res->flags & IORESOURCE_PREFETCH)
229 ma |= 0x2;
230
231 /* Program register values */
232 writel(la, reg + PCIL0_PMM0LA + (0x10 * j));
233 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * j));
234 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * j));
235 writel(ma, reg + PCIL0_PMM0MA + (0x10 * j));
236 j++;
237 }
238 }
239
240 static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
241 void __iomem *reg,
242 const struct resource *res)
243 {
244 resource_size_t size = res->end - res->start + 1;
245 u32 sa;
246
247 /* Calculate window size */
248 sa = (0xffffffffu << ilog2(size)) | 1;
249 sa |= 0x1;
250
251 /* RAM is always at 0 local for now */
252 writel(0, reg + PCIL0_PTM1LA);
253 writel(sa, reg + PCIL0_PTM1MS);
254
255 /* Map on PCI side */
256 early_write_config_dword(hose, hose->first_busno, 0,
257 PCI_BASE_ADDRESS_1, res->start);
258 early_write_config_dword(hose, hose->first_busno, 0,
259 PCI_BASE_ADDRESS_2, 0x00000000);
260 early_write_config_word(hose, hose->first_busno, 0,
261 PCI_COMMAND, 0x0006);
262 }
263
264 static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
265 {
266 /* NYI */
267 struct resource rsrc_cfg;
268 struct resource rsrc_reg;
269 struct resource dma_window;
270 struct pci_controller *hose = NULL;
271 void __iomem *reg = NULL;
272 const int *bus_range;
273 int primary = 0;
274
275 /* Fetch config space registers address */
276 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
277 printk(KERN_ERR "%s:Can't get PCI config register base !",
278 np->full_name);
279 return;
280 }
281 /* Fetch host bridge internal registers address */
282 if (of_address_to_resource(np, 3, &rsrc_reg)) {
283 printk(KERN_ERR "%s: Can't get PCI internal register base !",
284 np->full_name);
285 return;
286 }
287
288 /* Check if primary bridge */
289 if (of_get_property(np, "primary", NULL))
290 primary = 1;
291
292 /* Get bus range if any */
293 bus_range = of_get_property(np, "bus-range", NULL);
294
295 /* Map registers */
296 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
297 if (reg == NULL) {
298 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
299 goto fail;
300 }
301
302 /* Allocate the host controller data structure */
303 hose = pcibios_alloc_controller(np);
304 if (!hose)
305 goto fail;
306
307 hose->first_busno = bus_range ? bus_range[0] : 0x0;
308 hose->last_busno = bus_range ? bus_range[1] : 0xff;
309
310 /* Setup config space */
311 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
312
313 /* Disable all windows */
314 writel(0, reg + PCIL0_PMM0MA);
315 writel(0, reg + PCIL0_PMM1MA);
316 writel(0, reg + PCIL0_PMM2MA);
317 writel(0, reg + PCIL0_PTM1MS);
318 writel(0, reg + PCIL0_PTM2MS);
319
320 /* Parse outbound mapping resources */
321 pci_process_bridge_OF_ranges(hose, np, primary);
322
323 /* Parse inbound mapping resources */
324 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
325 goto fail;
326
327 /* Configure outbound ranges POMs */
328 ppc4xx_configure_pci_PMMs(hose, reg);
329
330 /* Configure inbound ranges PIMs */
331 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
332
333 /* We don't need the registers anymore */
334 iounmap(reg);
335 return;
336
337 fail:
338 if (hose)
339 pcibios_free_controller(hose);
340 if (reg)
341 iounmap(reg);
342 }
343
344 /*
345 * 4xx PCI-X part
346 */
347
348 static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
349 void __iomem *reg)
350 {
351 u32 lah, lal, pciah, pcial, sa;
352 int i, j;
353
354 /* Setup outbound memory windows */
355 for (i = j = 0; i < 3; i++) {
356 struct resource *res = &hose->mem_resources[i];
357
358 /* we only care about memory windows */
359 if (!(res->flags & IORESOURCE_MEM))
360 continue;
361 if (j > 1) {
362 printk(KERN_WARNING "%s: Too many ranges\n",
363 hose->dn->full_name);
364 break;
365 }
366
367 /* Calculate register values */
368 lah = RES_TO_U32_HIGH(res->start);
369 lal = RES_TO_U32_LOW(res->start);
370 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
371 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
372 sa = res->end + 1 - res->start;
373 if (!is_power_of_2(sa) || sa < 0x100000 ||
374 sa > 0xffffffffu) {
375 printk(KERN_WARNING "%s: Resource out of range\n",
376 hose->dn->full_name);
377 continue;
378 }
379 sa = (0xffffffffu << ilog2(sa)) | 0x1;
380
381 /* Program register values */
382 if (j == 0) {
383 writel(lah, reg + PCIX0_POM0LAH);
384 writel(lal, reg + PCIX0_POM0LAL);
385 writel(pciah, reg + PCIX0_POM0PCIAH);
386 writel(pcial, reg + PCIX0_POM0PCIAL);
387 writel(sa, reg + PCIX0_POM0SA);
388 } else {
389 writel(lah, reg + PCIX0_POM1LAH);
390 writel(lal, reg + PCIX0_POM1LAL);
391 writel(pciah, reg + PCIX0_POM1PCIAH);
392 writel(pcial, reg + PCIX0_POM1PCIAL);
393 writel(sa, reg + PCIX0_POM1SA);
394 }
395 j++;
396 }
397 }
398
399 static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
400 void __iomem *reg,
401 const struct resource *res,
402 int big_pim,
403 int enable_msi_hole)
404 {
405 resource_size_t size = res->end - res->start + 1;
406 u32 sa;
407
408 /* RAM is always at 0 */
409 writel(0x00000000, reg + PCIX0_PIM0LAH);
410 writel(0x00000000, reg + PCIX0_PIM0LAL);
411
412 /* Calculate window size */
413 sa = (0xffffffffu << ilog2(size)) | 1;
414 sa |= 0x1;
415 if (res->flags & IORESOURCE_PREFETCH)
416 sa |= 0x2;
417 if (enable_msi_hole)
418 sa |= 0x4;
419 writel(sa, reg + PCIX0_PIM0SA);
420 if (big_pim)
421 writel(0xffffffff, reg + PCIX0_PIM0SAH);
422
423 /* Map on PCI side */
424 writel(0x00000000, reg + PCIX0_BAR0H);
425 writel(res->start, reg + PCIX0_BAR0L);
426 writew(0x0006, reg + PCIX0_COMMAND);
427 }
428
429 static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
430 {
431 struct resource rsrc_cfg;
432 struct resource rsrc_reg;
433 struct resource dma_window;
434 struct pci_controller *hose = NULL;
435 void __iomem *reg = NULL;
436 const int *bus_range;
437 int big_pim = 0, msi = 0, primary = 0;
438
439 /* Fetch config space registers address */
440 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
441 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
442 np->full_name);
443 return;
444 }
445 /* Fetch host bridge internal registers address */
446 if (of_address_to_resource(np, 3, &rsrc_reg)) {
447 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
448 np->full_name);
449 return;
450 }
451
452 /* Check if it supports large PIMs (440GX) */
453 if (of_get_property(np, "large-inbound-windows", NULL))
454 big_pim = 1;
455
456 /* Check if we should enable MSIs inbound hole */
457 if (of_get_property(np, "enable-msi-hole", NULL))
458 msi = 1;
459
460 /* Check if primary bridge */
461 if (of_get_property(np, "primary", NULL))
462 primary = 1;
463
464 /* Get bus range if any */
465 bus_range = of_get_property(np, "bus-range", NULL);
466
467 /* Map registers */
468 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
469 if (reg == NULL) {
470 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
471 goto fail;
472 }
473
474 /* Allocate the host controller data structure */
475 hose = pcibios_alloc_controller(np);
476 if (!hose)
477 goto fail;
478
479 hose->first_busno = bus_range ? bus_range[0] : 0x0;
480 hose->last_busno = bus_range ? bus_range[1] : 0xff;
481
482 /* Setup config space */
483 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
484
485 /* Disable all windows */
486 writel(0, reg + PCIX0_POM0SA);
487 writel(0, reg + PCIX0_POM1SA);
488 writel(0, reg + PCIX0_POM2SA);
489 writel(0, reg + PCIX0_PIM0SA);
490 writel(0, reg + PCIX0_PIM1SA);
491 writel(0, reg + PCIX0_PIM2SA);
492 if (big_pim) {
493 writel(0, reg + PCIX0_PIM0SAH);
494 writel(0, reg + PCIX0_PIM2SAH);
495 }
496
497 /* Parse outbound mapping resources */
498 pci_process_bridge_OF_ranges(hose, np, primary);
499
500 /* Parse inbound mapping resources */
501 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
502 goto fail;
503
504 /* Configure outbound ranges POMs */
505 ppc4xx_configure_pcix_POMs(hose, reg);
506
507 /* Configure inbound ranges PIMs */
508 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
509
510 /* We don't need the registers anymore */
511 iounmap(reg);
512 return;
513
514 fail:
515 if (hose)
516 pcibios_free_controller(hose);
517 if (reg)
518 iounmap(reg);
519 }
520
521 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
522
523 /*
524 * 4xx PCI-Express part
525 *
526 * We support 3 parts currently based on the compatible property:
527 *
528 * ibm,plb-pciex-440spe
529 * ibm,plb-pciex-405ex
530 *
531 * Anything else will be rejected for now as they are all subtly
532 * different unfortunately.
533 *
534 */
535
536 #define MAX_PCIE_BUS_MAPPED 0x40
537
538 struct ppc4xx_pciex_port
539 {
540 struct pci_controller *hose;
541 struct device_node *node;
542 unsigned int index;
543 int endpoint;
544 int link;
545 int has_ibpre;
546 unsigned int sdr_base;
547 dcr_host_t dcrs;
548 struct resource cfg_space;
549 struct resource utl_regs;
550 void __iomem *utl_base;
551 };
552
553 static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
554 static unsigned int ppc4xx_pciex_port_count;
555
556 struct ppc4xx_pciex_hwops
557 {
558 int (*core_init)(struct device_node *np);
559 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
560 int (*setup_utl)(struct ppc4xx_pciex_port *port);
561 };
562
563 static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
564
565 #ifdef CONFIG_44x
566
567 /* Check various reset bits of the 440SPe PCIe core */
568 static int __init ppc440spe_pciex_check_reset(struct device_node *np)
569 {
570 u32 valPE0, valPE1, valPE2;
571 int err = 0;
572
573 /* SDR0_PEGPLLLCT1 reset */
574 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
575 /*
576 * the PCIe core was probably already initialised
577 * by firmware - let's re-reset RCSSET regs
578 *
579 * -- Shouldn't we also re-reset the whole thing ? -- BenH
580 */
581 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
582 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
583 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
584 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
585 }
586
587 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
588 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
589 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
590
591 /* SDR0_PExRCSSET rstgu */
592 if (!(valPE0 & 0x01000000) ||
593 !(valPE1 & 0x01000000) ||
594 !(valPE2 & 0x01000000)) {
595 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
596 err = -1;
597 }
598
599 /* SDR0_PExRCSSET rstdl */
600 if (!(valPE0 & 0x00010000) ||
601 !(valPE1 & 0x00010000) ||
602 !(valPE2 & 0x00010000)) {
603 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
604 err = -1;
605 }
606
607 /* SDR0_PExRCSSET rstpyn */
608 if ((valPE0 & 0x00001000) ||
609 (valPE1 & 0x00001000) ||
610 (valPE2 & 0x00001000)) {
611 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
612 err = -1;
613 }
614
615 /* SDR0_PExRCSSET hldplb */
616 if ((valPE0 & 0x10000000) ||
617 (valPE1 & 0x10000000) ||
618 (valPE2 & 0x10000000)) {
619 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
620 err = -1;
621 }
622
623 /* SDR0_PExRCSSET rdy */
624 if ((valPE0 & 0x00100000) ||
625 (valPE1 & 0x00100000) ||
626 (valPE2 & 0x00100000)) {
627 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
628 err = -1;
629 }
630
631 /* SDR0_PExRCSSET shutdown */
632 if ((valPE0 & 0x00000100) ||
633 (valPE1 & 0x00000100) ||
634 (valPE2 & 0x00000100)) {
635 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
636 err = -1;
637 }
638
639 return err;
640 }
641
642 /* Global PCIe core initializations for 440SPe core */
643 static int __init ppc440spe_pciex_core_init(struct device_node *np)
644 {
645 int time_out = 20;
646
647 /* Set PLL clock receiver to LVPECL */
648 mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28);
649
650 /* Shouldn't we do all the calibration stuff etc... here ? */
651 if (ppc440spe_pciex_check_reset(np))
652 return -ENXIO;
653
654 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
655 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
656 "failed (0x%08x)\n",
657 mfdcri(SDR0, PESDR0_PLLLCT2));
658 return -1;
659 }
660
661 /* De-assert reset of PCIe PLL, wait for lock */
662 mtdcri(SDR0, PESDR0_PLLLCT1,
663 mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24));
664 udelay(3);
665
666 while (time_out) {
667 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
668 time_out--;
669 udelay(1);
670 } else
671 break;
672 }
673 if (!time_out) {
674 printk(KERN_INFO "PCIE: VCO output not locked\n");
675 return -1;
676 }
677
678 pr_debug("PCIE initialization OK\n");
679
680 return 3;
681 }
682
683 static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
684 {
685 u32 val = 1 << 24;
686
687 if (port->endpoint)
688 val = PTYPE_LEGACY_ENDPOINT << 20;
689 else
690 val = PTYPE_ROOT_PORT << 20;
691
692 if (port->index == 0)
693 val |= LNKW_X8 << 12;
694 else
695 val |= LNKW_X4 << 12;
696
697 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
698 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
699 if (ppc440spe_revA())
700 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
701 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
702 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
703 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
704 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
705 if (port->index == 0) {
706 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
707 0x35000000);
708 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
709 0x35000000);
710 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
711 0x35000000);
712 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
713 0x35000000);
714 }
715 val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET);
716 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
717 (val & ~(1 << 24 | 1 << 16)) | 1 << 12);
718
719 return 0;
720 }
721
722 static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
723 {
724 return ppc440spe_pciex_init_port_hw(port);
725 }
726
727 static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
728 {
729 int rc = ppc440spe_pciex_init_port_hw(port);
730
731 port->has_ibpre = 1;
732
733 return rc;
734 }
735
736 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
737 {
738 /* XXX Check what that value means... I hate magic */
739 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
740
741 /*
742 * Set buffer allocations and then assert VRB and TXE.
743 */
744 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
745 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
746 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
747 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
748 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
749 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
750 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
751 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
752
753 return 0;
754 }
755
756 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
757 {
758 /* Report CRS to the operating system */
759 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
760
761 return 0;
762 }
763
764 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
765 {
766 .core_init = ppc440spe_pciex_core_init,
767 .port_init_hw = ppc440speA_pciex_init_port_hw,
768 .setup_utl = ppc440speA_pciex_init_utl,
769 };
770
771 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
772 {
773 .core_init = ppc440spe_pciex_core_init,
774 .port_init_hw = ppc440speB_pciex_init_port_hw,
775 .setup_utl = ppc440speB_pciex_init_utl,
776 };
777
778 #endif /* CONFIG_44x */
779
780 #ifdef CONFIG_40x
781
782 static int __init ppc405ex_pciex_core_init(struct device_node *np)
783 {
784 /* Nothing to do, return 2 ports */
785 return 2;
786 }
787
788 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
789 {
790 /* Assert the PE0_PHY reset */
791 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
792 msleep(1);
793
794 /* deassert the PE0_hotreset */
795 if (port->endpoint)
796 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
797 else
798 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
799
800 /* poll for phy !reset */
801 /* XXX FIXME add timeout */
802 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
803 ;
804
805 /* deassert the PE0_gpl_utl_reset */
806 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
807 }
808
809 static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
810 {
811 u32 val;
812
813 if (port->endpoint)
814 val = PTYPE_LEGACY_ENDPOINT;
815 else
816 val = PTYPE_ROOT_PORT;
817
818 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
819 1 << 24 | val << 20 | LNKW_X1 << 12);
820
821 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
822 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
823 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
824 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
825
826 /*
827 * Only reset the PHY when no link is currently established.
828 * This is for the Atheros PCIe board which has problems to establish
829 * the link (again) after this PHY reset. All other currently tested
830 * PCIe boards don't show this problem.
831 * This has to be re-tested and fixed in a later release!
832 */
833 #if 0 /* XXX FIXME: Not resetting the PHY will leave all resources
834 * configured as done previously by U-Boot. Then Linux will currently
835 * not reassign them. So the PHY reset is now done always. This will
836 * lead to problems with the Atheros PCIe board again.
837 */
838 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
839 if (!(val & 0x00001000))
840 ppc405ex_pcie_phy_reset(port);
841 #else
842 ppc405ex_pcie_phy_reset(port);
843 #endif
844
845 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
846
847 port->has_ibpre = 1;
848
849 return 0;
850 }
851
852 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
853 {
854 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
855
856 /*
857 * Set buffer allocations and then assert VRB and TXE.
858 */
859 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
860 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
861 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
862 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
863 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
864 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
865 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
866 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
867
868 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
869
870 return 0;
871 }
872
873 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
874 {
875 .core_init = ppc405ex_pciex_core_init,
876 .port_init_hw = ppc405ex_pciex_init_port_hw,
877 .setup_utl = ppc405ex_pciex_init_utl,
878 };
879
880 #endif /* CONFIG_40x */
881
882
883 /* Check that the core has been initied and if not, do it */
884 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
885 {
886 static int core_init;
887 int count = -ENODEV;
888
889 if (core_init++)
890 return 0;
891
892 #ifdef CONFIG_44x
893 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
894 if (ppc440spe_revA())
895 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
896 else
897 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
898 }
899 #endif /* CONFIG_44x */
900 #ifdef CONFIG_40x
901 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
902 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
903 #endif
904 if (ppc4xx_pciex_hwops == NULL) {
905 printk(KERN_WARNING "PCIE: unknown host type %s\n",
906 np->full_name);
907 return -ENODEV;
908 }
909
910 count = ppc4xx_pciex_hwops->core_init(np);
911 if (count > 0) {
912 ppc4xx_pciex_ports =
913 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
914 GFP_KERNEL);
915 if (ppc4xx_pciex_ports) {
916 ppc4xx_pciex_port_count = count;
917 return 0;
918 }
919 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
920 return -ENOMEM;
921 }
922 return -ENODEV;
923 }
924
925 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
926 {
927 /* We map PCI Express configuration based on the reg property */
928 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
929 RES_TO_U32_HIGH(port->cfg_space.start));
930 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
931 RES_TO_U32_LOW(port->cfg_space.start));
932
933 /* XXX FIXME: Use size from reg property. For now, map 512M */
934 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
935
936 /* We map UTL registers based on the reg property */
937 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
938 RES_TO_U32_HIGH(port->utl_regs.start));
939 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
940 RES_TO_U32_LOW(port->utl_regs.start));
941
942 /* XXX FIXME: Use size from reg property */
943 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
944
945 /* Disable all other outbound windows */
946 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
947 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
948 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
949 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
950 }
951
952 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
953 unsigned int sdr_offset,
954 unsigned int mask,
955 unsigned int value,
956 int timeout_ms)
957 {
958 u32 val;
959
960 while(timeout_ms--) {
961 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
962 if ((val & mask) == value) {
963 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
964 port->index, sdr_offset, timeout_ms, val);
965 return 0;
966 }
967 msleep(1);
968 }
969 return -1;
970 }
971
972 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
973 {
974 int rc = 0;
975
976 /* Init HW */
977 if (ppc4xx_pciex_hwops->port_init_hw)
978 rc = ppc4xx_pciex_hwops->port_init_hw(port);
979 if (rc != 0)
980 return rc;
981
982 printk(KERN_INFO "PCIE%d: Checking link...\n",
983 port->index);
984
985 /* Wait for reset to complete */
986 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
987 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
988 port->index);
989 return -1;
990 }
991
992 /* Check for card presence detect if supported, if not, just wait for
993 * link unconditionally.
994 *
995 * note that we don't fail if there is no link, we just filter out
996 * config space accesses. That way, it will be easier to implement
997 * hotplug later on.
998 */
999 if (!port->has_ibpre ||
1000 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1001 1 << 28, 1 << 28, 100)) {
1002 printk(KERN_INFO
1003 "PCIE%d: Device detected, waiting for link...\n",
1004 port->index);
1005 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1006 0x1000, 0x1000, 2000))
1007 printk(KERN_WARNING
1008 "PCIE%d: Link up failed\n", port->index);
1009 else {
1010 printk(KERN_INFO
1011 "PCIE%d: link is up !\n", port->index);
1012 port->link = 1;
1013 }
1014 } else
1015 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
1016
1017 /*
1018 * Initialize mapping: disable all regions and configure
1019 * CFG and REG regions based on resources in the device tree
1020 */
1021 ppc4xx_pciex_port_init_mapping(port);
1022
1023 /*
1024 * Map UTL
1025 */
1026 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1027 BUG_ON(port->utl_base == NULL);
1028
1029 /*
1030 * Setup UTL registers --BenH.
1031 */
1032 if (ppc4xx_pciex_hwops->setup_utl)
1033 ppc4xx_pciex_hwops->setup_utl(port);
1034
1035 /*
1036 * Check for VC0 active and assert RDY.
1037 */
1038 if (port->link &&
1039 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1040 1 << 16, 1 << 16, 5000)) {
1041 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1042 port->link = 0;
1043 }
1044
1045 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1046 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20);
1047 msleep(100);
1048
1049 return 0;
1050 }
1051
1052 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1053 struct pci_bus *bus,
1054 unsigned int devfn)
1055 {
1056 static int message;
1057
1058 /* Endpoint can not generate upstream(remote) config cycles */
1059 if (port->endpoint && bus->number != port->hose->first_busno)
1060 return PCIBIOS_DEVICE_NOT_FOUND;
1061
1062 /* Check we are within the mapped range */
1063 if (bus->number > port->hose->last_busno) {
1064 if (!message) {
1065 printk(KERN_WARNING "Warning! Probing bus %u"
1066 " out of range !\n", bus->number);
1067 message++;
1068 }
1069 return PCIBIOS_DEVICE_NOT_FOUND;
1070 }
1071
1072 /* The root complex has only one device / function */
1073 if (bus->number == port->hose->first_busno && devfn != 0)
1074 return PCIBIOS_DEVICE_NOT_FOUND;
1075
1076 /* The other side of the RC has only one device as well */
1077 if (bus->number == (port->hose->first_busno + 1) &&
1078 PCI_SLOT(devfn) != 0)
1079 return PCIBIOS_DEVICE_NOT_FOUND;
1080
1081 /* Check if we have a link */
1082 if ((bus->number != port->hose->first_busno) && !port->link)
1083 return PCIBIOS_DEVICE_NOT_FOUND;
1084
1085 return 0;
1086 }
1087
1088 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1089 struct pci_bus *bus,
1090 unsigned int devfn)
1091 {
1092 int relbus;
1093
1094 /* Remove the casts when we finally remove the stupid volatile
1095 * in struct pci_controller
1096 */
1097 if (bus->number == port->hose->first_busno)
1098 return (void __iomem *)port->hose->cfg_addr;
1099
1100 relbus = bus->number - (port->hose->first_busno + 1);
1101 return (void __iomem *)port->hose->cfg_data +
1102 ((relbus << 20) | (devfn << 12));
1103 }
1104
1105 static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1106 int offset, int len, u32 *val)
1107 {
1108 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1109 struct ppc4xx_pciex_port *port =
1110 &ppc4xx_pciex_ports[hose->indirect_type];
1111 void __iomem *addr;
1112 u32 gpl_cfg;
1113
1114 BUG_ON(hose != port->hose);
1115
1116 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1117 return PCIBIOS_DEVICE_NOT_FOUND;
1118
1119 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1120
1121 /*
1122 * Reading from configuration space of non-existing device can
1123 * generate transaction errors. For the read duration we suppress
1124 * assertion of machine check exceptions to avoid those.
1125 */
1126 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1127 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1128
1129 /* Make sure no CRS is recorded */
1130 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1131
1132 switch (len) {
1133 case 1:
1134 *val = in_8((u8 *)(addr + offset));
1135 break;
1136 case 2:
1137 *val = in_le16((u16 *)(addr + offset));
1138 break;
1139 default:
1140 *val = in_le32((u32 *)(addr + offset));
1141 break;
1142 }
1143
1144 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1145 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1146 bus->number, hose->first_busno, hose->last_busno,
1147 devfn, offset, len, addr + offset, *val);
1148
1149 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1150 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1151 pr_debug("Got CRS !\n");
1152 if (len != 4 || offset != 0)
1153 return PCIBIOS_DEVICE_NOT_FOUND;
1154 *val = 0xffff0001;
1155 }
1156
1157 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1158
1159 return PCIBIOS_SUCCESSFUL;
1160 }
1161
1162 static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1163 int offset, int len, u32 val)
1164 {
1165 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1166 struct ppc4xx_pciex_port *port =
1167 &ppc4xx_pciex_ports[hose->indirect_type];
1168 void __iomem *addr;
1169 u32 gpl_cfg;
1170
1171 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1172 return PCIBIOS_DEVICE_NOT_FOUND;
1173
1174 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1175
1176 /*
1177 * Reading from configuration space of non-existing device can
1178 * generate transaction errors. For the read duration we suppress
1179 * assertion of machine check exceptions to avoid those.
1180 */
1181 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1182 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1183
1184 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1185 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1186 bus->number, hose->first_busno, hose->last_busno,
1187 devfn, offset, len, addr + offset, val);
1188
1189 switch (len) {
1190 case 1:
1191 out_8((u8 *)(addr + offset), val);
1192 break;
1193 case 2:
1194 out_le16((u16 *)(addr + offset), val);
1195 break;
1196 default:
1197 out_le32((u32 *)(addr + offset), val);
1198 break;
1199 }
1200
1201 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1202
1203 return PCIBIOS_SUCCESSFUL;
1204 }
1205
1206 static struct pci_ops ppc4xx_pciex_pci_ops =
1207 {
1208 .read = ppc4xx_pciex_read_config,
1209 .write = ppc4xx_pciex_write_config,
1210 };
1211
1212 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1213 struct pci_controller *hose,
1214 void __iomem *mbase)
1215 {
1216 u32 lah, lal, pciah, pcial, sa;
1217 int i, j;
1218
1219 /* Setup outbound memory windows */
1220 for (i = j = 0; i < 3; i++) {
1221 struct resource *res = &hose->mem_resources[i];
1222
1223 /* we only care about memory windows */
1224 if (!(res->flags & IORESOURCE_MEM))
1225 continue;
1226 if (j > 1) {
1227 printk(KERN_WARNING "%s: Too many ranges\n",
1228 port->node->full_name);
1229 break;
1230 }
1231
1232 /* Calculate register values */
1233 lah = RES_TO_U32_HIGH(res->start);
1234 lal = RES_TO_U32_LOW(res->start);
1235 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
1236 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
1237 sa = res->end + 1 - res->start;
1238 if (!is_power_of_2(sa) || sa < 0x100000 ||
1239 sa > 0xffffffffu) {
1240 printk(KERN_WARNING "%s: Resource out of range\n",
1241 port->node->full_name);
1242 continue;
1243 }
1244 sa = (0xffffffffu << ilog2(sa)) | 0x1;
1245
1246 /* Program register values */
1247 switch (j) {
1248 case 0:
1249 out_le32(mbase + PECFG_POM0LAH, pciah);
1250 out_le32(mbase + PECFG_POM0LAL, pcial);
1251 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1252 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1253 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1254 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
1255 break;
1256 case 1:
1257 out_le32(mbase + PECFG_POM1LAH, pciah);
1258 out_le32(mbase + PECFG_POM1LAL, pcial);
1259 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1260 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1261 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1262 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
1263 break;
1264 }
1265 j++;
1266 }
1267
1268 /* Configure IO, always 64K starting at 0 */
1269 if (hose->io_resource.flags & IORESOURCE_IO) {
1270 lah = RES_TO_U32_HIGH(hose->io_base_phys);
1271 lal = RES_TO_U32_LOW(hose->io_base_phys);
1272 out_le32(mbase + PECFG_POM2LAH, 0);
1273 out_le32(mbase + PECFG_POM2LAL, 0);
1274 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1275 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1276 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1277 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0xffff0000 | 3);
1278 }
1279 }
1280
1281 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1282 struct pci_controller *hose,
1283 void __iomem *mbase,
1284 struct resource *res)
1285 {
1286 resource_size_t size = res->end - res->start + 1;
1287 u64 sa;
1288
1289 /* Calculate window size */
1290 sa = (0xffffffffffffffffull << ilog2(size));;
1291 if (res->flags & IORESOURCE_PREFETCH)
1292 sa |= 0x8;
1293
1294 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1295 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1296
1297 /* The setup of the split looks weird to me ... let's see if it works */
1298 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1299 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1300 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1301 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1302 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1303 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1304
1305 /* Enable inbound mapping */
1306 out_le32(mbase + PECFG_PIMEN, 0x1);
1307
1308 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1309 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1310
1311 /* Enable I/O, Mem, and Busmaster cycles */
1312 out_le16(mbase + PCI_COMMAND,
1313 in_le16(mbase + PCI_COMMAND) |
1314 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1315 }
1316
1317 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1318 {
1319 struct resource dma_window;
1320 struct pci_controller *hose = NULL;
1321 const int *bus_range;
1322 int primary = 0, busses;
1323 void __iomem *mbase = NULL, *cfg_data = NULL;
1324
1325 /* XXX FIXME: Handle endpoint mode properly */
1326 if (port->endpoint) {
1327 printk(KERN_WARNING "PCIE%d: Port in endpoint mode !\n",
1328 port->index);
1329 return;
1330 }
1331
1332 /* Check if primary bridge */
1333 if (of_get_property(port->node, "primary", NULL))
1334 primary = 1;
1335
1336 /* Get bus range if any */
1337 bus_range = of_get_property(port->node, "bus-range", NULL);
1338
1339 /* Allocate the host controller data structure */
1340 hose = pcibios_alloc_controller(port->node);
1341 if (!hose)
1342 goto fail;
1343
1344 /* We stick the port number in "indirect_type" so the config space
1345 * ops can retrieve the port data structure easily
1346 */
1347 hose->indirect_type = port->index;
1348
1349 /* Get bus range */
1350 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1351 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1352
1353 /* Because of how big mapping the config space is (1M per bus), we
1354 * limit how many busses we support. In the long run, we could replace
1355 * that with something akin to kmap_atomic instead. We set aside 1 bus
1356 * for the host itself too.
1357 */
1358 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1359 if (busses > MAX_PCIE_BUS_MAPPED) {
1360 busses = MAX_PCIE_BUS_MAPPED;
1361 hose->last_busno = hose->first_busno + busses;
1362 }
1363
1364 /* We map the external config space in cfg_data and the host config
1365 * space in cfg_addr. External space is 1M per bus, internal space
1366 * is 4K
1367 */
1368 cfg_data = ioremap(port->cfg_space.start +
1369 (hose->first_busno + 1) * 0x100000,
1370 busses * 0x100000);
1371 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1372 if (cfg_data == NULL || mbase == NULL) {
1373 printk(KERN_ERR "%s: Can't map config space !",
1374 port->node->full_name);
1375 goto fail;
1376 }
1377
1378 hose->cfg_data = cfg_data;
1379 hose->cfg_addr = mbase;
1380
1381 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1382 hose->first_busno, hose->last_busno);
1383 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1384 hose->cfg_addr, hose->cfg_data);
1385
1386 /* Setup config space */
1387 hose->ops = &ppc4xx_pciex_pci_ops;
1388 port->hose = hose;
1389 mbase = (void __iomem *)hose->cfg_addr;
1390
1391 /*
1392 * Set bus numbers on our root port
1393 */
1394 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1395 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1396 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1397
1398 /*
1399 * OMRs are already reset, also disable PIMs
1400 */
1401 out_le32(mbase + PECFG_PIMEN, 0);
1402
1403 /* Parse outbound mapping resources */
1404 pci_process_bridge_OF_ranges(hose, port->node, primary);
1405
1406 /* Parse inbound mapping resources */
1407 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1408 goto fail;
1409
1410 /* Configure outbound ranges POMs */
1411 ppc4xx_configure_pciex_POMs(port, hose, mbase);
1412
1413 /* Configure inbound ranges PIMs */
1414 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1415
1416 /* The root complex doesn't show up if we don't set some vendor
1417 * and device IDs into it. Those are the same bogus one that the
1418 * initial code in arch/ppc add. We might want to change that.
1419 */
1420 out_le16(mbase + 0x200, 0xaaa0 + port->index);
1421 out_le16(mbase + 0x202, 0xbed0 + port->index);
1422
1423 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1424 out_le32(mbase + 0x208, 0x06040001);
1425
1426 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
1427 port->index);
1428 return;
1429 fail:
1430 if (hose)
1431 pcibios_free_controller(hose);
1432 if (cfg_data)
1433 iounmap(cfg_data);
1434 if (mbase)
1435 iounmap(mbase);
1436 }
1437
1438 static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
1439 {
1440 struct ppc4xx_pciex_port *port;
1441 const u32 *pval;
1442 int portno;
1443 unsigned int dcrs;
1444
1445 /* First, proceed to core initialization as we assume there's
1446 * only one PCIe core in the system
1447 */
1448 if (ppc4xx_pciex_check_core_init(np))
1449 return;
1450
1451 /* Get the port number from the device-tree */
1452 pval = of_get_property(np, "port", NULL);
1453 if (pval == NULL) {
1454 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
1455 np->full_name);
1456 return;
1457 }
1458 portno = *pval;
1459 if (portno >= ppc4xx_pciex_port_count) {
1460 printk(KERN_ERR "PCIE: port number out of range for %s\n",
1461 np->full_name);
1462 return;
1463 }
1464 port = &ppc4xx_pciex_ports[portno];
1465 port->index = portno;
1466 port->node = of_node_get(np);
1467 pval = of_get_property(np, "sdr-base", NULL);
1468 if (pval == NULL) {
1469 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
1470 np->full_name);
1471 return;
1472 }
1473 port->sdr_base = *pval;
1474
1475 /* XXX Currently, we only support root complex mode */
1476 port->endpoint = 0;
1477
1478 /* Fetch config space registers address */
1479 if (of_address_to_resource(np, 0, &port->cfg_space)) {
1480 printk(KERN_ERR "%s: Can't get PCI-E config space !",
1481 np->full_name);
1482 return;
1483 }
1484 /* Fetch host bridge internal registers address */
1485 if (of_address_to_resource(np, 1, &port->utl_regs)) {
1486 printk(KERN_ERR "%s: Can't get UTL register base !",
1487 np->full_name);
1488 return;
1489 }
1490
1491 /* Map DCRs */
1492 dcrs = dcr_resource_start(np, 0);
1493 if (dcrs == 0) {
1494 printk(KERN_ERR "%s: Can't get DCR register base !",
1495 np->full_name);
1496 return;
1497 }
1498 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
1499
1500 /* Initialize the port specific registers */
1501 if (ppc4xx_pciex_port_init(port)) {
1502 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
1503 return;
1504 }
1505
1506 /* Setup the linux hose data structure */
1507 ppc4xx_pciex_port_setup_hose(port);
1508 }
1509
1510 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1511
1512 static int __init ppc4xx_pci_find_bridges(void)
1513 {
1514 struct device_node *np;
1515
1516 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
1517 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
1518 ppc4xx_probe_pciex_bridge(np);
1519 #endif
1520 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
1521 ppc4xx_probe_pcix_bridge(np);
1522 for_each_compatible_node(np, NULL, "ibm,plb-pci")
1523 ppc4xx_probe_pci_bridge(np);
1524
1525 return 0;
1526 }
1527 arch_initcall(ppc4xx_pci_find_bridges);
1528
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