arch/powerpc/platforms/cell/setup.c

   1 /*
   2  *  linux/arch/powerpc/platforms/cell/cell_setup.c
   3  *
   4  *  Copyright (C) 1995  Linus Torvalds
   5  *  Adapted from 'alpha' version by Gary Thomas
   6  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   7  *  Modified by PPC64 Team, IBM Corp
   8  *  Modified by Cell Team, IBM Deutschland Entwicklung GmbH
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/sched.h>
  18 #include <linux/kernel.h>
  19 #include <linux/mm.h>
  20 #include <linux/stddef.h>
  21 #include <linux/unistd.h>
  22 #include <linux/slab.h>
  23 #include <linux/user.h>
  24 #include <linux/reboot.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/irq.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/root_dev.h>
  30 #include <linux/console.h>
  31 #include <linux/mutex.h>
  32 #include <linux/memory_hotplug.h>
  33 #include <linux/of_platform.h>
  34
  35 #include <asm/mmu.h>
  36 #include <asm/processor.h>
  37 #include <asm/io.h>
  38 #include <asm/kexec.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/prom.h>
  41 #include <asm/rtas.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/iommu.h>
  44 #include <asm/dma.h>
  45 #include <asm/machdep.h>
  46 #include <asm/time.h>
  47 #include <asm/nvram.h>
  48 #include <asm/cputable.h>
  49 #include <asm/ppc-pci.h>
  50 #include <asm/irq.h>
  51 #include <asm/spu.h>
  52 #include <asm/spu_priv1.h>
  53 #include <asm/udbg.h>
  54 #include <asm/mpic.h>
  55 #include <asm/cell-regs.h>
  56
  57 #include "interrupt.h"
  58 #include "pervasive.h"
  59 #include "ras.h"
  60
  61 #ifdef DEBUG
  62 #define DBG(fmt...) udbg_printf(fmt)
  63 #else
  64 #define DBG(fmt...)
  65 #endif
  66
  67 static void cell_show_cpuinfo(struct seq_file *m)
  68 {
  69         struct device_node *root;
  70         const char *model = "";
  71
  72         root = of_find_node_by_path("/");
  73         if (root)
  74                 model = of_get_property(root, "model", NULL);
  75         seq_printf(m, "machine\t\t: CHRP %s\n", model);
  76         of_node_put(root);
  77 }
  78
  79 static void cell_progress(char *s, unsigned short hex)
  80 {
  81         printk("*** %04x : %s\n", hex, s ? s : "");
  82 }
  83
  84 static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
  85 {
  86         struct pci_controller *hose;
  87         const char *s;
  88         int i;
  89
  90         if (!machine_is(cell))
  91                 return;
  92
  93         /* We're searching for a direct child of the PHB */
  94         if (dev->bus->self != NULL || dev->devfn != 0)
  95                 return;
  96
  97         hose = pci_bus_to_host(dev->bus);
  98         if (hose == NULL)
  99                 return;
 100
 101         /* Only on PCIE */
 102         if (!of_device_is_compatible(hose->dn, "pciex"))
 103                 return;
 104
 105         /* And only on axon */
 106         s = of_get_property(hose->dn, "model", NULL);
 107         if (!s || strcmp(s, "Axon") != 0)
 108                 return;
 109
 110         for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
 111                 dev->resource[i].start = dev->resource[i].end = 0;
 112                 dev->resource[i].flags = 0;
 113         }
 114
 115         printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n",
 116                pci_name(dev));
 117 }
 118 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
 119
 120 static int __init cell_publish_devices(void)
 121 {
 122         int node;
 123
 124         /* Publish OF platform devices for southbridge IOs */
 125         of_platform_bus_probe(NULL, NULL, NULL);
 126
 127         /* There is no device for the MIC memory controller, thus we create
 128          * a platform device for it to attach the EDAC driver to.
 129          */
 130         for_each_online_node(node) {
 131                 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
 132                         continue;
 133                 platform_device_register_simple("cbe-mic", node, NULL, 0);
 134         }
 135         return 0;
 136 }
 137 machine_subsys_initcall(cell, cell_publish_devices);
 138
 139 static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc)
 140 {
 141         struct mpic *mpic = desc->handler_data;
 142         unsigned int virq;
 143
 144         virq = mpic_get_one_irq(mpic);
 145         if (virq != NO_IRQ)
 146                 generic_handle_irq(virq);
 147         desc->chip->eoi(irq);
 148 }
 149
 150 static void __init mpic_init_IRQ(void)
 151 {
 152         struct device_node *dn;
 153         struct mpic *mpic;
 154         unsigned int virq;
 155
 156         for (dn = NULL;
 157              (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
 158                 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
 159                         continue;
 160
 161                 /* The MPIC driver will get everything it needs from the
 162                  * device-tree, just pass 0 to all arguments
 163                  */
 164                 mpic = mpic_alloc(dn, 0, 0, 0, 0, " MPIC     ");
 165                 if (mpic == NULL)
 166                         continue;
 167                 mpic_init(mpic);
 168
 169                 virq = irq_of_parse_and_map(dn, 0);
 170                 if (virq == NO_IRQ)
 171                         continue;
 172
 173                 printk(KERN_INFO "%s : hooking up to IRQ %d\n",
 174                        dn->full_name, virq);
 175                 set_irq_data(virq, mpic);
 176                 set_irq_chained_handler(virq, cell_mpic_cascade);
 177         }
 178 }
 179
 180
 181 static void __init cell_init_irq(void)
 182 {
 183         iic_init_IRQ();
 184         spider_init_IRQ();
 185         mpic_init_IRQ();
 186 }
 187
 188 static void __init cell_set_dabrx(void)
 189 {
 190         mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
 191 }
 192
 193 static void __init cell_setup_arch(void)
 194 {
 195 #ifdef CONFIG_SPU_BASE
 196         spu_priv1_ops = &spu_priv1_mmio_ops;
 197         spu_management_ops = &spu_management_of_ops;
 198 #endif
 199
 200         cbe_regs_init();
 201
 202         cell_set_dabrx();
 203
 204 #ifdef CONFIG_CBE_RAS
 205         cbe_ras_init();
 206 #endif
 207
 208 #ifdef CONFIG_SMP
 209         smp_init_cell();
 210 #endif
 211         /* init to some ~sane value until calibrate_delay() runs */
 212         loops_per_jiffy = 50000000;
 213
 214         /* Find and initialize PCI host bridges */
 215         init_pci_config_tokens();
 216         find_and_init_phbs();
 217         cbe_pervasive_init();
 218 #ifdef CONFIG_DUMMY_CONSOLE
 219         conswitchp = &dummy_con;
 220 #endif
 221
 222         mmio_nvram_init();
 223 }
 224
 225 static int __init cell_probe(void)
 226 {
 227         unsigned long root = of_get_flat_dt_root();
 228
 229         if (!of_flat_dt_is_compatible(root, "IBM,CBEA") &&
 230             !of_flat_dt_is_compatible(root, "IBM,CPBW-1.0"))
 231                 return 0;
 232
 233         hpte_init_native();
 234
 235         return 1;
 236 }
 237
 238 define_machine(cell) {
 239         .name                   = "Cell",
 240         .probe                  = cell_probe,
 241         .setup_arch             = cell_setup_arch,
 242         .show_cpuinfo           = cell_show_cpuinfo,
 243         .restart                = rtas_restart,
 244         .power_off              = rtas_power_off,
 245         .halt                   = rtas_halt,
 246         .get_boot_time          = rtas_get_boot_time,
 247         .get_rtc_time           = rtas_get_rtc_time,
 248         .set_rtc_time           = rtas_set_rtc_time,
 249         .calibrate_decr         = generic_calibrate_decr,
 250         .progress               = cell_progress,
 251         .init_IRQ               = cell_init_irq,
 252         .pci_setup_phb          = rtas_setup_phb,
 253 #ifdef CONFIG_KEXEC
 254         .machine_kexec          = default_machine_kexec,
 255         .machine_kexec_prepare  = default_machine_kexec_prepare,
 256         .machine_crash_shutdown = default_machine_crash_shutdown,
 257 #endif
 258 };