arch/powerpc/platforms/8xx/mpc885ads.h

   1 /*
   2  * A collection of structures, addresses, and values associated with
   3  * the Freescale MPC885ADS board.
   4  * Copied from the FADS stuff.
   5  *
   6  * Author: MontaVista Software, Inc.
   7  *         source@mvista.com
   8  *
   9  * 2005 (c) MontaVista Software, Inc.  This file is licensed under the
  10  * terms of the GNU General Public License version 2.  This program is licensed
  11  * "as is" without any warranty of any kind, whether express or implied.
  12  */
  13
  14 #ifdef __KERNEL__
  15 #ifndef __ASM_MPC885ADS_H__
  16 #define __ASM_MPC885ADS_H__
  17
  18 #include <sysdev/fsl_soc.h>
  19
  20 #define MPC8xx_CPM_OFFSET       (0x9c0)
  21 #define CPM_MAP_ADDR            (get_immrbase() + MPC8xx_CPM_OFFSET)
  22 #define CPM_IRQ_OFFSET          16     // for compability with cpm_uart driver
  23
  24 /* Bits of interest in the BCSRs.
  25  */
  26 #define BCSR1_ETHEN             ((uint)0x20000000)
  27 #define BCSR1_IRDAEN            ((uint)0x10000000)
  28 #define BCSR1_RS232EN_1         ((uint)0x01000000)
  29 #define BCSR1_PCCEN             ((uint)0x00800000)
  30 #define BCSR1_PCCVCC0           ((uint)0x00400000)
  31 #define BCSR1_PCCVPP0           ((uint)0x00200000)
  32 #define BCSR1_PCCVPP1           ((uint)0x00100000)
  33 #define BCSR1_PCCVPP_MASK       (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
  34 #define BCSR1_RS232EN_2         ((uint)0x00040000)
  35 #define BCSR1_PCCVCC1           ((uint)0x00010000)
  36 #define BCSR1_PCCVCC_MASK       (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
  37
  38 #define BCSR4_ETH10_RST         ((uint)0x80000000)      /* 10Base-T PHY reset*/
  39 #define BCSR4_USB_LO_SPD        ((uint)0x04000000)
  40 #define BCSR4_USB_VCC           ((uint)0x02000000)
  41 #define BCSR4_USB_FULL_SPD      ((uint)0x00040000)
  42 #define BCSR4_USB_EN            ((uint)0x00020000)
  43
  44 #define BCSR5_MII2_EN           0x40
  45 #define BCSR5_MII2_RST          0x20
  46 #define BCSR5_T1_RST            0x10
  47 #define BCSR5_ATM155_RST        0x08
  48 #define BCSR5_ATM25_RST         0x04
  49 #define BCSR5_MII1_EN           0x02
  50 #define BCSR5_MII1_RST          0x01
  51
  52 #endif /* __ASM_MPC885ADS_H__ */
  53 #endif /* __KERNEL__ */