arch/powerpc/platforms/85xx/mpc85xx_mds.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
   3  *
   4  * Author: Andy Fleming <afleming@freescale.com>
   5  *
   6  * Based on 83xx/mpc8360e_pb.c by:
   7  *         Li Yang <LeoLi@freescale.com>
   8  *         Yin Olivia <Hong-hua.Yin@freescale.com>
   9  *
  10  * Description:
  11  * MPC85xx MDS board specific routines.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/major.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/initrd.h>
  31 #include <linux/module.h>
  32 #include <linux/fsl_devices.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/of_device.h>
  35
  36 #include <asm/system.h>
  37 #include <asm/atomic.h>
  38 #include <asm/time.h>
  39 #include <asm/io.h>
  40 #include <asm/machdep.h>
  41 #include <asm/pci-bridge.h>
  42 #include <asm/irq.h>
  43 #include <mm/mmu_decl.h>
  44 #include <asm/prom.h>
  45 #include <asm/udbg.h>
  46 #include <sysdev/fsl_soc.h>
  47 #include <sysdev/fsl_pci.h>
  48 #include <asm/qe.h>
  49 #include <asm/qe_ic.h>
  50 #include <asm/mpic.h>
  51
  52 #undef DEBUG
  53 #ifdef DEBUG
  54 #define DBG(fmt...) udbg_printf(fmt)
  55 #else
  56 #define DBG(fmt...)
  57 #endif
  58
  59 /* ************************************************************************
  60  *
  61  * Setup the architecture
  62  *
  63  */
  64 static void __init mpc85xx_mds_setup_arch(void)
  65 {
  66         struct device_node *np;
  67         static u8 *bcsr_regs = NULL;
  68
  69         if (ppc_md.progress)
  70                 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
  71
  72         /* Map BCSR area */
  73         np = of_find_node_by_name(NULL, "bcsr");
  74         if (np != NULL) {
  75                 struct resource res;
  76
  77                 of_address_to_resource(np, 0, &res);
  78                 bcsr_regs = ioremap(res.start, res.end - res.start +1);
  79                 of_node_put(np);
  80         }
  81
  82 #ifdef CONFIG_PCI
  83         for_each_node_by_type(np, "pci") {
  84                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
  85                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
  86                         struct resource rsrc;
  87                         of_address_to_resource(np, 0, &rsrc);
  88                         if ((rsrc.start & 0xfffff) == 0x8000)
  89                                 fsl_add_bridge(np, 1);
  90                         else
  91                                 fsl_add_bridge(np, 0);
  92                 }
  93         }
  94 #endif
  95
  96 #ifdef CONFIG_QUICC_ENGINE
  97         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
  98         if (!np) {
  99                 np = of_find_node_by_name(NULL, "qe");
 100                 if (!np)
 101                         return;
 102         }
 103
 104         qe_reset();
 105         of_node_put(np);
 106
 107         np = of_find_node_by_name(NULL, "par_io");
 108         if (np) {
 109                 struct device_node *ucc;
 110
 111                 par_io_init(np);
 112                 of_node_put(np);
 113
 114                 for_each_node_by_name(ucc, "ucc")
 115                         par_io_of_config(ucc);
 116         }
 117
 118         if (bcsr_regs) {
 119 #define BCSR_UCC1_GETH_EN       (0x1 << 7)
 120 #define BCSR_UCC2_GETH_EN       (0x1 << 7)
 121 #define BCSR_UCC1_MODE_MSK      (0x3 << 4)
 122 #define BCSR_UCC2_MODE_MSK      (0x3 << 0)
 123
 124                 /* Turn off UCC1 & UCC2 */
 125                 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 126                 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 127
 128                 /* Mode is RGMII, all bits clear */
 129                 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
 130                                          BCSR_UCC2_MODE_MSK);
 131
 132                 /* Turn UCC1 & UCC2 on */
 133                 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 134                 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 135
 136                 iounmap(bcsr_regs);
 137         }
 138 #endif  /* CONFIG_QUICC_ENGINE */
 139 }
 140
 141 static struct of_device_id mpc85xx_ids[] = {
 142         { .type = "soc", },
 143         { .compatible = "soc", },
 144         { .type = "qe", },
 145         { .compatible = "fsl,qe", },
 146         {},
 147 };
 148
 149 static int __init mpc85xx_publish_devices(void)
 150 {
 151         /* Publish the QE devices */
 152         of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
 153
 154         return 0;
 155 }
 156 machine_device_initcall(mpc85xx_mds, mpc85xx_publish_devices);
 157
 158 static void __init mpc85xx_mds_pic_init(void)
 159 {
 160         struct mpic *mpic;
 161         struct resource r;
 162         struct device_node *np = NULL;
 163
 164         np = of_find_node_by_type(NULL, "open-pic");
 165         if (!np)
 166                 return;
 167
 168         if (of_address_to_resource(np, 0, &r)) {
 169                 printk(KERN_ERR "Failed to map mpic register space\n");
 170                 of_node_put(np);
 171                 return;
 172         }
 173
 174         mpic = mpic_alloc(np, r.start,
 175                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 176                         0, 256, " OpenPIC  ");
 177         BUG_ON(mpic == NULL);
 178         of_node_put(np);
 179
 180         mpic_init(mpic);
 181
 182 #ifdef CONFIG_QUICC_ENGINE
 183         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
 184         if (!np) {
 185                 np = of_find_node_by_type(NULL, "qeic");
 186                 if (!np)
 187                         return;
 188         }
 189         qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
 190         of_node_put(np);
 191 #endif                          /* CONFIG_QUICC_ENGINE */
 192 }
 193
 194 static int __init mpc85xx_mds_probe(void)
 195 {
 196         unsigned long root = of_get_flat_dt_root();
 197
 198         return of_flat_dt_is_compatible(root, "MPC85xxMDS");
 199 }
 200
 201 define_machine(mpc85xx_mds) {
 202         .name           = "MPC85xx MDS",
 203         .probe          = mpc85xx_mds_probe,
 204         .setup_arch     = mpc85xx_mds_setup_arch,
 205         .init_IRQ       = mpc85xx_mds_pic_init,
 206         .get_irq        = mpic_get_irq,
 207         .restart        = fsl_rstcr_restart,
 208         .calibrate_decr = generic_calibrate_decr,
 209         .progress       = udbg_progress,
 210 #ifdef CONFIG_PCI
 211         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 212 #endif
 213 };