arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c

   1 /*
   2  * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
   3  *
   4  * Toshiba RBTX4927 specific interrupt handlers
   5  *
   6  * Author: MontaVista Software, Inc.
   7  *         source@mvista.com
   8  *
   9  * Copyright 2001-2002 MontaVista Software Inc.
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the
  13  *  Free Software Foundation; either version 2 of the License, or (at your
  14  *  option) any later version.
  15  *
  16  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  18  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  21  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  22  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  24  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  25  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  *  You should have received a copy of the GNU General Public License along
  28  *  with this program; if not, write to the Free Software Foundation, Inc.,
  29  *  675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31
  32
  33 /*
  34 IRQ  Device
  35 00   RBTX4927-ISA/00
  36 01   RBTX4927-ISA/01 PS2/Keyboard
  37 02   RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
  38 03   RBTX4927-ISA/03
  39 04   RBTX4927-ISA/04
  40 05   RBTX4927-ISA/05
  41 06   RBTX4927-ISA/06
  42 07   RBTX4927-ISA/07
  43 08   RBTX4927-ISA/08
  44 09   RBTX4927-ISA/09
  45 10   RBTX4927-ISA/10
  46 11   RBTX4927-ISA/11
  47 12   RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
  48 13   RBTX4927-ISA/13
  49 14   RBTX4927-ISA/14 IDE
  50 15   RBTX4927-ISA/15
  51
  52 16   TX4927-CP0/00 Software 0
  53 17   TX4927-CP0/01 Software 1
  54 18   TX4927-CP0/02 Cascade TX4927-CP0
  55 19   TX4927-CP0/03 Multiplexed -- do not use
  56 20   TX4927-CP0/04 Multiplexed -- do not use
  57 21   TX4927-CP0/05 Multiplexed -- do not use
  58 22   TX4927-CP0/06 Multiplexed -- do not use
  59 23   TX4927-CP0/07 CPU TIMER
  60
  61 24   TX4927-PIC/00
  62 25   TX4927-PIC/01
  63 26   TX4927-PIC/02
  64 27   TX4927-PIC/03 Cascade RBTX4927-IOC
  65 28   TX4927-PIC/04
  66 29   TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
  67 30   TX4927-PIC/06
  68 31   TX4927-PIC/07
  69 32   TX4927-PIC/08 TX4927 SerialIO Channel 0
  70 33   TX4927-PIC/09 TX4927 SerialIO Channel 1
  71 34   TX4927-PIC/10
  72 35   TX4927-PIC/11
  73 36   TX4927-PIC/12
  74 37   TX4927-PIC/13
  75 38   TX4927-PIC/14
  76 39   TX4927-PIC/15
  77 40   TX4927-PIC/16 TX4927 PCI PCI-C
  78 41   TX4927-PIC/17
  79 42   TX4927-PIC/18
  80 43   TX4927-PIC/19
  81 44   TX4927-PIC/20
  82 45   TX4927-PIC/21
  83 46   TX4927-PIC/22 TX4927 PCI PCI-ERR
  84 47   TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
  85 48   TX4927-PIC/24
  86 49   TX4927-PIC/25
  87 50   TX4927-PIC/26
  88 51   TX4927-PIC/27
  89 52   TX4927-PIC/28
  90 53   TX4927-PIC/29
  91 54   TX4927-PIC/30
  92 55   TX4927-PIC/31
  93
  94 56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed)        [RTL-8139=PJ4]
  95 57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed)        [RTL-8139=PJ5]
  96 58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
  97 59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4)      [RTL-8139=PJ6]
  98 60 RBTX4927-IOC/04
  99 61 RBTX4927-IOC/05
 100 62 RBTX4927-IOC/06
 101 63 RBTX4927-IOC/07
 102
 103 NOTES:
 104 SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
 105 SouthBridge/ISA/pin=0 no pci irq used by this device
 106 SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
 107 SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
 108 SouthBridge/PMC/pin=0 no pci irq used by this device
 109 SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
 110 SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
 111 JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
 112 */
 113
 114 #include <linux/init.h>
 115 #include <linux/kernel.h>
 116 #include <linux/types.h>
 117 #include <linux/mm.h>
 118 #include <linux/swap.h>
 119 #include <linux/ioport.h>
 120 #include <linux/sched.h>
 121 #include <linux/interrupt.h>
 122 #include <linux/pci.h>
 123 #include <linux/timex.h>
 124 #include <asm/bootinfo.h>
 125 #include <asm/page.h>
 126 #include <asm/io.h>
 127 #include <asm/irq.h>
 128 #include <asm/pci.h>
 129 #include <asm/processor.h>
 130 #include <asm/reboot.h>
 131 #include <asm/time.h>
 132 #include <asm/wbflush.h>
 133 #include <linux/bootmem.h>
 134 #include <linux/blkdev.h>
 135 #ifdef CONFIG_TOSHIBA_FPCIB0
 136 #include <asm/i8259.h>
 137 #include <asm/tx4927/smsc_fdc37m81x.h>
 138 #endif
 139 #include <asm/tx4927/toshiba_rbtx4927.h>
 140
 141
 142 #undef TOSHIBA_RBTX4927_IRQ_DEBUG
 143
 144 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
 145 #define TOSHIBA_RBTX4927_IRQ_NONE        0x00000000
 146
 147 #define TOSHIBA_RBTX4927_IRQ_INFO          ( 1 <<  0 )
 148 #define TOSHIBA_RBTX4927_IRQ_WARN          ( 1 <<  1 )
 149 #define TOSHIBA_RBTX4927_IRQ_EROR          ( 1 <<  2 )
 150
 151 #define TOSHIBA_RBTX4927_IRQ_IOC_INIT      ( 1 << 10 )
 152 #define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE    ( 1 << 13 )
 153 #define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE   ( 1 << 14 )
 154
 155 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
 156 #endif
 157
 158
 159 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
 160 static const u32 toshiba_rbtx4927_irq_debug_flag =
 161     (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
 162      TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
 163 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_INIT
 164 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
 165 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
 166     );
 167 #endif
 168
 169
 170 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
 171 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \
 172         if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \
 173         { \
 174            char tmp[100]; \
 175            sprintf( tmp, str ); \
 176            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
 177         }
 178 #else
 179 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag, str...)
 180 #endif
 181
 182
 183
 184
 185 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG   0
 186 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END   7
 187
 188 #define TOSHIBA_RBTX4927_IRQ_IOC_BEG  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
 189 #define TOSHIBA_RBTX4927_IRQ_IOC_END  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
 190
 191 #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
 192 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
 193
 194 extern int tx4927_using_backplane;
 195
 196 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
 197 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
 198
 199 #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
 200 static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
 201         .name = TOSHIBA_RBTX4927_IOC_NAME,
 202         .ack = toshiba_rbtx4927_irq_ioc_disable,
 203         .mask = toshiba_rbtx4927_irq_ioc_disable,
 204         .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
 205         .unmask = toshiba_rbtx4927_irq_ioc_enable,
 206 };
 207 #define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL
 208 #define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL
 209
 210
 211 u32 bit2num(u32 num)
 212 {
 213         u32 i;
 214
 215         for (i = 0; i < (sizeof(num) * 8); i++) {
 216                 if (num & (1 << i)) {
 217                         return (i);
 218                 }
 219         }
 220         return (0);
 221 }
 222
 223 int toshiba_rbtx4927_irq_nested(int sw_irq)
 224 {
 225         u32 level3;
 226
 227         level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
 228         if (level3) {
 229                 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
 230                 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
 231                         goto RETURN;
 232                 }
 233         }
 234 #ifdef CONFIG_TOSHIBA_FPCIB0
 235         if (tx4927_using_backplane) {
 236                 int irq = i8259_irq();
 237                 if (irq >= 0)
 238                         sw_irq = irq;
 239         }
 240 #endif
 241
 242       RETURN:
 243         return (sw_irq);
 244 }
 245
 246 static struct irqaction toshiba_rbtx4927_irq_ioc_action = {
 247         .handler        = no_action,
 248         .flags          = IRQF_SHARED,
 249         .mask           = CPU_MASK_NONE,
 250         .name           = TOSHIBA_RBTX4927_IOC_NAME
 251 };
 252
 253
 254 /**********************************************************************************/
 255 /* Functions for ioc                                                              */
 256 /**********************************************************************************/
 257
 258
 259 static void __init toshiba_rbtx4927_irq_ioc_init(void)
 260 {
 261         int i;
 262
 263         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT,
 264                                      "beg=%d end=%d\n",
 265                                      TOSHIBA_RBTX4927_IRQ_IOC_BEG,
 266                                      TOSHIBA_RBTX4927_IRQ_IOC_END);
 267
 268         for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
 269              i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
 270                 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
 271                                          handle_level_irq);
 272
 273         setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
 274                   &toshiba_rbtx4927_irq_ioc_action);
 275 }
 276
 277 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
 278 {
 279         volatile unsigned char v;
 280
 281         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
 282                                      "irq=%d\n", irq);
 283
 284         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
 285             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
 286                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 287                                              "bad irq=%d\n", irq);
 288                 panic("\n");
 289         }
 290
 291         v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
 292         v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
 293         writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
 294 }
 295
 296
 297 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
 298 {
 299         volatile unsigned char v;
 300
 301         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
 302                                      "irq=%d\n", irq);
 303
 304         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
 305             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
 306                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
 307                                              "bad irq=%d\n", irq);
 308                 panic("\n");
 309         }
 310
 311         v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
 312         v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
 313         writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
 314         mmiowb();
 315 }
 316
 317
 318 void __init arch_init_irq(void)
 319 {
 320         extern void tx4927_irq_init(void);
 321
 322         tx4927_irq_init();
 323         toshiba_rbtx4927_irq_ioc_init();
 324 #ifdef CONFIG_TOSHIBA_FPCIB0
 325         if (tx4927_using_backplane)
 326                 init_i8259_irqs();
 327 #endif
 328         /* Onboard 10M Ether: High Active */
 329         set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
 330
 331         wbflush();
 332 }
 333
 334 void toshiba_rbtx4927_irq_dump(char *key)
 335 {
 336 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
 337         {
 338                 u32 i, j = 0;
 339                 for (i = 0; i < NR_IRQS; i++) {
 340                         if (strcmp(irq_desc[i].chip->name, "none")
 341                             == 0)
 342                                 continue;
 343
 344                         if ((i >= 1)
 345                             && (irq_desc[i - 1].chip->name ==
 346                                 irq_desc[i].chip->name)) {
 347                                 j++;
 348                         } else {
 349                                 j = 0;
 350                         }
 351                         TOSHIBA_RBTX4927_IRQ_DPRINTK
 352                             (TOSHIBA_RBTX4927_IRQ_INFO,
 353                              "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
 354                              key, i, i, irq_desc[i].status,
 355                              (u32) irq_desc[i].chip,
 356                              (u32) irq_desc[i].action,
 357                              (u32) (irq_desc[i].action ? irq_desc[i].
 358                                     action->handler : 0),
 359                              irq_desc[i].depth,
 360                              irq_desc[i].chip->name, j);
 361                 }
 362         }
 363 #endif
 364 }
 365
 366 void toshiba_rbtx4927_irq_dump_pics(char *s)
 367 {
 368         u32 level0_m;
 369         u32 level0_s;
 370         u32 level1_m;
 371         u32 level1_s;
 372         u32 level2;
 373         u32 level2_p;
 374         u32 level2_s;
 375         u32 level3_m;
 376         u32 level3_s;
 377         u32 level4_m;
 378         u32 level4_s;
 379         u32 level5_m;
 380         u32 level5_s;
 381
 382         if (s == NULL)
 383                 s = "null";
 384
 385         level0_m = (read_c0_status() & 0x0000ff00) >> 8;
 386         level0_s = (read_c0_cause() & 0x0000ff00) >> 8;
 387
 388         level1_m = level0_m;
 389         level1_s = level0_s & 0x87;
 390
 391         level2 = __raw_readl((void __iomem *)0xff1ff6a0UL);
 392         level2_p = (((level2 & 0x10000)) ? 0 : 1);
 393         level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
 394
 395         level3_m = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
 396         level3_s = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
 397
 398         level4_m = inb(0x21);
 399         outb(0x0A, 0x20);
 400         level4_s = inb(0x20);
 401
 402         level5_m = inb(0xa1);
 403         outb(0x0A, 0xa0);
 404         level5_s = inb(0xa0);
 405
 406         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 407                                      "dump_raw_pic() ");
 408         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 409                                      "cp0:m=0x%02x/s=0x%02x ", level0_m,
 410                                      level0_s);
 411         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 412                                      "cp0:m=0x%02x/s=0x%02x ", level1_m,
 413                                      level1_s);
 414         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 415                                      "pic:e=0x%02x/s=0x%02x ", level2_p,
 416                                      level2_s);
 417         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 418                                      "ioc:m=0x%02x/s=0x%02x ", level3_m,
 419                                      level3_s);
 420         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 421                                      "sbm:m=0x%02x/s=0x%02x ", level4_m,
 422                                      level4_s);
 423         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
 424                                      "sbs:m=0x%02x/s=0x%02x ", level5_m,
 425                                      level5_s);
 426         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
 427                                      s);
 428 }