Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / arch / mips / mm / sc-r5k.c
blobf330d38e55753b057c9647c031215c8fb2feb7d0
1 /*
2 * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org),
3 * derived from r4xx0.c by David S. Miller (dm@engr.sgi.com).
4 */
5 #include <linux/init.h>
6 #include <linux/kernel.h>
7 #include <linux/sched.h>
8 #include <linux/mm.h>
10 #include <asm/mipsregs.h>
11 #include <asm/bcache.h>
12 #include <asm/cacheops.h>
13 #include <asm/page.h>
14 #include <asm/pgtable.h>
15 #include <asm/system.h>
16 #include <asm/mmu_context.h>
17 #include <asm/r4kcache.h>
19 /* Secondary cache size in bytes, if present. */
20 static unsigned long scache_size;
22 #define SC_LINE 32
23 #define SC_PAGE (128*SC_LINE)
25 static inline void blast_r5000_scache(void)
27 unsigned long start = INDEX_BASE;
28 unsigned long end = start + scache_size;
30 while(start < end) {
31 cache_op(R5K_Page_Invalidate_S, start);
32 start += SC_PAGE;
36 static void r5k_dma_cache_inv_sc(unsigned long addr, unsigned long size)
38 unsigned long end, a;
40 /* Catch bad driver code */
41 BUG_ON(size == 0);
43 if (size >= scache_size) {
44 blast_r5000_scache();
45 return;
48 /* On the R5000 secondary cache we cannot
49 * invalidate less than a page at a time.
50 * The secondary cache is physically indexed, write-through.
52 a = addr & ~(SC_PAGE - 1);
53 end = (addr + size - 1) & ~(SC_PAGE - 1);
54 while (a <= end) {
55 cache_op(R5K_Page_Invalidate_S, a);
56 a += SC_PAGE;
60 static void r5k_sc_enable(void)
62 unsigned long flags;
64 local_irq_save(flags);
65 set_c0_config(R5K_CONF_SE);
66 blast_r5000_scache();
67 local_irq_restore(flags);
70 static void r5k_sc_disable(void)
72 unsigned long flags;
74 local_irq_save(flags);
75 blast_r5000_scache();
76 clear_c0_config(R5K_CONF_SE);
77 local_irq_restore(flags);
80 static inline int __init r5k_sc_probe(void)
82 unsigned long config = read_c0_config();
84 if (config & CONF_SC)
85 return(0);
87 scache_size = (512 * 1024) << ((config & R5K_CONF_SS) >> 20);
89 printk("R5000 SCACHE size %ldkB, linesize 32 bytes.\n",
90 scache_size >> 10);
92 return 1;
95 static struct bcache_ops r5k_sc_ops = {
96 .bc_enable = r5k_sc_enable,
97 .bc_disable = r5k_sc_disable,
98 .bc_wback_inv = r5k_dma_cache_inv_sc,
99 .bc_inv = r5k_dma_cache_inv_sc
102 void __cpuinit r5k_sc_init(void)
104 if (r5k_sc_probe()) {
105 r5k_sc_enable();
106 bcops = &r5k_sc_ops;