arch/mips/jmr3927/rbhma3100/irq.c

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc.
   4  *              ahennessy@mvista.com
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  *
  10  * Copyright (C) 2000-2001 Toshiba Corporation
  11  *
  12  *  This program is free software; you can redistribute  it and/or modify it
  13  *  under  the terms of  the GNU General  Public License as published by the
  14  *  Free Software Foundation;  either version 2 of the  License, or (at your
  15  *  option) any later version.
  16  *
  17  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  *  You should have received a copy of the  GNU General Public License along
  29  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  30  *  675 Mass Ave, Cambridge, MA 02139, USA.
  31  */
  32 #include <linux/init.h>
  33 #include <linux/sched.h>
  34 #include <linux/types.h>
  35 #include <linux/interrupt.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/mipsregs.h>
  39 #include <asm/system.h>
  40
  41 #include <asm/processor.h>
  42 #include <asm/jmr3927/jmr3927.h>
  43
  44 #if JMR3927_IRQ_END > NR_IRQS
  45 #error JMR3927_IRQ_END > NR_IRQS
  46 #endif
  47
  48 static unsigned char irc_level[TX3927_NUM_IR] = {
  49         5, 5, 5, 5, 5, 5,       /* INT[5:0] */
  50         7, 7,                   /* SIO */
  51         5, 5, 5, 0, 0,          /* DMA, PIO, PCI */
  52         6, 6, 6                 /* TMR */
  53 };
  54
  55 /*
  56  * CP0_STATUS is a thread's resource (saved/restored on context switch).
  57  * So disable_irq/enable_irq MUST handle IOC/IRC registers.
  58  */
  59 static void mask_irq_ioc(unsigned int irq)
  60 {
  61         /* 0: mask */
  62         unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
  63         unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
  64         unsigned int bit = 1 << irq_nr;
  65         jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
  66         /* flush write buffer */
  67         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
  68 }
  69 static void unmask_irq_ioc(unsigned int irq)
  70 {
  71         /* 0: mask */
  72         unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
  73         unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
  74         unsigned int bit = 1 << irq_nr;
  75         jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
  76         /* flush write buffer */
  77         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
  78 }
  79
  80 asmlinkage void plat_irq_dispatch(void)
  81 {
  82         unsigned long cp0_cause = read_c0_cause();
  83         int irq;
  84
  85         if ((cp0_cause & CAUSEF_IP7) == 0)
  86                 return;
  87         irq = (cp0_cause >> CAUSEB_IP2) & 0x0f;
  88
  89         do_IRQ(irq + JMR3927_IRQ_IRC);
  90 }
  91
  92 static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id)
  93 {
  94         unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
  95         int i;
  96
  97         for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
  98                 if (istat & (1 << i)) {
  99                         irq = JMR3927_IRQ_IOC + i;
 100                         do_IRQ(irq);
 101                 }
 102         }
 103         return IRQ_HANDLED;
 104 }
 105
 106 static struct irqaction ioc_action = {
 107         .handler = jmr3927_ioc_interrupt,
 108         .mask = CPU_MASK_NONE,
 109         .name = "IOC",
 110 };
 111
 112 static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
 113 {
 114         printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
 115         printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
 116                tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
 117
 118         return IRQ_HANDLED;
 119 }
 120 static struct irqaction pcierr_action = {
 121         .handler = jmr3927_pcierr_interrupt,
 122         .mask = CPU_MASK_NONE,
 123         .name = "PCI error",
 124 };
 125
 126 static void __init jmr3927_irq_init(void);
 127
 128 void __init arch_init_irq(void)
 129 {
 130         /* Now, interrupt control disabled, */
 131         /* all IRC interrupts are masked, */
 132         /* all IRC interrupt mode are Low Active. */
 133
 134         /* mask all IOC interrupts */
 135         jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
 136         /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
 137         jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
 138
 139         /* clear PCI Soft interrupts */
 140         jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
 141         /* clear PCI Reset interrupts */
 142         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 143
 144         jmr3927_irq_init();
 145
 146         /* setup IOC interrupt 1 (PCI, MODEM) */
 147         setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
 148
 149 #ifdef CONFIG_PCI
 150         setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
 151 #endif
 152
 153         /* enable all CPU interrupt bits. */
 154         set_c0_status(ST0_IM);  /* IE bit is still 0. */
 155 }
 156
 157 static struct irq_chip jmr3927_irq_ioc = {
 158         .name = "jmr3927_ioc",
 159         .ack = mask_irq_ioc,
 160         .mask = mask_irq_ioc,
 161         .mask_ack = mask_irq_ioc,
 162         .unmask = unmask_irq_ioc,
 163 };
 164
 165 static void __init jmr3927_irq_init(void)
 166 {
 167         u32 i;
 168
 169         txx9_irq_init(TX3927_IRC_REG);
 170         for (i = 0; i < TXx9_MAX_IR; i++)
 171                 txx9_irq_set_pri(i, irc_level[i]);
 172         for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
 173                 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
 174 }