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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / arch / mips / au1000 / common / irq.c
blob3c7714f057acf7b01b9d7b4c23db7cff4f6ca1fc
1 /*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ppopov@mvista.com or source@mvista.com
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28 #include <linux/bitops.h>
29 #include <linux/init.h>
30 #include <linux/io.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33
34 #include <asm/irq_cpu.h>
35 #include <asm/mipsregs.h>
36 #include <asm/mach-au1x00/au1000.h>
37 #ifdef CONFIG_MIPS_PB1000
38 #include <asm/mach-pb1x00/pb1000.h>
39 #endif
40
41 #define EXT_INTC0_REQ0 2 /* IP 2 */
42 #define EXT_INTC0_REQ1 3 /* IP 3 */
43 #define EXT_INTC1_REQ0 4 /* IP 4 */
44 #define EXT_INTC1_REQ1 5 /* IP 5 */
45 #define MIPS_TIMER_IP 7 /* IP 7 */
46
47 void (*board_init_irq)(void) __initdata = NULL;
48
49 static DEFINE_SPINLOCK(irq_lock);
50
51 #ifdef CONFIG_PM
52
53 /*
54 * Save/restore the interrupt controller state.
55 * Called from the save/restore core registers as part of the
56 * au_sleep function in power.c.....maybe I should just pm_register()
57 * them instead?
58 */
59 static unsigned int sleep_intctl_config0[2];
60 static unsigned int sleep_intctl_config1[2];
61 static unsigned int sleep_intctl_config2[2];
62 static unsigned int sleep_intctl_src[2];
63 static unsigned int sleep_intctl_assign[2];
64 static unsigned int sleep_intctl_wake[2];
65 static unsigned int sleep_intctl_mask[2];
66
67 void save_au1xxx_intctl(void)
68 {
69 sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
70 sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
71 sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
72 sleep_intctl_src[0] = au_readl(IC0_SRCRD);
73 sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
74 sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
75 sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
76
77 sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
78 sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
79 sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
80 sleep_intctl_src[1] = au_readl(IC1_SRCRD);
81 sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
82 sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
83 sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
84 }
85
86 /*
87 * For most restore operations, we clear the entire register and
88 * then set the bits we found during the save.
89 */
90 void restore_au1xxx_intctl(void)
91 {
92 au_writel(0xffffffff, IC0_MASKCLR); au_sync();
93
94 au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
95 au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
96 au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
97 au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
98 au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
99 au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
100 au_writel(0xffffffff, IC0_SRCCLR); au_sync();
101 au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
102 au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
103 au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
104 au_writel(0xffffffff, IC0_WAKECLR); au_sync();
105 au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
106 au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
107 au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
108 au_writel(0x00000000, IC0_TESTBIT); au_sync();
109
110 au_writel(0xffffffff, IC1_MASKCLR); au_sync();
111
112 au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
113 au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
114 au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
115 au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
116 au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
117 au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
118 au_writel(0xffffffff, IC1_SRCCLR); au_sync();
119 au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
120 au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
121 au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
122 au_writel(0xffffffff, IC1_WAKECLR); au_sync();
123 au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
124 au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
125 au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
126 au_writel(0x00000000, IC1_TESTBIT); au_sync();
127
128 au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
129
130 au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
131 }
132 #endif /* CONFIG_PM */
133
134
135 inline void local_enable_irq(unsigned int irq_nr)
136 {
137 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
138
139 if (bit >= 32) {
140 au_writel(1 << (bit - 32), IC1_MASKSET);
141 au_writel(1 << (bit - 32), IC1_WAKESET);
142 } else {
143 au_writel(1 << bit, IC0_MASKSET);
144 au_writel(1 << bit, IC0_WAKESET);
145 }
146 au_sync();
147 }
148
149
150 inline void local_disable_irq(unsigned int irq_nr)
151 {
152 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
153
154 if (bit >= 32) {
155 au_writel(1 << (bit - 32), IC1_MASKCLR);
156 au_writel(1 << (bit - 32), IC1_WAKECLR);
157 } else {
158 au_writel(1 << bit, IC0_MASKCLR);
159 au_writel(1 << bit, IC0_WAKECLR);
160 }
161 au_sync();
162 }
163
164
165 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
166 {
167 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
168
169 if (bit >= 32) {
170 au_writel(1 << (bit - 32), IC1_RISINGCLR);
171 au_writel(1 << (bit - 32), IC1_MASKCLR);
172 } else {
173 au_writel(1 << bit, IC0_RISINGCLR);
174 au_writel(1 << bit, IC0_MASKCLR);
175 }
176 au_sync();
177 }
178
179
180 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
181 {
182 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
183
184 if (bit >= 32) {
185 au_writel(1 << (bit - 32), IC1_FALLINGCLR);
186 au_writel(1 << (bit - 32), IC1_MASKCLR);
187 } else {
188 au_writel(1 << bit, IC0_FALLINGCLR);
189 au_writel(1 << bit, IC0_MASKCLR);
190 }
191 au_sync();
192 }
193
194
195 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
196 {
197 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
198
199 /*
200 * This may assume that we don't get interrupts from
201 * both edges at once, or if we do, that we don't care.
202 */
203 if (bit >= 32) {
204 au_writel(1 << (bit - 32), IC1_FALLINGCLR);
205 au_writel(1 << (bit - 32), IC1_RISINGCLR);
206 au_writel(1 << (bit - 32), IC1_MASKCLR);
207 } else {
208 au_writel(1 << bit, IC0_FALLINGCLR);
209 au_writel(1 << bit, IC0_RISINGCLR);
210 au_writel(1 << bit, IC0_MASKCLR);
211 }
212 au_sync();
213 }
214
215
216 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
217 {
218
219 local_disable_irq(irq_nr);
220 au_sync();
221 #if defined(CONFIG_MIPS_PB1000)
222 if (irq_nr == AU1000_GPIO_15) {
223 au_writel(0x8000, PB1000_MDR); /* ack int */
224 au_sync();
225 }
226 #endif
227 }
228
229 static void end_irq(unsigned int irq_nr)
230 {
231 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
232 local_enable_irq(irq_nr);
233
234 #if defined(CONFIG_MIPS_PB1000)
235 if (irq_nr == AU1000_GPIO_15) {
236 au_writel(0x4000, PB1000_MDR); /* enable int */
237 au_sync();
238 }
239 #endif
240 }
241
242 unsigned long save_local_and_disable(int controller)
243 {
244 int i;
245 unsigned long flags, mask;
246
247 spin_lock_irqsave(&irq_lock, flags);
248 if (controller) {
249 mask = au_readl(IC1_MASKSET);
250 for (i = 32; i < 64; i++)
251 local_disable_irq(i);
252 } else {
253 mask = au_readl(IC0_MASKSET);
254 for (i = 0; i < 32; i++)
255 local_disable_irq(i);
256 }
257 spin_unlock_irqrestore(&irq_lock, flags);
258
259 return mask;
260 }
261
262 void restore_local_and_enable(int controller, unsigned long mask)
263 {
264 int i;
265 unsigned long flags, new_mask;
266
267 spin_lock_irqsave(&irq_lock, flags);
268 for (i = 0; i < 32; i++) {
269 if (mask & (1 << i)) {
270 if (controller)
271 local_enable_irq(i + 32);
272 else
273 local_enable_irq(i);
274 }
275 }
276 if (controller)
277 new_mask = au_readl(IC1_MASKSET);
278 else
279 new_mask = au_readl(IC0_MASKSET);
280
281 spin_unlock_irqrestore(&irq_lock, flags);
282 }
283
284
285 static struct irq_chip rise_edge_irq_type = {
286 .name = "Au1000 Rise Edge",
287 .ack = mask_and_ack_rise_edge_irq,
288 .mask = local_disable_irq,
289 .mask_ack = mask_and_ack_rise_edge_irq,
290 .unmask = local_enable_irq,
291 .end = end_irq,
292 };
293
294 static struct irq_chip fall_edge_irq_type = {
295 .name = "Au1000 Fall Edge",
296 .ack = mask_and_ack_fall_edge_irq,
297 .mask = local_disable_irq,
298 .mask_ack = mask_and_ack_fall_edge_irq,
299 .unmask = local_enable_irq,
300 .end = end_irq,
301 };
302
303 static struct irq_chip either_edge_irq_type = {
304 .name = "Au1000 Rise or Fall Edge",
305 .ack = mask_and_ack_either_edge_irq,
306 .mask = local_disable_irq,
307 .mask_ack = mask_and_ack_either_edge_irq,
308 .unmask = local_enable_irq,
309 .end = end_irq,
310 };
311
312 static struct irq_chip level_irq_type = {
313 .name = "Au1000 Level",
314 .ack = mask_and_ack_level_irq,
315 .mask = local_disable_irq,
316 .mask_ack = mask_and_ack_level_irq,
317 .unmask = local_enable_irq,
318 .end = end_irq,
319 };
320
321 static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req)
322 {
323 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
324
325 if (irq_nr > AU1000_MAX_INTR)
326 return;
327
328 /* Config2[n], Config1[n], Config0[n] */
329 if (bit >= 32) {
330 switch (type) {
331 case INTC_INT_RISE_EDGE: /* 0:0:1 */
332 au_writel(1 << (bit - 32), IC1_CFG2CLR);
333 au_writel(1 << (bit - 32), IC1_CFG1CLR);
334 au_writel(1 << (bit - 32), IC1_CFG0SET);
335 set_irq_chip(irq_nr, &rise_edge_irq_type);
336 break;
337 case INTC_INT_FALL_EDGE: /* 0:1:0 */
338 au_writel(1 << (bit - 32), IC1_CFG2CLR);
339 au_writel(1 << (bit - 32), IC1_CFG1SET);
340 au_writel(1 << (bit - 32), IC1_CFG0CLR);
341 set_irq_chip(irq_nr, &fall_edge_irq_type);
342 break;
343 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
344 au_writel(1 << (bit - 32), IC1_CFG2CLR);
345 au_writel(1 << (bit - 32), IC1_CFG1SET);
346 au_writel(1 << (bit - 32), IC1_CFG0SET);
347 set_irq_chip(irq_nr, &either_edge_irq_type);
348 break;
349 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
350 au_writel(1 << (bit - 32), IC1_CFG2SET);
351 au_writel(1 << (bit - 32), IC1_CFG1CLR);
352 au_writel(1 << (bit - 32), IC1_CFG0SET);
353 set_irq_chip(irq_nr, &level_irq_type);
354 break;
355 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
356 au_writel(1 << (bit - 32), IC1_CFG2SET);
357 au_writel(1 << (bit - 32), IC1_CFG1SET);
358 au_writel(1 << (bit - 32), IC1_CFG0CLR);
359 set_irq_chip(irq_nr, &level_irq_type);
360 break;
361 case INTC_INT_DISABLED: /* 0:0:0 */
362 au_writel(1 << (bit - 32), IC1_CFG0CLR);
363 au_writel(1 << (bit - 32), IC1_CFG1CLR);
364 au_writel(1 << (bit - 32), IC1_CFG2CLR);
365 break;
366 default: /* disable the interrupt */
367 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
368 type, irq_nr);
369 au_writel(1 << (bit - 32), IC1_CFG0CLR);
370 au_writel(1 << (bit - 32), IC1_CFG1CLR);
371 au_writel(1 << (bit - 32), IC1_CFG2CLR);
372 return;
373 }
374 if (int_req) /* assign to interrupt request 1 */
375 au_writel(1 << (bit - 32), IC1_ASSIGNCLR);
376 else /* assign to interrupt request 0 */
377 au_writel(1 << (bit - 32), IC1_ASSIGNSET);
378 au_writel(1 << (bit - 32), IC1_SRCSET);
379 au_writel(1 << (bit - 32), IC1_MASKCLR);
380 au_writel(1 << (bit - 32), IC1_WAKECLR);
381 } else {
382 switch (type) {
383 case INTC_INT_RISE_EDGE: /* 0:0:1 */
384 au_writel(1 << bit, IC0_CFG2CLR);
385 au_writel(1 << bit, IC0_CFG1CLR);
386 au_writel(1 << bit, IC0_CFG0SET);
387 set_irq_chip(irq_nr, &rise_edge_irq_type);
388 break;
389 case INTC_INT_FALL_EDGE: /* 0:1:0 */
390 au_writel(1 << bit, IC0_CFG2CLR);
391 au_writel(1 << bit, IC0_CFG1SET);
392 au_writel(1 << bit, IC0_CFG0CLR);
393 set_irq_chip(irq_nr, &fall_edge_irq_type);
394 break;
395 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
396 au_writel(1 << bit, IC0_CFG2CLR);
397 au_writel(1 << bit, IC0_CFG1SET);
398 au_writel(1 << bit, IC0_CFG0SET);
399 set_irq_chip(irq_nr, &either_edge_irq_type);
400 break;
401 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
402 au_writel(1 << bit, IC0_CFG2SET);
403 au_writel(1 << bit, IC0_CFG1CLR);
404 au_writel(1 << bit, IC0_CFG0SET);
405 set_irq_chip(irq_nr, &level_irq_type);
406 break;
407 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
408 au_writel(1 << bit, IC0_CFG2SET);
409 au_writel(1 << bit, IC0_CFG1SET);
410 au_writel(1 << bit, IC0_CFG0CLR);
411 set_irq_chip(irq_nr, &level_irq_type);
412 break;
413 case INTC_INT_DISABLED: /* 0:0:0 */
414 au_writel(1 << bit, IC0_CFG0CLR);
415 au_writel(1 << bit, IC0_CFG1CLR);
416 au_writel(1 << bit, IC0_CFG2CLR);
417 break;
418 default: /* disable the interrupt */
419 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
420 type, irq_nr);
421 au_writel(1 << bit, IC0_CFG0CLR);
422 au_writel(1 << bit, IC0_CFG1CLR);
423 au_writel(1 << bit, IC0_CFG2CLR);
424 return;
425 }
426 if (int_req) /* assign to interrupt request 1 */
427 au_writel(1 << bit, IC0_ASSIGNCLR);
428 else /* assign to interrupt request 0 */
429 au_writel(1 << bit, IC0_ASSIGNSET);
430 au_writel(1 << bit, IC0_SRCSET);
431 au_writel(1 << bit, IC0_MASKCLR);
432 au_writel(1 << bit, IC0_WAKECLR);
433 }
434 au_sync();
435 }
436
437 /*
438 * Interrupts are nested. Even if an interrupt handler is registered
439 * as "fast", we might get another interrupt before we return from
440 * intcX_reqX_irqdispatch().
441 */
442
443 static void intc0_req0_irqdispatch(void)
444 {
445 static unsigned long intc0_req0;
446 unsigned int bit;
447
448 intc0_req0 |= au_readl(IC0_REQ0INT);
449
450 if (!intc0_req0)
451 return;
452
453 #ifdef AU1000_USB_DEV_REQ_INT
454 /*
455 * Because of the tight timing of SETUP token to reply
456 * transactions, the USB devices-side packet complete
457 * interrupt needs the highest priority.
458 */
459 if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) {
460 intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT);
461 do_IRQ(AU1000_USB_DEV_REQ_INT);
462 return;
463 }
464 #endif
465 bit = __ffs(intc0_req0);
466 intc0_req0 &= ~(1 << bit);
467 do_IRQ(AU1000_INTC0_INT_BASE + bit);
468 }
469
470
471 static void intc0_req1_irqdispatch(void)
472 {
473 static unsigned long intc0_req1;
474 unsigned int bit;
475
476 intc0_req1 |= au_readl(IC0_REQ1INT);
477
478 if (!intc0_req1)
479 return;
480
481 bit = __ffs(intc0_req1);
482 intc0_req1 &= ~(1 << bit);
483 do_IRQ(AU1000_INTC0_INT_BASE + bit);
484 }
485
486
487 /*
488 * Interrupt Controller 1:
489 * interrupts 32 - 63
490 */
491 static void intc1_req0_irqdispatch(void)
492 {
493 static unsigned long intc1_req0;
494 unsigned int bit;
495
496 intc1_req0 |= au_readl(IC1_REQ0INT);
497
498 if (!intc1_req0)
499 return;
500
501 bit = __ffs(intc1_req0);
502 intc1_req0 &= ~(1 << bit);
503 do_IRQ(AU1000_INTC1_INT_BASE + bit);
504 }
505
506
507 static void intc1_req1_irqdispatch(void)
508 {
509 static unsigned long intc1_req1;
510 unsigned int bit;
511
512 intc1_req1 |= au_readl(IC1_REQ1INT);
513
514 if (!intc1_req1)
515 return;
516
517 bit = __ffs(intc1_req1);
518 intc1_req1 &= ~(1 << bit);
519 do_IRQ(AU1000_INTC1_INT_BASE + bit);
520 }
521
522 asmlinkage void plat_irq_dispatch(void)
523 {
524 unsigned int pending = read_c0_status() & read_c0_cause();
525
526 if (pending & CAUSEF_IP7)
527 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
528 else if (pending & CAUSEF_IP2)
529 intc0_req0_irqdispatch();
530 else if (pending & CAUSEF_IP3)
531 intc0_req1_irqdispatch();
532 else if (pending & CAUSEF_IP4)
533 intc1_req0_irqdispatch();
534 else if (pending & CAUSEF_IP5)
535 intc1_req1_irqdispatch();
536 else
537 spurious_interrupt();
538 }
539
540 void __init arch_init_irq(void)
541 {
542 int i;
543 struct au1xxx_irqmap *imp;
544 extern struct au1xxx_irqmap au1xxx_irq_map[];
545 extern struct au1xxx_irqmap au1xxx_ic0_map[];
546 extern int au1xxx_nr_irqs;
547 extern int au1xxx_ic0_nr_irqs;
548
549 /*
550 * Initialize interrupt controllers to a safe state.
551 */
552 au_writel(0xffffffff, IC0_CFG0CLR);
553 au_writel(0xffffffff, IC0_CFG1CLR);
554 au_writel(0xffffffff, IC0_CFG2CLR);
555 au_writel(0xffffffff, IC0_MASKCLR);
556 au_writel(0xffffffff, IC0_ASSIGNSET);
557 au_writel(0xffffffff, IC0_WAKECLR);
558 au_writel(0xffffffff, IC0_SRCSET);
559 au_writel(0xffffffff, IC0_FALLINGCLR);
560 au_writel(0xffffffff, IC0_RISINGCLR);
561 au_writel(0x00000000, IC0_TESTBIT);
562
563 au_writel(0xffffffff, IC1_CFG0CLR);
564 au_writel(0xffffffff, IC1_CFG1CLR);
565 au_writel(0xffffffff, IC1_CFG2CLR);
566 au_writel(0xffffffff, IC1_MASKCLR);
567 au_writel(0xffffffff, IC1_ASSIGNSET);
568 au_writel(0xffffffff, IC1_WAKECLR);
569 au_writel(0xffffffff, IC1_SRCSET);
570 au_writel(0xffffffff, IC1_FALLINGCLR);
571 au_writel(0xffffffff, IC1_RISINGCLR);
572 au_writel(0x00000000, IC1_TESTBIT);
573
574 mips_cpu_irq_init();
575
576 /*
577 * Initialize IC0, which is fixed per processor.
578 */
579 imp = au1xxx_ic0_map;
580 for (i = 0; i < au1xxx_ic0_nr_irqs; i++) {
581 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
582 imp++;
583 }
584
585 /*
586 * Now set up the irq mapping for the board.
587 */
588 imp = au1xxx_irq_map;
589 for (i = 0; i < au1xxx_nr_irqs; i++) {
590 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
591 imp++;
592 }
593
594 set_c0_status(ALLINTS);
595
596 /* Board specific IRQ initialization.
597 */
598 if (board_init_irq)
599 board_init_irq();
600 }
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