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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / arch / ia64 / kernel / minstate.h
blobc9ac8bada786f19888bab6b93536054da44f599f
1
2 #include <asm/cache.h>
3
4 #include "entry.h"
5
6 /*
7 * DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
8 * the minimum state necessary that allows us to turn psr.ic back
9 * on.
10 *
11 * Assumed state upon entry:
12 * psr.ic: off
13 * r31: contains saved predicates (pr)
14 *
15 * Upon exit, the state is as follows:
16 * psr.ic: off
17 * r2 = points to &pt_regs.r16
18 * r8 = contents of ar.ccv
19 * r9 = contents of ar.csd
20 * r10 = contents of ar.ssd
21 * r11 = FPSR_DEFAULT
22 * r12 = kernel sp (kernel virtual address)
23 * r13 = points to current task_struct (kernel virtual address)
24 * p15 = TRUE if psr.i is set in cr.ipsr
25 * predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
26 * preserved
27 *
28 * Note that psr.ic is NOT turned on by this macro. This is so that
29 * we can pass interruption state as arguments to a handler.
30 */
31 #define DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \
32 mov r16=IA64_KR(CURRENT); /* M */ \
33 mov r27=ar.rsc; /* M */ \
34 mov r20=r1; /* A */ \
35 mov r25=ar.unat; /* M */ \
36 mov r29=cr.ipsr; /* M */ \
37 mov r26=ar.pfs; /* I */ \
38 mov r28=cr.iip; /* M */ \
39 mov r21=ar.fpsr; /* M */ \
40 COVER; /* B;; (or nothing) */ \
41 ;; \
42 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16; \
43 ;; \
44 ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \
45 st1 [r16]=r0; /* clear current->thread.on_ustack flag */ \
46 adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 \
47 /* switch from user to kernel RBS: */ \
48 ;; \
49 invala; /* M */ \
50 SAVE_IFS; \
51 cmp.eq pKStk,pUStk=r0,r17; /* are we in kernel mode already? */ \
52 ;; \
53 (pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
54 ;; \
55 (pUStk) mov.m r24=ar.rnat; \
56 (pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \
57 (pKStk) mov r1=sp; /* get sp */ \
58 ;; \
59 (pUStk) lfetch.fault.excl.nt1 [r22]; \
60 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
61 (pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \
62 ;; \
63 (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
64 (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \
65 ;; \
66 (pUStk) mov r18=ar.bsp; \
67 (pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \
68 adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \
69 adds r16=PT(CR_IPSR),r1; \
70 ;; \
71 lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
72 st8 [r16]=r29; /* save cr.ipsr */ \
73 ;; \
74 lfetch.fault.excl.nt1 [r17]; \
75 tbit.nz p15,p0=r29,IA64_PSR_I_BIT; \
76 mov r29=b0 \
77 ;; \
78 adds r16=PT(R8),r1; /* initialize first base pointer */ \
79 adds r17=PT(R9),r1; /* initialize second base pointer */ \
80 (pKStk) mov r18=r0; /* make sure r18 isn't NaT */ \
81 ;; \
82 .mem.offset 0,0; st8.spill [r16]=r8,16; \
83 .mem.offset 8,0; st8.spill [r17]=r9,16; \
84 ;; \
85 .mem.offset 0,0; st8.spill [r16]=r10,24; \
86 .mem.offset 8,0; st8.spill [r17]=r11,24; \
87 ;; \
88 st8 [r16]=r28,16; /* save cr.iip */ \
89 st8 [r17]=r30,16; /* save cr.ifs */ \
90 (pUStk) sub r18=r18,r22; /* r18=RSE.ndirty*8 */ \
91 mov r8=ar.ccv; \
92 mov r9=ar.csd; \
93 mov r10=ar.ssd; \
94 movl r11=FPSR_DEFAULT; /* L-unit */ \
95 ;; \
96 st8 [r16]=r25,16; /* save ar.unat */ \
97 st8 [r17]=r26,16; /* save ar.pfs */ \
98 shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \
99 ;; \
100 st8 [r16]=r27,16; /* save ar.rsc */ \
101 (pUStk) st8 [r17]=r24,16; /* save ar.rnat */ \
102 (pKStk) adds r17=16,r17; /* skip over ar_rnat field */ \
103 ;; /* avoid RAW on r16 & r17 */ \
104 (pUStk) st8 [r16]=r23,16; /* save ar.bspstore */ \
105 st8 [r17]=r31,16; /* save predicates */ \
106 (pKStk) adds r16=16,r16; /* skip over ar_bspstore field */ \
107 ;; \
108 st8 [r16]=r29,16; /* save b0 */ \
109 st8 [r17]=r18,16; /* save ar.rsc value for "loadrs" */ \
110 cmp.eq pNonSys,pSys=r0,r0 /* initialize pSys=0, pNonSys=1 */ \
111 ;; \
112 .mem.offset 0,0; st8.spill [r16]=r20,16; /* save original r1 */ \
113 .mem.offset 8,0; st8.spill [r17]=r12,16; \
114 adds r12=-16,r1; /* switch to kernel memory stack (with 16 bytes of scratch) */ \
115 ;; \
116 .mem.offset 0,0; st8.spill [r16]=r13,16; \
117 .mem.offset 8,0; st8.spill [r17]=r21,16; /* save ar.fpsr */ \
118 mov r13=IA64_KR(CURRENT); /* establish `current' */ \
119 ;; \
120 .mem.offset 0,0; st8.spill [r16]=r15,16; \
121 .mem.offset 8,0; st8.spill [r17]=r14,16; \
122 ;; \
123 .mem.offset 0,0; st8.spill [r16]=r2,16; \
124 .mem.offset 8,0; st8.spill [r17]=r3,16; \
125 adds r2=IA64_PT_REGS_R16_OFFSET,r1; \
126 ;; \
127 EXTRA; \
128 movl r1=__gp; /* establish kernel global pointer */ \
129 ;; \
130 bsw.1; /* switch back to bank 1 (must be last in insn group) */ \
131 ;;
132
133 /*
134 * SAVE_REST saves the remainder of pt_regs (with psr.ic on).
135 *
136 * Assumed state upon entry:
137 * psr.ic: on
138 * r2: points to &pt_regs.r16
139 * r3: points to &pt_regs.r17
140 * r8: contents of ar.ccv
141 * r9: contents of ar.csd
142 * r10: contents of ar.ssd
143 * r11: FPSR_DEFAULT
144 *
145 * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
146 */
147 #define SAVE_REST \
148 .mem.offset 0,0; st8.spill [r2]=r16,16; \
149 .mem.offset 8,0; st8.spill [r3]=r17,16; \
150 ;; \
151 .mem.offset 0,0; st8.spill [r2]=r18,16; \
152 .mem.offset 8,0; st8.spill [r3]=r19,16; \
153 ;; \
154 .mem.offset 0,0; st8.spill [r2]=r20,16; \
155 .mem.offset 8,0; st8.spill [r3]=r21,16; \
156 mov r18=b6; \
157 ;; \
158 .mem.offset 0,0; st8.spill [r2]=r22,16; \
159 .mem.offset 8,0; st8.spill [r3]=r23,16; \
160 mov r19=b7; \
161 ;; \
162 .mem.offset 0,0; st8.spill [r2]=r24,16; \
163 .mem.offset 8,0; st8.spill [r3]=r25,16; \
164 ;; \
165 .mem.offset 0,0; st8.spill [r2]=r26,16; \
166 .mem.offset 8,0; st8.spill [r3]=r27,16; \
167 ;; \
168 .mem.offset 0,0; st8.spill [r2]=r28,16; \
169 .mem.offset 8,0; st8.spill [r3]=r29,16; \
170 ;; \
171 .mem.offset 0,0; st8.spill [r2]=r30,16; \
172 .mem.offset 8,0; st8.spill [r3]=r31,32; \
173 ;; \
174 mov ar.fpsr=r11; /* M-unit */ \
175 st8 [r2]=r8,8; /* ar.ccv */ \
176 adds r24=PT(B6)-PT(F7),r3; \
177 ;; \
178 stf.spill [r2]=f6,32; \
179 stf.spill [r3]=f7,32; \
180 ;; \
181 stf.spill [r2]=f8,32; \
182 stf.spill [r3]=f9,32; \
183 ;; \
184 stf.spill [r2]=f10; \
185 stf.spill [r3]=f11; \
186 adds r25=PT(B7)-PT(F11),r3; \
187 ;; \
188 st8 [r24]=r18,16; /* b6 */ \
189 st8 [r25]=r19,16; /* b7 */ \
190 ;; \
191 st8 [r24]=r9; /* ar.csd */ \
192 st8 [r25]=r10; /* ar.ssd */ \
193 ;;
194
195 #define SAVE_MIN_WITH_COVER DO_SAVE_MIN(cover, mov r30=cr.ifs,)
196 #define SAVE_MIN_WITH_COVER_R19 DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19)
197 #define SAVE_MIN DO_SAVE_MIN( , mov r30=r0, )
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