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Committer: Michael Beasley <mike@snafu.setup>
[mikesnafu-overlay.git] / arch / arm / plat-omap / gpio.c
blob8c78e4e57b5cf09c44547eb74c277ed3fc7d4803
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20
21 #include <asm/hardware.h>
22 #include <asm/irq.h>
23 #include <asm/arch/irqs.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/mach/irq.h>
26
27 #include <asm/io.h>
28
29 /*
30 * OMAP1510 GPIO registers
31 */
32 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
33 #define OMAP1510_GPIO_DATA_INPUT 0x00
34 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
35 #define OMAP1510_GPIO_DIR_CONTROL 0x08
36 #define OMAP1510_GPIO_INT_CONTROL 0x0c
37 #define OMAP1510_GPIO_INT_MASK 0x10
38 #define OMAP1510_GPIO_INT_STATUS 0x14
39 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40
41 #define OMAP1510_IH_GPIO_BASE 64
42
43 /*
44 * OMAP1610 specific GPIO registers
45 */
46 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
50 #define OMAP1610_GPIO_REVISION 0x0000
51 #define OMAP1610_GPIO_SYSCONFIG 0x0010
52 #define OMAP1610_GPIO_SYSSTATUS 0x0014
53 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
54 #define OMAP1610_GPIO_IRQENABLE1 0x001c
55 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
63 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
65 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
66 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
67
68 /*
69 * OMAP730 specific GPIO registers
70 */
71 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
77 #define OMAP730_GPIO_DATA_INPUT 0x00
78 #define OMAP730_GPIO_DATA_OUTPUT 0x04
79 #define OMAP730_GPIO_DIR_CONTROL 0x08
80 #define OMAP730_GPIO_INT_CONTROL 0x0c
81 #define OMAP730_GPIO_INT_MASK 0x10
82 #define OMAP730_GPIO_INT_STATUS 0x14
83
84 /*
85 * omap24xx specific GPIO registers
86 */
87 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
91
92 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
97
98 #define OMAP24XX_GPIO_REVISION 0x0000
99 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
100 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
101 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
104 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
121
122 /*
123 * omap34xx specific GPIO registers
124 */
125
126 #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127 #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128 #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129 #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130 #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131 #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
132
133
134 struct gpio_bank {
135 void __iomem *base;
136 u16 irq;
137 u16 virtual_irq_start;
138 int method;
139 u32 reserved_map;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
141 u32 suspend_wakeup;
142 u32 saved_wakeup;
143 #endif
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
147
148 u32 saved_datain;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
151 #endif
152 spinlock_t lock;
153 };
154
155 #define METHOD_MPUIO 0
156 #define METHOD_GPIO_1510 1
157 #define METHOD_GPIO_1610 2
158 #define METHOD_GPIO_730 3
159 #define METHOD_GPIO_24XX 4
160
161 #ifdef CONFIG_ARCH_OMAP16XX
162 static struct gpio_bank gpio_bank_1610[5] = {
163 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
164 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
168 };
169 #endif
170
171 #ifdef CONFIG_ARCH_OMAP15XX
172 static struct gpio_bank gpio_bank_1510[2] = {
173 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
174 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
175 };
176 #endif
177
178 #ifdef CONFIG_ARCH_OMAP730
179 static struct gpio_bank gpio_bank_730[7] = {
180 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
181 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
182 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
183 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
184 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
185 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
186 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
187 };
188 #endif
189
190 #ifdef CONFIG_ARCH_OMAP24XX
191
192 static struct gpio_bank gpio_bank_242x[4] = {
193 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
194 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
197 };
198
199 static struct gpio_bank gpio_bank_243x[5] = {
200 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
201 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
205 };
206
207 #endif
208
209 #ifdef CONFIG_ARCH_OMAP34XX
210 static struct gpio_bank gpio_bank_34xx[6] = {
211 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
217 };
218
219 #endif
220
221 static struct gpio_bank *gpio_bank;
222 static int gpio_bank_count;
223
224 static inline struct gpio_bank *get_gpio_bank(int gpio)
225 {
226 if (cpu_is_omap15xx()) {
227 if (OMAP_GPIO_IS_MPUIO(gpio))
228 return &gpio_bank[0];
229 return &gpio_bank[1];
230 }
231 if (cpu_is_omap16xx()) {
232 if (OMAP_GPIO_IS_MPUIO(gpio))
233 return &gpio_bank[0];
234 return &gpio_bank[1 + (gpio >> 4)];
235 }
236 if (cpu_is_omap730()) {
237 if (OMAP_GPIO_IS_MPUIO(gpio))
238 return &gpio_bank[0];
239 return &gpio_bank[1 + (gpio >> 5)];
240 }
241 if (cpu_is_omap24xx())
242 return &gpio_bank[gpio >> 5];
243 if (cpu_is_omap34xx())
244 return &gpio_bank[gpio >> 5];
245 }
246
247 static inline int get_gpio_index(int gpio)
248 {
249 if (cpu_is_omap730())
250 return gpio & 0x1f;
251 if (cpu_is_omap24xx())
252 return gpio & 0x1f;
253 if (cpu_is_omap34xx())
254 return gpio & 0x1f;
255 return gpio & 0x0f;
256 }
257
258 static inline int gpio_valid(int gpio)
259 {
260 if (gpio < 0)
261 return -1;
262 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
263 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
264 return -1;
265 return 0;
266 }
267 if (cpu_is_omap15xx() && gpio < 16)
268 return 0;
269 if ((cpu_is_omap16xx()) && gpio < 64)
270 return 0;
271 if (cpu_is_omap730() && gpio < 192)
272 return 0;
273 if (cpu_is_omap24xx() && gpio < 128)
274 return 0;
275 if (cpu_is_omap34xx() && gpio < 160)
276 return 0;
277 return -1;
278 }
279
280 static int check_gpio(int gpio)
281 {
282 if (unlikely(gpio_valid(gpio)) < 0) {
283 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
284 dump_stack();
285 return -1;
286 }
287 return 0;
288 }
289
290 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
291 {
292 void __iomem *reg = bank->base;
293 u32 l;
294
295 switch (bank->method) {
296 #ifdef CONFIG_ARCH_OMAP1
297 case METHOD_MPUIO:
298 reg += OMAP_MPUIO_IO_CNTL;
299 break;
300 #endif
301 #ifdef CONFIG_ARCH_OMAP15XX
302 case METHOD_GPIO_1510:
303 reg += OMAP1510_GPIO_DIR_CONTROL;
304 break;
305 #endif
306 #ifdef CONFIG_ARCH_OMAP16XX
307 case METHOD_GPIO_1610:
308 reg += OMAP1610_GPIO_DIRECTION;
309 break;
310 #endif
311 #ifdef CONFIG_ARCH_OMAP730
312 case METHOD_GPIO_730:
313 reg += OMAP730_GPIO_DIR_CONTROL;
314 break;
315 #endif
316 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
317 case METHOD_GPIO_24XX:
318 reg += OMAP24XX_GPIO_OE;
319 break;
320 #endif
321 default:
322 WARN_ON(1);
323 return;
324 }
325 l = __raw_readl(reg);
326 if (is_input)
327 l |= 1 << gpio;
328 else
329 l &= ~(1 << gpio);
330 __raw_writel(l, reg);
331 }
332
333 void omap_set_gpio_direction(int gpio, int is_input)
334 {
335 struct gpio_bank *bank;
336 unsigned long flags;
337
338 if (check_gpio(gpio) < 0)
339 return;
340 bank = get_gpio_bank(gpio);
341 spin_lock_irqsave(&bank->lock, flags);
342 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
343 spin_unlock_irqrestore(&bank->lock, flags);
344 }
345
346 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
347 {
348 void __iomem *reg = bank->base;
349 u32 l = 0;
350
351 switch (bank->method) {
352 #ifdef CONFIG_ARCH_OMAP1
353 case METHOD_MPUIO:
354 reg += OMAP_MPUIO_OUTPUT;
355 l = __raw_readl(reg);
356 if (enable)
357 l |= 1 << gpio;
358 else
359 l &= ~(1 << gpio);
360 break;
361 #endif
362 #ifdef CONFIG_ARCH_OMAP15XX
363 case METHOD_GPIO_1510:
364 reg += OMAP1510_GPIO_DATA_OUTPUT;
365 l = __raw_readl(reg);
366 if (enable)
367 l |= 1 << gpio;
368 else
369 l &= ~(1 << gpio);
370 break;
371 #endif
372 #ifdef CONFIG_ARCH_OMAP16XX
373 case METHOD_GPIO_1610:
374 if (enable)
375 reg += OMAP1610_GPIO_SET_DATAOUT;
376 else
377 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
378 l = 1 << gpio;
379 break;
380 #endif
381 #ifdef CONFIG_ARCH_OMAP730
382 case METHOD_GPIO_730:
383 reg += OMAP730_GPIO_DATA_OUTPUT;
384 l = __raw_readl(reg);
385 if (enable)
386 l |= 1 << gpio;
387 else
388 l &= ~(1 << gpio);
389 break;
390 #endif
391 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
392 case METHOD_GPIO_24XX:
393 if (enable)
394 reg += OMAP24XX_GPIO_SETDATAOUT;
395 else
396 reg += OMAP24XX_GPIO_CLEARDATAOUT;
397 l = 1 << gpio;
398 break;
399 #endif
400 default:
401 WARN_ON(1);
402 return;
403 }
404 __raw_writel(l, reg);
405 }
406
407 void omap_set_gpio_dataout(int gpio, int enable)
408 {
409 struct gpio_bank *bank;
410 unsigned long flags;
411
412 if (check_gpio(gpio) < 0)
413 return;
414 bank = get_gpio_bank(gpio);
415 spin_lock_irqsave(&bank->lock, flags);
416 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
417 spin_unlock_irqrestore(&bank->lock, flags);
418 }
419
420 int omap_get_gpio_datain(int gpio)
421 {
422 struct gpio_bank *bank;
423 void __iomem *reg;
424
425 if (check_gpio(gpio) < 0)
426 return -EINVAL;
427 bank = get_gpio_bank(gpio);
428 reg = bank->base;
429 switch (bank->method) {
430 #ifdef CONFIG_ARCH_OMAP1
431 case METHOD_MPUIO:
432 reg += OMAP_MPUIO_INPUT_LATCH;
433 break;
434 #endif
435 #ifdef CONFIG_ARCH_OMAP15XX
436 case METHOD_GPIO_1510:
437 reg += OMAP1510_GPIO_DATA_INPUT;
438 break;
439 #endif
440 #ifdef CONFIG_ARCH_OMAP16XX
441 case METHOD_GPIO_1610:
442 reg += OMAP1610_GPIO_DATAIN;
443 break;
444 #endif
445 #ifdef CONFIG_ARCH_OMAP730
446 case METHOD_GPIO_730:
447 reg += OMAP730_GPIO_DATA_INPUT;
448 break;
449 #endif
450 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
451 case METHOD_GPIO_24XX:
452 reg += OMAP24XX_GPIO_DATAIN;
453 break;
454 #endif
455 default:
456 return -EINVAL;
457 }
458 return (__raw_readl(reg)
459 & (1 << get_gpio_index(gpio))) != 0;
460 }
461
462 #define MOD_REG_BIT(reg, bit_mask, set) \
463 do { \
464 int l = __raw_readl(base + reg); \
465 if (set) l |= bit_mask; \
466 else l &= ~bit_mask; \
467 __raw_writel(l, base + reg); \
468 } while(0)
469
470 void omap_set_gpio_debounce(int gpio, int enable)
471 {
472 struct gpio_bank *bank;
473 void __iomem *reg;
474 u32 val, l = 1 << get_gpio_index(gpio);
475
476 if (cpu_class_is_omap1())
477 return;
478
479 bank = get_gpio_bank(gpio);
480 reg = bank->base;
481
482 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
483 val = __raw_readl(reg);
484
485 if (enable)
486 val |= l;
487 else
488 val &= ~l;
489
490 __raw_writel(val, reg);
491 }
492 EXPORT_SYMBOL(omap_set_gpio_debounce);
493
494 void omap_set_gpio_debounce_time(int gpio, int enc_time)
495 {
496 struct gpio_bank *bank;
497 void __iomem *reg;
498
499 if (cpu_class_is_omap1())
500 return;
501
502 bank = get_gpio_bank(gpio);
503 reg = bank->base;
504
505 enc_time &= 0xff;
506 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
507 __raw_writel(enc_time, reg);
508 }
509 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
510
511 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
512 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
513 int trigger)
514 {
515 void __iomem *base = bank->base;
516 u32 gpio_bit = 1 << gpio;
517
518 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
519 trigger & __IRQT_LOWLVL);
520 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
521 trigger & __IRQT_HIGHLVL);
522 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
523 trigger & __IRQT_RISEDGE);
524 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
525 trigger & __IRQT_FALEDGE);
526
527 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
528 if (trigger != 0)
529 __raw_writel(1 << gpio, bank->base
530 + OMAP24XX_GPIO_SETWKUENA);
531 else
532 __raw_writel(1 << gpio, bank->base
533 + OMAP24XX_GPIO_CLEARWKUENA);
534 } else {
535 if (trigger != 0)
536 bank->enabled_non_wakeup_gpios |= gpio_bit;
537 else
538 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
539 }
540
541 /*
542 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
543 * level triggering requested.
544 */
545 }
546 #endif
547
548 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
549 {
550 void __iomem *reg = bank->base;
551 u32 l = 0;
552
553 switch (bank->method) {
554 #ifdef CONFIG_ARCH_OMAP1
555 case METHOD_MPUIO:
556 reg += OMAP_MPUIO_GPIO_INT_EDGE;
557 l = __raw_readl(reg);
558 if (trigger & __IRQT_RISEDGE)
559 l |= 1 << gpio;
560 else if (trigger & __IRQT_FALEDGE)
561 l &= ~(1 << gpio);
562 else
563 goto bad;
564 break;
565 #endif
566 #ifdef CONFIG_ARCH_OMAP15XX
567 case METHOD_GPIO_1510:
568 reg += OMAP1510_GPIO_INT_CONTROL;
569 l = __raw_readl(reg);
570 if (trigger & __IRQT_RISEDGE)
571 l |= 1 << gpio;
572 else if (trigger & __IRQT_FALEDGE)
573 l &= ~(1 << gpio);
574 else
575 goto bad;
576 break;
577 #endif
578 #ifdef CONFIG_ARCH_OMAP16XX
579 case METHOD_GPIO_1610:
580 if (gpio & 0x08)
581 reg += OMAP1610_GPIO_EDGE_CTRL2;
582 else
583 reg += OMAP1610_GPIO_EDGE_CTRL1;
584 gpio &= 0x07;
585 l = __raw_readl(reg);
586 l &= ~(3 << (gpio << 1));
587 if (trigger & __IRQT_RISEDGE)
588 l |= 2 << (gpio << 1);
589 if (trigger & __IRQT_FALEDGE)
590 l |= 1 << (gpio << 1);
591 if (trigger)
592 /* Enable wake-up during idle for dynamic tick */
593 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
594 else
595 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
596 break;
597 #endif
598 #ifdef CONFIG_ARCH_OMAP730
599 case METHOD_GPIO_730:
600 reg += OMAP730_GPIO_INT_CONTROL;
601 l = __raw_readl(reg);
602 if (trigger & __IRQT_RISEDGE)
603 l |= 1 << gpio;
604 else if (trigger & __IRQT_FALEDGE)
605 l &= ~(1 << gpio);
606 else
607 goto bad;
608 break;
609 #endif
610 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
611 case METHOD_GPIO_24XX:
612 set_24xx_gpio_triggering(bank, gpio, trigger);
613 break;
614 #endif
615 default:
616 goto bad;
617 }
618 __raw_writel(l, reg);
619 return 0;
620 bad:
621 return -EINVAL;
622 }
623
624 static int gpio_irq_type(unsigned irq, unsigned type)
625 {
626 struct gpio_bank *bank;
627 unsigned gpio;
628 int retval;
629 unsigned long flags;
630
631 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
632 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
633 else
634 gpio = irq - IH_GPIO_BASE;
635
636 if (check_gpio(gpio) < 0)
637 return -EINVAL;
638
639 if (type & ~IRQ_TYPE_SENSE_MASK)
640 return -EINVAL;
641
642 /* OMAP1 allows only only edge triggering */
643 if (!cpu_class_is_omap2()
644 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
645 return -EINVAL;
646
647 bank = get_irq_chip_data(irq);
648 spin_lock_irqsave(&bank->lock, flags);
649 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
650 if (retval == 0) {
651 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
652 irq_desc[irq].status |= type;
653 }
654 spin_unlock_irqrestore(&bank->lock, flags);
655 return retval;
656 }
657
658 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
659 {
660 void __iomem *reg = bank->base;
661
662 switch (bank->method) {
663 #ifdef CONFIG_ARCH_OMAP1
664 case METHOD_MPUIO:
665 /* MPUIO irqstatus is reset by reading the status register,
666 * so do nothing here */
667 return;
668 #endif
669 #ifdef CONFIG_ARCH_OMAP15XX
670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_STATUS;
672 break;
673 #endif
674 #ifdef CONFIG_ARCH_OMAP16XX
675 case METHOD_GPIO_1610:
676 reg += OMAP1610_GPIO_IRQSTATUS1;
677 break;
678 #endif
679 #ifdef CONFIG_ARCH_OMAP730
680 case METHOD_GPIO_730:
681 reg += OMAP730_GPIO_INT_STATUS;
682 break;
683 #endif
684 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
685 case METHOD_GPIO_24XX:
686 reg += OMAP24XX_GPIO_IRQSTATUS1;
687 break;
688 #endif
689 default:
690 WARN_ON(1);
691 return;
692 }
693 __raw_writel(gpio_mask, reg);
694
695 /* Workaround for clearing DSP GPIO interrupts to allow retention */
696 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
697 if (cpu_is_omap24xx() || cpu_is_omap34xx())
698 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
699 #endif
700 }
701
702 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
703 {
704 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
705 }
706
707 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
708 {
709 void __iomem *reg = bank->base;
710 int inv = 0;
711 u32 l;
712 u32 mask;
713
714 switch (bank->method) {
715 #ifdef CONFIG_ARCH_OMAP1
716 case METHOD_MPUIO:
717 reg += OMAP_MPUIO_GPIO_MASKIT;
718 mask = 0xffff;
719 inv = 1;
720 break;
721 #endif
722 #ifdef CONFIG_ARCH_OMAP15XX
723 case METHOD_GPIO_1510:
724 reg += OMAP1510_GPIO_INT_MASK;
725 mask = 0xffff;
726 inv = 1;
727 break;
728 #endif
729 #ifdef CONFIG_ARCH_OMAP16XX
730 case METHOD_GPIO_1610:
731 reg += OMAP1610_GPIO_IRQENABLE1;
732 mask = 0xffff;
733 break;
734 #endif
735 #ifdef CONFIG_ARCH_OMAP730
736 case METHOD_GPIO_730:
737 reg += OMAP730_GPIO_INT_MASK;
738 mask = 0xffffffff;
739 inv = 1;
740 break;
741 #endif
742 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
743 case METHOD_GPIO_24XX:
744 reg += OMAP24XX_GPIO_IRQENABLE1;
745 mask = 0xffffffff;
746 break;
747 #endif
748 default:
749 WARN_ON(1);
750 return 0;
751 }
752
753 l = __raw_readl(reg);
754 if (inv)
755 l = ~l;
756 l &= mask;
757 return l;
758 }
759
760 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
761 {
762 void __iomem *reg = bank->base;
763 u32 l;
764
765 switch (bank->method) {
766 #ifdef CONFIG_ARCH_OMAP1
767 case METHOD_MPUIO:
768 reg += OMAP_MPUIO_GPIO_MASKIT;
769 l = __raw_readl(reg);
770 if (enable)
771 l &= ~(gpio_mask);
772 else
773 l |= gpio_mask;
774 break;
775 #endif
776 #ifdef CONFIG_ARCH_OMAP15XX
777 case METHOD_GPIO_1510:
778 reg += OMAP1510_GPIO_INT_MASK;
779 l = __raw_readl(reg);
780 if (enable)
781 l &= ~(gpio_mask);
782 else
783 l |= gpio_mask;
784 break;
785 #endif
786 #ifdef CONFIG_ARCH_OMAP16XX
787 case METHOD_GPIO_1610:
788 if (enable)
789 reg += OMAP1610_GPIO_SET_IRQENABLE1;
790 else
791 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
792 l = gpio_mask;
793 break;
794 #endif
795 #ifdef CONFIG_ARCH_OMAP730
796 case METHOD_GPIO_730:
797 reg += OMAP730_GPIO_INT_MASK;
798 l = __raw_readl(reg);
799 if (enable)
800 l &= ~(gpio_mask);
801 else
802 l |= gpio_mask;
803 break;
804 #endif
805 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
806 case METHOD_GPIO_24XX:
807 if (enable)
808 reg += OMAP24XX_GPIO_SETIRQENABLE1;
809 else
810 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
811 l = gpio_mask;
812 break;
813 #endif
814 default:
815 WARN_ON(1);
816 return;
817 }
818 __raw_writel(l, reg);
819 }
820
821 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
822 {
823 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
824 }
825
826 /*
827 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
828 * 1510 does not seem to have a wake-up register. If JTAG is connected
829 * to the target, system will wake up always on GPIO events. While
830 * system is running all registered GPIO interrupts need to have wake-up
831 * enabled. When system is suspended, only selected GPIO interrupts need
832 * to have wake-up enabled.
833 */
834 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
835 {
836 unsigned long flags;
837
838 switch (bank->method) {
839 #ifdef CONFIG_ARCH_OMAP16XX
840 case METHOD_MPUIO:
841 case METHOD_GPIO_1610:
842 spin_lock_irqsave(&bank->lock, flags);
843 if (enable) {
844 bank->suspend_wakeup |= (1 << gpio);
845 enable_irq_wake(bank->irq);
846 } else {
847 disable_irq_wake(bank->irq);
848 bank->suspend_wakeup &= ~(1 << gpio);
849 }
850 spin_unlock_irqrestore(&bank->lock, flags);
851 return 0;
852 #endif
853 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
854 case METHOD_GPIO_24XX:
855 if (bank->non_wakeup_gpios & (1 << gpio)) {
856 printk(KERN_ERR "Unable to modify wakeup on "
857 "non-wakeup GPIO%d\n",
858 (bank - gpio_bank) * 32 + gpio);
859 return -EINVAL;
860 }
861 spin_lock_irqsave(&bank->lock, flags);
862 if (enable) {
863 bank->suspend_wakeup |= (1 << gpio);
864 enable_irq_wake(bank->irq);
865 } else {
866 disable_irq_wake(bank->irq);
867 bank->suspend_wakeup &= ~(1 << gpio);
868 }
869 spin_unlock_irqrestore(&bank->lock, flags);
870 return 0;
871 #endif
872 default:
873 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
874 bank->method);
875 return -EINVAL;
876 }
877 }
878
879 static void _reset_gpio(struct gpio_bank *bank, int gpio)
880 {
881 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
882 _set_gpio_irqenable(bank, gpio, 0);
883 _clear_gpio_irqstatus(bank, gpio);
884 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
885 }
886
887 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
888 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
889 {
890 unsigned int gpio = irq - IH_GPIO_BASE;
891 struct gpio_bank *bank;
892 int retval;
893
894 if (check_gpio(gpio) < 0)
895 return -ENODEV;
896 bank = get_irq_chip_data(irq);
897 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
898
899 return retval;
900 }
901
902 int omap_request_gpio(int gpio)
903 {
904 struct gpio_bank *bank;
905 unsigned long flags;
906
907 if (check_gpio(gpio) < 0)
908 return -EINVAL;
909
910 bank = get_gpio_bank(gpio);
911 spin_lock_irqsave(&bank->lock, flags);
912 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
913 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
914 dump_stack();
915 spin_unlock_irqrestore(&bank->lock, flags);
916 return -1;
917 }
918 bank->reserved_map |= (1 << get_gpio_index(gpio));
919
920 /* Set trigger to none. You need to enable the desired trigger with
921 * request_irq() or set_irq_type().
922 */
923 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
924
925 #ifdef CONFIG_ARCH_OMAP15XX
926 if (bank->method == METHOD_GPIO_1510) {
927 void __iomem *reg;
928
929 /* Claim the pin for MPU */
930 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
931 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
932 }
933 #endif
934 spin_unlock_irqrestore(&bank->lock, flags);
935
936 return 0;
937 }
938
939 void omap_free_gpio(int gpio)
940 {
941 struct gpio_bank *bank;
942 unsigned long flags;
943
944 if (check_gpio(gpio) < 0)
945 return;
946 bank = get_gpio_bank(gpio);
947 spin_lock_irqsave(&bank->lock, flags);
948 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
949 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
950 dump_stack();
951 spin_unlock_irqrestore(&bank->lock, flags);
952 return;
953 }
954 #ifdef CONFIG_ARCH_OMAP16XX
955 if (bank->method == METHOD_GPIO_1610) {
956 /* Disable wake-up during idle for dynamic tick */
957 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
958 __raw_writel(1 << get_gpio_index(gpio), reg);
959 }
960 #endif
961 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
962 if (bank->method == METHOD_GPIO_24XX) {
963 /* Disable wake-up during idle for dynamic tick */
964 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
965 __raw_writel(1 << get_gpio_index(gpio), reg);
966 }
967 #endif
968 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
969 _reset_gpio(bank, gpio);
970 spin_unlock_irqrestore(&bank->lock, flags);
971 }
972
973 /*
974 * We need to unmask the GPIO bank interrupt as soon as possible to
975 * avoid missing GPIO interrupts for other lines in the bank.
976 * Then we need to mask-read-clear-unmask the triggered GPIO lines
977 * in the bank to avoid missing nested interrupts for a GPIO line.
978 * If we wait to unmask individual GPIO lines in the bank after the
979 * line's interrupt handler has been run, we may miss some nested
980 * interrupts.
981 */
982 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
983 {
984 void __iomem *isr_reg = NULL;
985 u32 isr;
986 unsigned int gpio_irq;
987 struct gpio_bank *bank;
988 u32 retrigger = 0;
989 int unmasked = 0;
990
991 desc->chip->ack(irq);
992
993 bank = get_irq_data(irq);
994 #ifdef CONFIG_ARCH_OMAP1
995 if (bank->method == METHOD_MPUIO)
996 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
997 #endif
998 #ifdef CONFIG_ARCH_OMAP15XX
999 if (bank->method == METHOD_GPIO_1510)
1000 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1001 #endif
1002 #if defined(CONFIG_ARCH_OMAP16XX)
1003 if (bank->method == METHOD_GPIO_1610)
1004 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1005 #endif
1006 #ifdef CONFIG_ARCH_OMAP730
1007 if (bank->method == METHOD_GPIO_730)
1008 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1009 #endif
1010 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1011 if (bank->method == METHOD_GPIO_24XX)
1012 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1013 #endif
1014 while(1) {
1015 u32 isr_saved, level_mask = 0;
1016 u32 enabled;
1017
1018 enabled = _get_gpio_irqbank_mask(bank);
1019 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1020
1021 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1022 isr &= 0x0000ffff;
1023
1024 if (cpu_class_is_omap2()) {
1025 level_mask =
1026 __raw_readl(bank->base +
1027 OMAP24XX_GPIO_LEVELDETECT0) |
1028 __raw_readl(bank->base +
1029 OMAP24XX_GPIO_LEVELDETECT1);
1030 level_mask &= enabled;
1031 }
1032
1033 /* clear edge sensitive interrupts before handler(s) are
1034 called so that we don't miss any interrupt occurred while
1035 executing them */
1036 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1037 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1038 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1039
1040 /* if there is only edge sensitive GPIO pin interrupts
1041 configured, we could unmask GPIO bank interrupt immediately */
1042 if (!level_mask && !unmasked) {
1043 unmasked = 1;
1044 desc->chip->unmask(irq);
1045 }
1046
1047 isr |= retrigger;
1048 retrigger = 0;
1049 if (!isr)
1050 break;
1051
1052 gpio_irq = bank->virtual_irq_start;
1053 for (; isr != 0; isr >>= 1, gpio_irq++) {
1054 struct irq_desc *d;
1055 int irq_mask;
1056 if (!(isr & 1))
1057 continue;
1058 d = irq_desc + gpio_irq;
1059 /* Don't run the handler if it's already running
1060 * or was disabled lazely.
1061 */
1062 if (unlikely((d->depth ||
1063 (d->status & IRQ_INPROGRESS)))) {
1064 irq_mask = 1 <<
1065 (gpio_irq - bank->virtual_irq_start);
1066 /* The unmasking will be done by
1067 * enable_irq in case it is disabled or
1068 * after returning from the handler if
1069 * it's already running.
1070 */
1071 _enable_gpio_irqbank(bank, irq_mask, 0);
1072 if (!d->depth) {
1073 /* Level triggered interrupts
1074 * won't ever be reentered
1075 */
1076 BUG_ON(level_mask & irq_mask);
1077 d->status |= IRQ_PENDING;
1078 }
1079 continue;
1080 }
1081
1082 desc_handle_irq(gpio_irq, d);
1083
1084 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1085 irq_mask = 1 <<
1086 (gpio_irq - bank->virtual_irq_start);
1087 d->status &= ~IRQ_PENDING;
1088 _enable_gpio_irqbank(bank, irq_mask, 1);
1089 retrigger |= irq_mask;
1090 }
1091 }
1092
1093 if (cpu_class_is_omap2()) {
1094 /* clear level sensitive interrupts after handler(s) */
1095 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1096 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1097 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1098 }
1099
1100 }
1101 /* if bank has any level sensitive GPIO pin interrupt
1102 configured, we must unmask the bank interrupt only after
1103 handler(s) are executed in order to avoid spurious bank
1104 interrupt */
1105 if (!unmasked)
1106 desc->chip->unmask(irq);
1107
1108 }
1109
1110 static void gpio_irq_shutdown(unsigned int irq)
1111 {
1112 unsigned int gpio = irq - IH_GPIO_BASE;
1113 struct gpio_bank *bank = get_irq_chip_data(irq);
1114
1115 _reset_gpio(bank, gpio);
1116 }
1117
1118 static void gpio_ack_irq(unsigned int irq)
1119 {
1120 unsigned int gpio = irq - IH_GPIO_BASE;
1121 struct gpio_bank *bank = get_irq_chip_data(irq);
1122
1123 _clear_gpio_irqstatus(bank, gpio);
1124 }
1125
1126 static void gpio_mask_irq(unsigned int irq)
1127 {
1128 unsigned int gpio = irq - IH_GPIO_BASE;
1129 struct gpio_bank *bank = get_irq_chip_data(irq);
1130
1131 _set_gpio_irqenable(bank, gpio, 0);
1132 }
1133
1134 static void gpio_unmask_irq(unsigned int irq)
1135 {
1136 unsigned int gpio = irq - IH_GPIO_BASE;
1137 struct gpio_bank *bank = get_irq_chip_data(irq);
1138
1139 _set_gpio_irqenable(bank, gpio, 1);
1140 }
1141
1142 static struct irq_chip gpio_irq_chip = {
1143 .name = "GPIO",
1144 .shutdown = gpio_irq_shutdown,
1145 .ack = gpio_ack_irq,
1146 .mask = gpio_mask_irq,
1147 .unmask = gpio_unmask_irq,
1148 .set_type = gpio_irq_type,
1149 .set_wake = gpio_wake_enable,
1150 };
1151
1152 /*---------------------------------------------------------------------*/
1153
1154 #ifdef CONFIG_ARCH_OMAP1
1155
1156 /* MPUIO uses the always-on 32k clock */
1157
1158 static void mpuio_ack_irq(unsigned int irq)
1159 {
1160 /* The ISR is reset automatically, so do nothing here. */
1161 }
1162
1163 static void mpuio_mask_irq(unsigned int irq)
1164 {
1165 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1166 struct gpio_bank *bank = get_irq_chip_data(irq);
1167
1168 _set_gpio_irqenable(bank, gpio, 0);
1169 }
1170
1171 static void mpuio_unmask_irq(unsigned int irq)
1172 {
1173 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1174 struct gpio_bank *bank = get_irq_chip_data(irq);
1175
1176 _set_gpio_irqenable(bank, gpio, 1);
1177 }
1178
1179 static struct irq_chip mpuio_irq_chip = {
1180 .name = "MPUIO",
1181 .ack = mpuio_ack_irq,
1182 .mask = mpuio_mask_irq,
1183 .unmask = mpuio_unmask_irq,
1184 .set_type = gpio_irq_type,
1185 #ifdef CONFIG_ARCH_OMAP16XX
1186 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1187 .set_wake = gpio_wake_enable,
1188 #endif
1189 };
1190
1191
1192 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1193
1194
1195 #ifdef CONFIG_ARCH_OMAP16XX
1196
1197 #include <linux/platform_device.h>
1198
1199 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1200 {
1201 struct gpio_bank *bank = platform_get_drvdata(pdev);
1202 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1203 unsigned long flags;
1204
1205 spin_lock_irqsave(&bank->lock, flags);
1206 bank->saved_wakeup = __raw_readl(mask_reg);
1207 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1208 spin_unlock_irqrestore(&bank->lock, flags);
1209
1210 return 0;
1211 }
1212
1213 static int omap_mpuio_resume_early(struct platform_device *pdev)
1214 {
1215 struct gpio_bank *bank = platform_get_drvdata(pdev);
1216 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1217 unsigned long flags;
1218
1219 spin_lock_irqsave(&bank->lock, flags);
1220 __raw_writel(bank->saved_wakeup, mask_reg);
1221 spin_unlock_irqrestore(&bank->lock, flags);
1222
1223 return 0;
1224 }
1225
1226 /* use platform_driver for this, now that there's no longer any
1227 * point to sys_device (other than not disturbing old code).
1228 */
1229 static struct platform_driver omap_mpuio_driver = {
1230 .suspend_late = omap_mpuio_suspend_late,
1231 .resume_early = omap_mpuio_resume_early,
1232 .driver = {
1233 .name = "mpuio",
1234 },
1235 };
1236
1237 static struct platform_device omap_mpuio_device = {
1238 .name = "mpuio",
1239 .id = -1,
1240 .dev = {
1241 .driver = &omap_mpuio_driver.driver,
1242 }
1243 /* could list the /proc/iomem resources */
1244 };
1245
1246 static inline void mpuio_init(void)
1247 {
1248 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1249
1250 if (platform_driver_register(&omap_mpuio_driver) == 0)
1251 (void) platform_device_register(&omap_mpuio_device);
1252 }
1253
1254 #else
1255 static inline void mpuio_init(void) {}
1256 #endif /* 16xx */
1257
1258 #else
1259
1260 extern struct irq_chip mpuio_irq_chip;
1261
1262 #define bank_is_mpuio(bank) 0
1263 static inline void mpuio_init(void) {}
1264
1265 #endif
1266
1267 /*---------------------------------------------------------------------*/
1268
1269 static int initialized;
1270 #if !defined(CONFIG_ARCH_OMAP3)
1271 static struct clk * gpio_ick;
1272 #endif
1273
1274 #if defined(CONFIG_ARCH_OMAP2)
1275 static struct clk * gpio_fck;
1276 #endif
1277
1278 #if defined(CONFIG_ARCH_OMAP2430)
1279 static struct clk * gpio5_ick;
1280 static struct clk * gpio5_fck;
1281 #endif
1282
1283 #if defined(CONFIG_ARCH_OMAP3)
1284 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1285 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1286 #endif
1287
1288 /* This lock class tells lockdep that GPIO irqs are in a different
1289 * category than their parents, so it won't report false recursion.
1290 */
1291 static struct lock_class_key gpio_lock_class;
1292
1293 static int __init _omap_gpio_init(void)
1294 {
1295 int i;
1296 struct gpio_bank *bank;
1297 #if defined(CONFIG_ARCH_OMAP3)
1298 char clk_name[11];
1299 #endif
1300
1301 initialized = 1;
1302
1303 #if defined(CONFIG_ARCH_OMAP1)
1304 if (cpu_is_omap15xx()) {
1305 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1306 if (IS_ERR(gpio_ick))
1307 printk("Could not get arm_gpio_ck\n");
1308 else
1309 clk_enable(gpio_ick);
1310 }
1311 #endif
1312 #if defined(CONFIG_ARCH_OMAP2)
1313 if (cpu_class_is_omap2()) {
1314 gpio_ick = clk_get(NULL, "gpios_ick");
1315 if (IS_ERR(gpio_ick))
1316 printk("Could not get gpios_ick\n");
1317 else
1318 clk_enable(gpio_ick);
1319 gpio_fck = clk_get(NULL, "gpios_fck");
1320 if (IS_ERR(gpio_fck))
1321 printk("Could not get gpios_fck\n");
1322 else
1323 clk_enable(gpio_fck);
1324
1325 /*
1326 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1327 */
1328 #if defined(CONFIG_ARCH_OMAP2430)
1329 if (cpu_is_omap2430()) {
1330 gpio5_ick = clk_get(NULL, "gpio5_ick");
1331 if (IS_ERR(gpio5_ick))
1332 printk("Could not get gpio5_ick\n");
1333 else
1334 clk_enable(gpio5_ick);
1335 gpio5_fck = clk_get(NULL, "gpio5_fck");
1336 if (IS_ERR(gpio5_fck))
1337 printk("Could not get gpio5_fck\n");
1338 else
1339 clk_enable(gpio5_fck);
1340 }
1341 #endif
1342 }
1343 #endif
1344
1345 #if defined(CONFIG_ARCH_OMAP3)
1346 if (cpu_is_omap34xx()) {
1347 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1348 sprintf(clk_name, "gpio%d_ick", i + 1);
1349 gpio_iclks[i] = clk_get(NULL, clk_name);
1350 if (IS_ERR(gpio_iclks[i]))
1351 printk(KERN_ERR "Could not get %s\n", clk_name);
1352 else
1353 clk_enable(gpio_iclks[i]);
1354 sprintf(clk_name, "gpio%d_fck", i + 1);
1355 gpio_fclks[i] = clk_get(NULL, clk_name);
1356 if (IS_ERR(gpio_fclks[i]))
1357 printk(KERN_ERR "Could not get %s\n", clk_name);
1358 else
1359 clk_enable(gpio_fclks[i]);
1360 }
1361 }
1362 #endif
1363
1364
1365 #ifdef CONFIG_ARCH_OMAP15XX
1366 if (cpu_is_omap15xx()) {
1367 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1368 gpio_bank_count = 2;
1369 gpio_bank = gpio_bank_1510;
1370 }
1371 #endif
1372 #if defined(CONFIG_ARCH_OMAP16XX)
1373 if (cpu_is_omap16xx()) {
1374 u32 rev;
1375
1376 gpio_bank_count = 5;
1377 gpio_bank = gpio_bank_1610;
1378 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1379 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1380 (rev >> 4) & 0x0f, rev & 0x0f);
1381 }
1382 #endif
1383 #ifdef CONFIG_ARCH_OMAP730
1384 if (cpu_is_omap730()) {
1385 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1386 gpio_bank_count = 7;
1387 gpio_bank = gpio_bank_730;
1388 }
1389 #endif
1390
1391 #ifdef CONFIG_ARCH_OMAP24XX
1392 if (cpu_is_omap242x()) {
1393 int rev;
1394
1395 gpio_bank_count = 4;
1396 gpio_bank = gpio_bank_242x;
1397 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1398 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1399 (rev >> 4) & 0x0f, rev & 0x0f);
1400 }
1401 if (cpu_is_omap243x()) {
1402 int rev;
1403
1404 gpio_bank_count = 5;
1405 gpio_bank = gpio_bank_243x;
1406 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1407 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1408 (rev >> 4) & 0x0f, rev & 0x0f);
1409 }
1410 #endif
1411 #ifdef CONFIG_ARCH_OMAP34XX
1412 if (cpu_is_omap34xx()) {
1413 int rev;
1414
1415 gpio_bank_count = OMAP34XX_NR_GPIOS;
1416 gpio_bank = gpio_bank_34xx;
1417 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1418 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1419 (rev >> 4) & 0x0f, rev & 0x0f);
1420 }
1421 #endif
1422 for (i = 0; i < gpio_bank_count; i++) {
1423 int j, gpio_count = 16;
1424
1425 bank = &gpio_bank[i];
1426 bank->reserved_map = 0;
1427 bank->base = IO_ADDRESS(bank->base);
1428 spin_lock_init(&bank->lock);
1429 if (bank_is_mpuio(bank))
1430 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1431 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1432 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1433 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1434 }
1435 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1436 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1437 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1438 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1439 }
1440 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1441 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1442 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1443
1444 gpio_count = 32; /* 730 has 32-bit GPIOs */
1445 }
1446
1447 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1448 if (bank->method == METHOD_GPIO_24XX) {
1449 static const u32 non_wakeup_gpios[] = {
1450 0xe203ffc0, 0x08700040
1451 };
1452
1453 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1454 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1455 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1456
1457 /* Initialize interface clock ungated, module enabled */
1458 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1459 if (i < ARRAY_SIZE(non_wakeup_gpios))
1460 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1461 gpio_count = 32;
1462 }
1463 #endif
1464 for (j = bank->virtual_irq_start;
1465 j < bank->virtual_irq_start + gpio_count; j++) {
1466 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1467 set_irq_chip_data(j, bank);
1468 if (bank_is_mpuio(bank))
1469 set_irq_chip(j, &mpuio_irq_chip);
1470 else
1471 set_irq_chip(j, &gpio_irq_chip);
1472 set_irq_handler(j, handle_simple_irq);
1473 set_irq_flags(j, IRQF_VALID);
1474 }
1475 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1476 set_irq_data(bank->irq, bank);
1477 }
1478
1479 /* Enable system clock for GPIO module.
1480 * The CAM_CLK_CTRL *is* really the right place. */
1481 if (cpu_is_omap16xx())
1482 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1483
1484 /* Enable autoidle for the OCP interface */
1485 if (cpu_is_omap24xx())
1486 omap_writel(1 << 0, 0x48019010);
1487 if (cpu_is_omap34xx())
1488 omap_writel(1 << 0, 0x48306814);
1489
1490 return 0;
1491 }
1492
1493 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1494 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1495 {
1496 int i;
1497
1498 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1499 return 0;
1500
1501 for (i = 0; i < gpio_bank_count; i++) {
1502 struct gpio_bank *bank = &gpio_bank[i];
1503 void __iomem *wake_status;
1504 void __iomem *wake_clear;
1505 void __iomem *wake_set;
1506 unsigned long flags;
1507
1508 switch (bank->method) {
1509 #ifdef CONFIG_ARCH_OMAP16XX
1510 case METHOD_GPIO_1610:
1511 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1512 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1513 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1514 break;
1515 #endif
1516 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1517 case METHOD_GPIO_24XX:
1518 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1519 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1520 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1521 break;
1522 #endif
1523 default:
1524 continue;
1525 }
1526
1527 spin_lock_irqsave(&bank->lock, flags);
1528 bank->saved_wakeup = __raw_readl(wake_status);
1529 __raw_writel(0xffffffff, wake_clear);
1530 __raw_writel(bank->suspend_wakeup, wake_set);
1531 spin_unlock_irqrestore(&bank->lock, flags);
1532 }
1533
1534 return 0;
1535 }
1536
1537 static int omap_gpio_resume(struct sys_device *dev)
1538 {
1539 int i;
1540
1541 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1542 return 0;
1543
1544 for (i = 0; i < gpio_bank_count; i++) {
1545 struct gpio_bank *bank = &gpio_bank[i];
1546 void __iomem *wake_clear;
1547 void __iomem *wake_set;
1548 unsigned long flags;
1549
1550 switch (bank->method) {
1551 #ifdef CONFIG_ARCH_OMAP16XX
1552 case METHOD_GPIO_1610:
1553 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1554 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1555 break;
1556 #endif
1557 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1558 case METHOD_GPIO_24XX:
1559 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1560 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1561 break;
1562 #endif
1563 default:
1564 continue;
1565 }
1566
1567 spin_lock_irqsave(&bank->lock, flags);
1568 __raw_writel(0xffffffff, wake_clear);
1569 __raw_writel(bank->saved_wakeup, wake_set);
1570 spin_unlock_irqrestore(&bank->lock, flags);
1571 }
1572
1573 return 0;
1574 }
1575
1576 static struct sysdev_class omap_gpio_sysclass = {
1577 .name = "gpio",
1578 .suspend = omap_gpio_suspend,
1579 .resume = omap_gpio_resume,
1580 };
1581
1582 static struct sys_device omap_gpio_device = {
1583 .id = 0,
1584 .cls = &omap_gpio_sysclass,
1585 };
1586
1587 #endif
1588
1589 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1590
1591 static int workaround_enabled;
1592
1593 void omap2_gpio_prepare_for_retention(void)
1594 {
1595 int i, c = 0;
1596
1597 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1598 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1599 for (i = 0; i < gpio_bank_count; i++) {
1600 struct gpio_bank *bank = &gpio_bank[i];
1601 u32 l1, l2;
1602
1603 if (!(bank->enabled_non_wakeup_gpios))
1604 continue;
1605 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1606 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1607 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1608 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1609 #endif
1610 bank->saved_fallingdetect = l1;
1611 bank->saved_risingdetect = l2;
1612 l1 &= ~bank->enabled_non_wakeup_gpios;
1613 l2 &= ~bank->enabled_non_wakeup_gpios;
1614 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1615 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1616 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1617 #endif
1618 c++;
1619 }
1620 if (!c) {
1621 workaround_enabled = 0;
1622 return;
1623 }
1624 workaround_enabled = 1;
1625 }
1626
1627 void omap2_gpio_resume_after_retention(void)
1628 {
1629 int i;
1630
1631 if (!workaround_enabled)
1632 return;
1633 for (i = 0; i < gpio_bank_count; i++) {
1634 struct gpio_bank *bank = &gpio_bank[i];
1635 u32 l;
1636
1637 if (!(bank->enabled_non_wakeup_gpios))
1638 continue;
1639 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1640 __raw_writel(bank->saved_fallingdetect,
1641 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1642 __raw_writel(bank->saved_risingdetect,
1643 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1644 #endif
1645 /* Check if any of the non-wakeup interrupt GPIOs have changed
1646 * state. If so, generate an IRQ by software. This is
1647 * horribly racy, but it's the best we can do to work around
1648 * this silicon bug. */
1649 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1650 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1651 #endif
1652 l ^= bank->saved_datain;
1653 l &= bank->non_wakeup_gpios;
1654 if (l) {
1655 u32 old0, old1;
1656 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1657 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1658 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1659 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1660 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1661 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1662 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1663 #endif
1664 }
1665 }
1666
1667 }
1668
1669 #endif
1670
1671 /*
1672 * This may get called early from board specific init
1673 * for boards that have interrupts routed via FPGA.
1674 */
1675 int __init omap_gpio_init(void)
1676 {
1677 if (!initialized)
1678 return _omap_gpio_init();
1679 else
1680 return 0;
1681 }
1682
1683 static int __init omap_gpio_sysinit(void)
1684 {
1685 int ret = 0;
1686
1687 if (!initialized)
1688 ret = _omap_gpio_init();
1689
1690 mpuio_init();
1691
1692 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1693 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1694 if (ret == 0) {
1695 ret = sysdev_class_register(&omap_gpio_sysclass);
1696 if (ret == 0)
1697 ret = sysdev_register(&omap_gpio_device);
1698 }
1699 }
1700 #endif
1701
1702 return ret;
1703 }
1704
1705 EXPORT_SYMBOL(omap_request_gpio);
1706 EXPORT_SYMBOL(omap_free_gpio);
1707 EXPORT_SYMBOL(omap_set_gpio_direction);
1708 EXPORT_SYMBOL(omap_set_gpio_dataout);
1709 EXPORT_SYMBOL(omap_get_gpio_datain);
1710
1711 arch_initcall(omap_gpio_sysinit);
1712
1713
1714 #ifdef CONFIG_DEBUG_FS
1715
1716 #include <linux/debugfs.h>
1717 #include <linux/seq_file.h>
1718
1719 static int gpio_is_input(struct gpio_bank *bank, int mask)
1720 {
1721 void __iomem *reg = bank->base;
1722
1723 switch (bank->method) {
1724 case METHOD_MPUIO:
1725 reg += OMAP_MPUIO_IO_CNTL;
1726 break;
1727 case METHOD_GPIO_1510:
1728 reg += OMAP1510_GPIO_DIR_CONTROL;
1729 break;
1730 case METHOD_GPIO_1610:
1731 reg += OMAP1610_GPIO_DIRECTION;
1732 break;
1733 case METHOD_GPIO_730:
1734 reg += OMAP730_GPIO_DIR_CONTROL;
1735 break;
1736 case METHOD_GPIO_24XX:
1737 reg += OMAP24XX_GPIO_OE;
1738 break;
1739 }
1740 return __raw_readl(reg) & mask;
1741 }
1742
1743
1744 static int dbg_gpio_show(struct seq_file *s, void *unused)
1745 {
1746 unsigned i, j, gpio;
1747
1748 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1749 struct gpio_bank *bank = gpio_bank + i;
1750 unsigned bankwidth = 16;
1751 u32 mask = 1;
1752
1753 if (bank_is_mpuio(bank))
1754 gpio = OMAP_MPUIO(0);
1755 else if (cpu_class_is_omap2() || cpu_is_omap730())
1756 bankwidth = 32;
1757
1758 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1759 unsigned irq, value, is_in, irqstat;
1760
1761 if (!(bank->reserved_map & mask))
1762 continue;
1763
1764 irq = bank->virtual_irq_start + j;
1765 value = omap_get_gpio_datain(gpio);
1766 is_in = gpio_is_input(bank, mask);
1767
1768 if (bank_is_mpuio(bank))
1769 seq_printf(s, "MPUIO %2d: ", j);
1770 else
1771 seq_printf(s, "GPIO %3d: ", gpio);
1772 seq_printf(s, "%s %s",
1773 is_in ? "in " : "out",
1774 value ? "hi" : "lo");
1775
1776 irqstat = irq_desc[irq].status;
1777 if (is_in && ((bank->suspend_wakeup & mask)
1778 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1779 char *trigger = NULL;
1780
1781 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1782 case IRQ_TYPE_EDGE_FALLING:
1783 trigger = "falling";
1784 break;
1785 case IRQ_TYPE_EDGE_RISING:
1786 trigger = "rising";
1787 break;
1788 case IRQ_TYPE_EDGE_BOTH:
1789 trigger = "bothedge";
1790 break;
1791 case IRQ_TYPE_LEVEL_LOW:
1792 trigger = "low";
1793 break;
1794 case IRQ_TYPE_LEVEL_HIGH:
1795 trigger = "high";
1796 break;
1797 case IRQ_TYPE_NONE:
1798 trigger = "(unspecified)";
1799 break;
1800 }
1801 seq_printf(s, ", irq-%d %s%s",
1802 irq, trigger,
1803 (bank->suspend_wakeup & mask)
1804 ? " wakeup" : "");
1805 }
1806 seq_printf(s, "\n");
1807 }
1808
1809 if (bank_is_mpuio(bank)) {
1810 seq_printf(s, "\n");
1811 gpio = 0;
1812 }
1813 }
1814 return 0;
1815 }
1816
1817 static int dbg_gpio_open(struct inode *inode, struct file *file)
1818 {
1819 return single_open(file, dbg_gpio_show, &inode->i_private);
1820 }
1821
1822 static const struct file_operations debug_fops = {
1823 .open = dbg_gpio_open,
1824 .read = seq_read,
1825 .llseek = seq_lseek,
1826 .release = single_release,
1827 };
1828
1829 static int __init omap_gpio_debuginit(void)
1830 {
1831 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1832 NULL, NULL, &debug_fops);
1833 return 0;
1834 }
1835 late_initcall(omap_gpio_debuginit);
1836 #endif
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