arch/arm/mach-imx/irq.c

   1 /*
   2  *  linux/arch/arm/mach-imx/irq.c
   3  *
   4  *  Copyright (C) 1999 ARM Limited
   5  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  *  03/03/2004   Sascha Hauer <sascha@saschahauer.de>
  22  *               Copied from the motorola bsp package and added gpio demux
  23  *               interrupt handler
  24  */
  25
  26 #include <linux/init.h>
  27 #include <linux/list.h>
  28 #include <linux/timer.h>
  29
  30 #include <asm/hardware.h>
  31 #include <asm/irq.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/mach/irq.h>
  35
  36 /*
  37  *
  38  * We simply use the ENABLE DISABLE registers inside of the IMX
  39  * to turn on/off specific interrupts.  FIXME- We should
  40  * also add support for the accelerated interrupt controller
  41  * by putting offets to irq jump code in the appropriate
  42  * places.
  43  *
  44  */
  45
  46 #define INTCNTL_OFF               0x00
  47 #define NIMASK_OFF                0x04
  48 #define INTENNUM_OFF              0x08
  49 #define INTDISNUM_OFF             0x0C
  50 #define INTENABLEH_OFF            0x10
  51 #define INTENABLEL_OFF            0x14
  52 #define INTTYPEH_OFF              0x18
  53 #define INTTYPEL_OFF              0x1C
  54 #define NIPRIORITY_OFF(x)         (0x20+4*(7-(x)))
  55 #define NIVECSR_OFF               0x40
  56 #define FIVECSR_OFF               0x44
  57 #define INTSRCH_OFF               0x48
  58 #define INTSRCL_OFF               0x4C
  59 #define INTFRCH_OFF               0x50
  60 #define INTFRCL_OFF               0x54
  61 #define NIPNDH_OFF                0x58
  62 #define NIPNDL_OFF                0x5C
  63 #define FIPNDH_OFF                0x60
  64 #define FIPNDL_OFF                0x64
  65
  66 #define VA_AITC_BASE              IO_ADDRESS(IMX_AITC_BASE)
  67 #define IMX_AITC_INTCNTL         (VA_AITC_BASE + INTCNTL_OFF)
  68 #define IMX_AITC_NIMASK          (VA_AITC_BASE + NIMASK_OFF)
  69 #define IMX_AITC_INTENNUM        (VA_AITC_BASE + INTENNUM_OFF)
  70 #define IMX_AITC_INTDISNUM       (VA_AITC_BASE + INTDISNUM_OFF)
  71 #define IMX_AITC_INTENABLEH      (VA_AITC_BASE + INTENABLEH_OFF)
  72 #define IMX_AITC_INTENABLEL      (VA_AITC_BASE + INTENABLEL_OFF)
  73 #define IMX_AITC_INTTYPEH        (VA_AITC_BASE + INTTYPEH_OFF)
  74 #define IMX_AITC_INTTYPEL        (VA_AITC_BASE + INTTYPEL_OFF)
  75 #define IMX_AITC_NIPRIORITY(x)   (VA_AITC_BASE + NIPRIORITY_OFF(x))
  76 #define IMX_AITC_NIVECSR         (VA_AITC_BASE + NIVECSR_OFF)
  77 #define IMX_AITC_FIVECSR         (VA_AITC_BASE + FIVECSR_OFF)
  78 #define IMX_AITC_INTSRCH         (VA_AITC_BASE + INTSRCH_OFF)
  79 #define IMX_AITC_INTSRCL         (VA_AITC_BASE + INTSRCL_OFF)
  80 #define IMX_AITC_INTFRCH         (VA_AITC_BASE + INTFRCH_OFF)
  81 #define IMX_AITC_INTFRCL         (VA_AITC_BASE + INTFRCL_OFF)
  82 #define IMX_AITC_NIPNDH          (VA_AITC_BASE + NIPNDH_OFF)
  83 #define IMX_AITC_NIPNDL          (VA_AITC_BASE + NIPNDL_OFF)
  84 #define IMX_AITC_FIPNDH          (VA_AITC_BASE + FIPNDH_OFF)
  85 #define IMX_AITC_FIPNDL          (VA_AITC_BASE + FIPNDL_OFF)
  86
  87 #if 0
  88 #define DEBUG_IRQ(fmt...)       printk(fmt)
  89 #else
  90 #define DEBUG_IRQ(fmt...)       do { } while (0)
  91 #endif
  92
  93 static void
  94 imx_mask_irq(unsigned int irq)
  95 {
  96         __raw_writel(irq, IMX_AITC_INTDISNUM);
  97 }
  98
  99 static void
 100 imx_unmask_irq(unsigned int irq)
 101 {
 102         __raw_writel(irq, IMX_AITC_INTENNUM);
 103 }
 104
 105 static int
 106 imx_gpio_irq_type(unsigned int _irq, unsigned int type)
 107 {
 108         unsigned int irq_type = 0, irq, reg, bit;
 109
 110         irq = _irq - IRQ_GPIOA(0);
 111         reg = irq >> 5;
 112         bit = 1 << (irq % 32);
 113
 114         if (type == IRQT_PROBE) {
 115                 /* Don't mess with enabled GPIOs using preconfigured edges or
 116                    GPIOs set to alternate function during probe */
 117                 /* TODO: support probe */
 118 //              if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
 119 //                  GPIO_bit(gpio))
 120 //                      return 0;
 121 //              if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
 122 //                      return 0;
 123 //              type = __IRQT_RISEDGE | __IRQT_FALEDGE;
 124         }
 125
 126         GIUS(reg) |= bit;
 127         DDIR(reg) &= ~(bit);
 128
 129         DEBUG_IRQ("setting type of irq %d to ", _irq);
 130
 131         if (type & __IRQT_RISEDGE) {
 132                 DEBUG_IRQ("rising edges\n");
 133                 irq_type = 0x0;
 134         }
 135         if (type & __IRQT_FALEDGE) {
 136                 DEBUG_IRQ("falling edges\n");
 137                 irq_type = 0x1;
 138         }
 139         if (type & __IRQT_LOWLVL) {
 140                 DEBUG_IRQ("low level\n");
 141                 irq_type = 0x3;
 142         }
 143         if (type & __IRQT_HIGHLVL) {
 144                 DEBUG_IRQ("high level\n");
 145                 irq_type = 0x2;
 146         }
 147
 148         if (irq % 32 < 16) {
 149                 ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) |
 150                     (irq_type << ((irq % 16) * 2));
 151         } else {
 152                 ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) |
 153                     (irq_type << ((irq % 16) * 2));
 154         }
 155
 156         return 0;
 157
 158 }
 159
 160 static void
 161 imx_gpio_ack_irq(unsigned int irq)
 162 {
 163         DEBUG_IRQ("%s: irq %d\n", __func__, irq);
 164         ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
 165 }
 166
 167 static void
 168 imx_gpio_mask_irq(unsigned int irq)
 169 {
 170         DEBUG_IRQ("%s: irq %d\n", __func__, irq);
 171         IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
 172 }
 173
 174 static void
 175 imx_gpio_unmask_irq(unsigned int irq)
 176 {
 177         DEBUG_IRQ("%s: irq %d\n", __func__, irq);
 178         IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
 179 }
 180
 181 static void
 182 imx_gpio_handler(unsigned int mask, unsigned int irq,
 183                  struct irq_desc *desc)
 184 {
 185         desc = irq_desc + irq;
 186         while (mask) {
 187                 if (mask & 1) {
 188                         DEBUG_IRQ("handling irq %d\n", irq);
 189                         desc_handle_irq(irq, desc);
 190                 }
 191                 irq++;
 192                 desc++;
 193                 mask >>= 1;
 194         }
 195 }
 196
 197 static void
 198 imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 199 {
 200         unsigned int mask, irq;
 201
 202         mask = ISR(0);
 203         irq = IRQ_GPIOA(0);
 204         imx_gpio_handler(mask, irq, desc);
 205 }
 206
 207 static void
 208 imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 209 {
 210         unsigned int mask, irq;
 211
 212         mask = ISR(1);
 213         irq = IRQ_GPIOB(0);
 214         imx_gpio_handler(mask, irq, desc);
 215 }
 216
 217 static void
 218 imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 219 {
 220         unsigned int mask, irq;
 221
 222         mask = ISR(2);
 223         irq = IRQ_GPIOC(0);
 224         imx_gpio_handler(mask, irq, desc);
 225 }
 226
 227 static void
 228 imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 229 {
 230         unsigned int mask, irq;
 231
 232         mask = ISR(3);
 233         irq = IRQ_GPIOD(0);
 234         imx_gpio_handler(mask, irq, desc);
 235 }
 236
 237 static struct irq_chip imx_internal_chip = {
 238         .name = "MPU",
 239         .ack = imx_mask_irq,
 240         .mask = imx_mask_irq,
 241         .unmask = imx_unmask_irq,
 242 };
 243
 244 static struct irq_chip imx_gpio_chip = {
 245         .name = "GPIO",
 246         .ack = imx_gpio_ack_irq,
 247         .mask = imx_gpio_mask_irq,
 248         .unmask = imx_gpio_unmask_irq,
 249         .set_type = imx_gpio_irq_type,
 250 };
 251
 252 void __init
 253 imx_init_irq(void)
 254 {
 255         unsigned int irq;
 256
 257         DEBUG_IRQ("Initializing imx interrupts\n");
 258
 259         /* Disable all interrupts initially. */
 260         /* Do not rely on the bootloader. */
 261         __raw_writel(0, IMX_AITC_INTENABLEH);
 262         __raw_writel(0, IMX_AITC_INTENABLEL);
 263
 264         /* Mask all GPIO interrupts as well */
 265         IMR(0) = 0;
 266         IMR(1) = 0;
 267         IMR(2) = 0;
 268         IMR(3) = 0;
 269
 270         for (irq = 0; irq < IMX_IRQS; irq++) {
 271                 set_irq_chip(irq, &imx_internal_chip);
 272                 set_irq_handler(irq, handle_level_irq);
 273                 set_irq_flags(irq, IRQF_VALID);
 274         }
 275
 276         for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
 277                 set_irq_chip(irq, &imx_gpio_chip);
 278                 set_irq_handler(irq, handle_edge_irq);
 279                 set_irq_flags(irq, IRQF_VALID);
 280         }
 281
 282         set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
 283         set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
 284         set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
 285         set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);
 286
 287         /* Release masking of interrupts according to priority */
 288         __raw_writel(-1, IMX_AITC_NIMASK);
 289 }