omnivision.c

   1 /**
   2  * @file omnivision.c
   3  * @date 2008-10-27
   4  *
   5  * @brief Common control functions for Omnivision Image Sensors.
   6  *
   7  * @par Licences
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22  */
  23
  24 #include "sn9c20x.h"
  25 #include "sn9c20x-bridge.h"
  26 #include "omnivision.h"
  27
  28 struct sn9c20x_i2c_regs ov7660_init[] = {
  29         /* System CLK selection, to get a higher Frame Rate */
  30         {OV7660_CTL_COM5, 0x80},
  31         /* OV7660 Wakeup */
  32         /* COM4 is Reserved : using default value 0x40 OR windows driver value 0x08 */
  33         {OV7660_CTL_COM4, 0x08},
  34         /* Enable HREF at optical black, Use optical black line as BLC signal
  35             Reset all timing when format changes, Enable ADBLC option */
  36         {OV7660_CTL_COM6, 0xc3},
  37         /* windows 0x00, default 0x00, trying 0x60 to enable CCIR656 format */
  38         {OV7660_CTL_COM1, 0xc3},
  39         /* default is 0x40, windows sets it to 0x00 */
  40         {OV7660_CTL_AECH, 0x40},
  41         /* default is 0x00, windows sets it to 0x40 */
  42         {OV7660_CTL_CLKRC, 0x40},
  43         /* Set O/P format - RGB Selection, Set O/P format Raw RGB */
  44         {OV7660_CTL_COM7, 0x05},
  45         /* default is 0x8f, windows used 0xf8 */
  46         /* Enable fast AGC/AEC algorithm, AEC - Step size limit = 1/16 x AEC */
  47         /* Banding & Reserved are disabled. AGC, AEC enabled, 0x85 */
  48         {OV7660_CTL_COM8, 0xba},
  49         /* video appears jagged w/o these  ADC writes */
  50         {OV7660_CTL_ADC, 0x0f},
  51         {OV7660_CTL_ACOM, 0x02},
  52         {OV7660_CTL_OFON, 0x43},
  53         /* video appears jagged w/o this write */
  54         /* Default 0x0c sets format to uYvY, Windows driver 0x00 sets format to YuYv */
  55         {OV7660_CTL_TSLB, 0x00},
  56         /* Not doing this write makes the video look green */
  57         /* Manual Banding Filter MSB , set B & R channel pre-gain */
  58         {OV7660_CTL_HV, 0x90},
  59         /*  No video stream w/o these ADVFL/ADVFH write totally black */
  60         {OV7660_CTL_ADVFL, 0xf6},
  61         {OV7660_CTL_ADVFH, 0x0b},
  62         /* Setting BLUE to 0x78; RED to 0x78 to get natural colors in artificial light */
  63         {OV7660_CTL_BLUE, 0x78},
  64         /* Setting RED to 0x50 to get natural colors in natural light */
  65         {OV7660_CTL_RED,  0x50},
  66         {0xff, 0xff},
  67 };
  68
  69 struct sn9c20x_i2c_regs ov7670_init[] = {
  70         /* Phase 1 */
  71         {OV7670_CTL_COM7, 0x80},
  72         {OV7670_CTL_CLKRC, 0x80},
  73         {OV7670_CTL_TSLB, 0x04},
  74         {OV7670_CTL_COM7, 0x00},
  75         {OV7670_CTL_HREF, 0xb6},
  76         {OV7670_CTL_VREF, 0x0a},
  77         {OV7670_CTL_COM3, 0x00},
  78         {OV7670_CTL_COM14, 0x00},
  79         {OV7670_CTL_SCALING_XSC, 0x3a},
  80         {OV7670_CTL_SCALING_YSC, 0x35},
  81         {OV7670_CTL_SCALING_DCWCTR, 0x11},
  82         {OV7670_CTL_SCALING_PCLK_DIV, 0xf0},
  83         {OV7670_CTL_SCALING_PCLK_DELAY, 0x02},
  84         {OV7670_CTL_COM8, 0xe0},
  85         {OV7670_CTL_GAIN, 0x00},
  86         {OV7670_CTL_AECH, 0x00},
  87         {OV7670_CTL_COM4, 0x40},
  88         {OV7670_CTL_COM9, 0x08},
  89         {OV7670_CTL_BD50MAX, 0x05},
  90         {OV7670_CTL_BD60MAX, 0x07},
  91         {OV7670_CTL_AEW, 0x95},
  92         {OV7670_CTL_AEB, 0x33},
  93         {OV7670_CTL_VPT, 0xe3},
  94         {OV7670_CTL_HAECC1, 0x75},
  95         {OV7670_CTL_HAECC2, 0x65},
  96         {0xa1, 0x0b},
  97         {OV7670_CTL_HAECC3, 0xd8},
  98         {OV7670_CTL_HAECC4, 0xd8},
  99         {OV7670_CTL_HAECC5, 0xf0},
 100         {OV7670_CTL_HAECC6, 0x90},
 101         {OV7670_CTL_HAECC7, 0x94},
 102         {OV7670_CTL_COM8, 0xe5},
 103         {OV7670_CTL_COM5, 0x61},
 104         {OV7670_CTL_COM6, 0x4b},
 105         {0x16, 0x02},
 106         {OV7670_CTL_MVFP, 0x27},
 107         {OV7670_CTL_ADCCTR1, 0x02},
 108         {OV7670_CTL_ADCCTR2, 0x91},
 109         {0x29, 0x07},
 110         {OV7670_CTL_CHLF, 0x0b},
 111         {0x35, 0x0b},
 112         {OV7670_CTL_ADC, 0x1d},
 113         {OV7670_CTL_ACOM, 0x71},
 114         {OV7670_CTL_OFON, 0x2a},
 115         {OV7670_CTL_COM12, 0x78},
 116         {0x4d, 0x40},
 117         {0x4e, 0x20},
 118         {OV7670_CTL_GFIX, 0x00},
 119         {OV7670_CTL_REG74, 0x19},
 120         {0x8d, 0x4f},
 121         {0x8e, 0x00},
 122         {0x8f, 0x00},
 123         {0x90, 0x00},
 124         {0x91, 0x00},
 125         {0x96, 0x00},
 126         {0x9a, 0x80},
 127         {0xb0, 0x84},
 128         {OV7670_CTL_ABLC1, 0x0c},
 129         {0xb2, 0x0e},
 130         {OV7670_CTL_THL_ST, 0x82},
 131         {0xb8, 0x0a},
 132         {OV7670_CTL_AWBC1, 0x0a},
 133         {OV7670_CTL_AWBC2, 0xf0},
 134         {OV7670_CTL_AWBC3, 0x20},
 135         {OV7670_CTL_AWBC4, 0x7d},
 136         {OV7670_CTL_AWBC5, 0x29},
 137         {OV7670_CTL_AWBC6, 0x4a},
 138         {0x59, 0x8c},
 139         {0x5a, 0xa5},
 140         {0x5b, 0xde},
 141         {0x5c, 0x96},
 142         {0x5d, 0x66},
 143         {0x5e, 0x10},
 144         {OV7670_CTL_AWBCTR3, 0x0a},
 145         {OV7670_CTL_AWBCTR2, 0x55},
 146         {OV7670_CTL_AWBCTR1, 0x11},
 147         {OV7670_CTL_AWBCTR0, 0x9e},
 148         {OV7670_CTL_GGAIN, 0x40},
 149         {OV7670_CTL_BLUE, 0x40},
 150         {OV7670_CTL_RED, 0x40},
 151         {OV7670_CTL_COM8, 0xe7},
 152         {OV7670_CTL_MTX1, 0x6e},
 153         {OV7670_CTL_MTX2, 0x70},
 154         {OV7670_CTL_MTX3, 0x02},
 155         {OV7670_CTL_MTX4, 0x1d},
 156         {OV7670_CTL_MTX5, 0x56},
 157         {OV7670_CTL_MTX6, 0x73},
 158         {OV7670_CTL_BRIGHT, 0x0a},
 159         {OV7670_CTL_CONTRAS, 0x55},
 160         {OV7670_CTL_CONTRAS_CENTER, 0x80},
 161         {OV7670_CTL_MTXS, 0x9e},
 162         {OV7670_CTL_COM16, 0x08},
 163         {OV7670_CTL_EDGE, 0x02},
 164         {OV7670_CTL_REG75, 0x03},
 165         {OV7670_CTL_REG76, 0x63},
 166         {OV7670_CTL_DNSTH, 0x04},
 167         {OV7670_CTL_REG77, 0x06},
 168         {OV7670_CTL_COM13, 0xc2},
 169         {OV7670_CTL_REG4B, 0x09},
 170         {OV7670_CTL_SATCTR, 0x30},
 171         {OV7670_CTL_COM16, 0x08},
 172         {OV7670_CTL_CONTRAS, 0x48},
 173         {OV7670_CTL_ARBLM, 0x11},
 174         {OV7670_CTL_COM11, 0xc2},
 175         {OV7670_CTL_NT_CTRL, 0x88},
 176         {0x96, 0x00},
 177         {0x97, 0x30},
 178         {0x98, 0x20},
 179         {0x99, 0x30},
 180         {0x9a, 0x84},
 181         {0x9b, 0x29},
 182         {0x9c, 0x03},
 183         {OV7670_CTL_BD50ST, 0x99},
 184         {OV7670_CTL_BD60ST, 0x7f},
 185         {0x78, 0x04},
 186         {0x79, 0x01},
 187         {0xc8, 0xf0},
 188         {0x79, 0x0f},
 189         {0xc8, 0x00},
 190         {0x79, 0x10},
 191         {0xc8, 0x7e},
 192         {0x79, 0x0a},
 193         {0xc8, 0x80},
 194         {0x79, 0x0b},
 195         {0xc8, 0x01},
 196         {0x79, 0x0c},
 197         {0xc8, 0x0f},
 198         {0x79, 0x0d},
 199         {0xc8, 0x20},
 200         {0x79, 0x09},
 201         {0xc8, 0x80},
 202         {0x79, 0x02},
 203         {0xc8, 0xc0},
 204         {0x79, 0x03},
 205         {0xc8, 0x40},
 206         {0x79, 0x05},
 207         {0xc8, 0x30},
 208         {0x79, 0x26},
 209         {OV7670_CTL_LCC1, 0x20},
 210         {OV7670_CTL_LCC2, 0x00},
 211         {OV7670_CTL_LCC3, 0x06},
 212         {OV7670_CTL_LCC4, 0x00},
 213         {OV7670_CTL_LCC5, 0x05},
 214         {OV7670_CTL_LCC6, 0x05},
 215         {OV7670_CTL_LCC7, 0x0a},
 216         {OV7670_CTL_HSTART, 0x13},
 217         {OV7670_CTL_HSTOP, 0x01},
 218         {OV7670_CTL_VSTRT, 0x02},
 219         {OV7670_CTL_VSTOP, 0x7a},
 220         {OV7670_CTL_AWBC4, 0x59},
 221         {OV7670_CTL_AWBC5, 0x30},
 222         {OV7670_CTL_MTXS, 0x9a},
 223         {0x59, 0x84},
 224         {0x5a, 0x91},
 225         {0x5b, 0x57},
 226         {0x5c, 0x75},
 227         {0x5d, 0x6d},
 228         {0x5e, 0x13},
 229         {OV7670_CTL_LCC3, 0x07},
 230         {OV7670_CTL_LCC6, 0x07},
 231         {OV7670_CTL_LCC7, 0x0d},
 232         {OV7670_CTL_HAECC3, 0xdf},
 233         {OV7670_CTL_HAECC4, 0xdf},
 234         {OV7670_CTL_AWBC6, 0x4d},
 235         {OV7670_CTL_MTX3, 0x00},
 236         /* Phase 2 */
 237         {OV7670_CTL_DBLV, 0x0a},
 238         {OV7670_CTL_CLKRC, 0x80},
 239         {OV7670_CTL_EXHCH, 0x00},
 240         {OV7670_CTL_EXHCL, 0x00},
 241         {OV7670_CTL_DM_LNL, 0x00},
 242         {OV7670_CTL_DM_LNH, 0x00},
 243         {OV7670_CTL_COM11, 0xc2},
 244         {OV7670_CTL_BRIGHT, 0x0a},
 245         {OV7670_CTL_CONTRAS, 0x60},
 246         {OV7670_CTL_MTX1, 0x6e},
 247         {OV7670_CTL_MTX1 + 1, 0x70},
 248         {OV7670_CTL_MTX1 + 2, 0x00},
 249         {OV7670_CTL_MTX1 + 3, 0x1d},
 250         {OV7670_CTL_MTX5, 0x56},
 251         {OV7670_CTL_MTX5 + 1, 0x73},
 252         {OV7670_CTL_MTXS, 0x9a},
 253         {OV7670_CTL_MTX1, 0x6e},
 254         {OV7670_CTL_MTX1 + 1, 0x70},
 255         {OV7670_CTL_MTX1 + 2, 0x00},
 256         {OV7670_CTL_MTX1 + 3, 0x1d},
 257         {OV7670_CTL_MTX5, 0x56},
 258         {OV7670_CTL_MTX5 + 1, 0x73},
 259         {OV7670_CTL_MTXS, 0x9a},
 260         {OV7670_CTL_EDGE, 0x01},
 261         {OV7670_CTL_GAM1, 0x03},
 262         {OV7670_CTL_GAM1 + 1, 0x09},
 263         {OV7670_CTL_GAM1 + 2, 0x16},
 264         {OV7670_CTL_GAM1 + 3, 0x38},
 265         {OV7670_CTL_GAM5, 0x47},
 266         {OV7670_CTL_GAM5 + 1, 0x53},
 267         {OV7670_CTL_GAM5 + 2, 0x5e},
 268         {OV7670_CTL_GAM5 + 3, 0x6a},
 269         {OV7670_CTL_GAM9, 0x74},
 270         {OV7670_CTL_GAM9 + 1, 0x80},
 271         {OV7670_CTL_GAM9 + 2, 0x8c},
 272         {OV7670_CTL_GAM9 + 3, 0x9b},
 273         {OV7670_CTL_GAM13, 0xb2},
 274         {OV7670_CTL_GAM13 + 1, 0xcc},
 275         {OV7670_CTL_GAM13 + 2, 0xe5},
 276         {OV7670_CTL_SLOP, 0x24},
 277         {OV7670_CTL_COM11, 0xc0},
 278         {OV7670_CTL_COM11, 0xc0},
 279         {OV7670_CTL_HAECC1, 0x76},
 280         {OV7670_CTL_HAECC1 + 1, 0x65},
 281         {OV7670_CTL_COM8, 0xe2},
 282         /* Phase 3 */
 283         {OV7670_CTL_DBLV, 0x0a},
 284         {OV7670_CTL_CLKRC, 0x80},
 285         {OV7670_CTL_EXHCH, 0x00},
 286         {OV7670_CTL_EXHCL, 0x00},
 287         {OV7670_CTL_DM_LNL, 0x00},
 288         {OV7670_CTL_DM_LNH, 0x00},
 289         {0xff, 0xff},
 290 };
 291
 292 /**
 293  * @var ov9650_init
 294  * @brief Addresses and values for the initialization of ov965x sensors
 295  *
 296  */
 297 struct sn9c20x_i2c_regs ov9650_init[] = {
 298         {OV965X_CTL_COM7, OV965X_COM7_SCCB_RESET},
 299         {OV965X_CTL_GAIN, 0x00},
 300         {OV965X_CTL_BLUE, 0x78},
 301         {OV965X_CTL_RED, 0x78},
 302         {OV965X_CTL_VREF, OV965X_VREF_VSTOP_LOW3(0x06) |
 303                           OV965X_VREF_VSTART_LOW3(0x06)},
 304         {OV965X_CTL_COM1, 0x03},
 305         {OV965X_CTL_BAVE, 0x00}, /* default */
 306         {OV965X_CTL_GEAVE, 0x00}, /* default */
 307         {OV965X_CTL_RAVE, 0x00}, /* default */
 308         {OV965X_CTL_COM2, OV965X_COM2_OUTPUT_DRIVE_CAP_2X},
 309         {OV965X_CTL_COM3, 0x00},
 310         {OV965X_CTL_COM4, 0x00},
 311         {OV965X_CTL_COM5, OV965X_COM5_15FPS_48MHZ_RGB | 0x20},
 312         {OV965X_CTL_COM6, OV965X_COM6_TIMING_RESET_ON_FMT_CHANGE | 0x50},
 313         {OV965X_CTL_AECH, 0x7c},
 314         {OV965X_CTL_CLKRC, OV965X_CLKRC_DBL_CLK_ENABLE},
 315         {OV965X_CTL_COM7, OV965X_COM7_OUTPUT_VGA | OV965X_COM7_OUTPUT_RAW_RGB},
 316         {OV965X_CTL_COM8, OV965X_COM8_FAST_AGC_AEC |
 317                           OV965X_COM8_AEC_STEP_SIZE_NOLIMIT |
 318                           OV965X_COM8_AWB_ENABLE},
 319         {OV965X_CTL_COM9, OV965X_COM9_MAX_AGC_4X |
 320                           OV965X_COM9_RELAX_EXPOSURE_TIMING |
 321                           OV965X_COM9_DROP_VSYNC_ON_FRAME_DROP |
 322                           OV965X_COM9_DROP_FRAME_ON_BIG_AEC},
 323         {OV965X_CTL_COM10, 0x00},
 324         {0x16, 0x07}, /* reserved */
 325         {OV965X_CTL_HSTART, 0x24},
 326         {OV965X_CTL_HSTOP, 0xc5},
 327         {OV965X_CTL_VSTRT, 0x00},
 328         {OV965X_CTL_VSTOP, 0x3c},
 329         {OV965X_CTL_PSHIFT, 0x00}, /* default */
 330         {OV965X_CTL_MVFP, 0x04},
 331         {OV965X_CTL_LAEC, 0x00}, /* reserved */
 332         {OV965X_CTL_AEW, 0x78}, /* default */
 333         {OV965X_CTL_AEB, 0x68}, /* default */
 334         {OV965X_CTL_VPT, 0xd4}, /* default */
 335         {OV965X_CTL_BBIAS, OV965X_BIAS_SUBTRACT}, /* default */
 336         {OV965X_CTL_GbBIAS, OV965X_BIAS_SUBTRACT}, /* default */
 337         {OV965X_CTL_Gr_COM, OV965X_Gr_COM_BYPASS_ANALOG_BLC |
 338                             OV965X_Gr_COM_BYPASS_REGULATOR},
 339         {OV965X_CTL_EXHCH, 0x00}, /* default */
 340         {OV965X_CTL_EXHCL, 0x00}, /* default */
 341         {OV965X_CTL_RBIAS, OV965X_BIAS_SUBTRACT}, /* default */
 342         {OV965X_CTL_ADVFL, 0x00}, /* default */
 343         {OV965X_CTL_ADVFH, 0x00}, /* default */
 344         {OV965X_CTL_YAVE, 0x00}, /* default */
 345         {OV965X_CTL_HSYST, 0x08}, /* default */
 346         {OV965X_CTL_HSYEN, 0x30}, /* default */
 347         {OV965X_CTL_HREF, OV965X_HREF_EDGE_OFT_TO_DATA_OUT(2) |
 348                           OV965X_HREF_HSTOP_LOW3(0) |
 349                           OV965X_HREF_HSTART_LOW3(4)},
 350         {OV965X_CTL_CHLF, 0xe2}, /* reserved */
 351         {OV965X_CTL_ARBLM, 0xbf}, /* reserved */
 352         {0x35, 0x81}, /* reserved */
 353         {0x36, 0xf9}, /* reserved */
 354         {OV965X_CTL_ADC, 0x00}, /* reserved */
 355         {OV965X_CTL_ACOM, 0x93}, /* reserved */
 356         {OV965X_CTL_OFON, 0x50},
 357         {OV965X_CTL_TSLB, OV965X_TSLB_DIGITAL_BLC_ENABLE},
 358         {OV965X_CTL_COM11, OV965X_COM11_MANUAL_BANDING_FILTER},
 359         {OV965X_CTL_COM12, 0x73},
 360         {OV965X_CTL_COM13, OV965X_COM13_ENABLE_COLOR_MATRIX |
 361                            OV965X_COM13_DELAY_Y_CHANNEL |
 362                            OV965X_COM13_OUTPUT_DELAY(1)},
 363         {OV965X_CTL_COM14, OV965X_COM14_YUV_EDGE_ENHANCE |
 364                            OV965X_COM14_EDGE_ENHANCE_FACTOR_DBL | 0x0b},
 365         {OV965X_CTL_EDGE, OV965X_EDGE_EDGE_ENHANCE_LOW4(8) |
 366                           OV965X_EDGE_EDGE_ENHANCE_FACTOR(8)},
 367         {OV965X_CTL_COM15, OV965X_COM15_OUTPUT_RANGE_O0_TO_FF | 0x01},
 368         {OV965X_CTL_COM16, 0x00},
 369         {OV965X_CTL_COM17, 0x08},
 370         {OV965X_CTL_MANU, 0x80}, /* default */
 371         {OV965X_CTL_MANV, 0x80}, /* default */
 372         {OV965X_CTL_HV, 0x40},
 373         {OV965X_CTL_MBD, 0x00}, /* default */
 374         {OV965X_CTL_DBLV, 0x0a}, /* reserved */
 375         {OV965X_CTL_COM21, 0x06}, /* reserved */
 376         {OV965X_CTL_COM22, 0x20},
 377         {OV965X_CTL_COM23, 0x00}, /* default */
 378         {OV965X_CTL_COM24, 0x00}, /* reserved */
 379         {OV965X_CTL_DBLC1, 0xdf},
 380         {OV965X_CTL_DM_LNL, 0x00}, /* default */
 381         {OV965X_CTL_DM_LNH, 0x00}, /* default */
 382         {0x94, 0x88}, /* reserved */
 383         {0x95, 0x88}, /* reserved */
 384         {0x96, 0x04}, /* reserved */
 385         {OV965X_CTL_AECHM, 0x00},
 386         {OV965X_CTL_COM26, 0x80}, /* reserved */
 387         {0xa8, 0x80}, /* reserved */
 388         {0xa9, 0xb8}, /* reserved */
 389         {0xaa, 0x92}, /* reserved */
 390         {0xab, 0x0a}, /* reserved */
 391         {0xff, 0xff},
 392 };
 393
 394 /**
 395  * @var soi968_init
 396  * @brief Addresses and values for the initialization of SOI968 sensors
 397  * @author GWater
 398  *
 399  */
 400 struct sn9c20x_i2c_regs soi968_init[] = {
 401         /* reset all registers */
 402         {0x12, 0x80},
 403         /* stop resetting */
 404         {0x12, 0x00},
 405         /* snapshot mode: off */
 406         {0x0c, 0x00},
 407         /* enable offset adjustment,
 408          * full data range,
 409          * analogue2digital control black-level calibration
 410          */
 411         {0x0f, 0x1f},
 412         /* Clock: internal PLL on */
 413         {0x11, 0x80},
 414         /* Analoge Black-level calibration off , no anaolgue gain */
 415         {0x38, 0x52},
 416         /* reserved */
 417         {0x1e, 0x00},
 418         /* special system settings (voltage, analogue2digital, ...) */
 419         {0x33, 0x08},
 420         {0x35, 0x8c},
 421         {0x36, 0x0c},
 422         {0x37, 0x04},
 423         /*  next 7 are unknown/reserved */
 424         {0x45, 0x04},
 425         {0x47, 0xff},
 426         {0x3e, 0x00},
 427         {0x3f, 0x00},
 428         {0x3b, 0x20},
 429         {0x3a, 0x96},
 430         {0x3d, 0x0a},
 431         /* disable banding filter in dark environment,
 432          * VSYNC is dropped when framerate is dropped,
 433          * drop frmaes when exposure out of tolerance,
 434          * unfreeze exposure and gain values
 435          */
 436         {0x14, 0x4e},
 437         /* AEC, AGC, AWB disabled; fast AEC */
 438         {0x13, 0x8a},
 439         /* output: VGA, master mode */
 440         {0x12, 0x40},
 441         /* set HSTART, HSTOP, VSTART and VSTOP */
 442         {0x17, 0x13},
 443         {0x18, 0x63},
 444         {0x19, 0x01},
 445         {0x1a, 0x79},
 446         {0x32, 0x24}, /* LSB for all four */
 447         /* AWB update threshold,
 448          * blue and red gain LSB
 449          */
 450         {0x03, 0x00},
 451         /* CLock: internal PLL off */
 452         {0x11, 0x40},
 453         /* Line interval adjustment */
 454         {0x2a, 0x10},
 455         {0x2b, 0xe0},
 456         /* AEC MSB */
 457         {0x10, 0x32},
 458         /* gain - default*/
 459         {0x00, 0x00},
 460         /* blue and red gain - default*/
 461         {0x01, 0x80},
 462         {0x02, 0x80},
 463         {0xff, 0xff},
 464 };
 465
 466 struct sn9c20x_i2c_regs ov9655_init[] = {
 467         {0x12, 0x80}, {0x12, 0x01}, {0x0d, 0x00}, {0x0e, 0x61},
 468         {0x11, 0x80}, {0x13, 0xba}, {0x14, 0x3e}, {0x16, 0x24},
 469         {0x1e, 0x04}, {0x1e, 0x04}, {0x1e, 0x04}, {0x27, 0x08},
 470         {0x28, 0x08}, {0x29, 0x15}, {0x2c, 0x08}, {0x32, 0xbf},
 471         {0x34, 0x3d}, {0x35, 0x00}, {0x36, 0xf8}, {0x38, 0x12},
 472         {0x39, 0x57}, {0x3a, 0x00}, {0x3b, 0xcc}, {0x3c, 0x0c},
 473         {0x3d, 0x19}, {0x3e, 0x0c}, {0x3f, 0x01}, {0x41, 0x40},
 474         {0x42, 0x80}, {0x45, 0x46}, {0x46, 0x62}, {0x47, 0x2a},
 475         {0x48, 0x3c}, {0x4a, 0xf0}, {0x4b, 0xdc}, {0x4c, 0xdc},
 476         {0x4d, 0xdc}, {0x4e, 0xdc}, {0x69, 0x02}, {0x6c, 0x04},
 477         {0x6f, 0x9e}, {0x70, 0x05}, {0x71, 0x78}, {0x77, 0x02},
 478         {0x8a, 0x23}, {0x8c, 0x0d}, {0x90, 0x7e}, {0x91, 0x7c},
 479         {0x9f, 0x6e}, {0xa0, 0x6e}, {0xa5, 0x68}, {0xa6, 0x60},
 480         {0xa8, 0xc1}, {0xa9, 0xfa}, {0xaa, 0x92}, {0xab, 0x04},
 481         {0xac, 0x80}, {0xad, 0x80}, {0xae, 0x80}, {0xaf, 0x80},
 482         {0xb2, 0xf2}, {0xb3, 0x20}, {0xb5, 0x00}, {0xb6, 0xaf},
 483         {0xbb, 0xae}, {0xbc, 0x44}, {0xbd, 0x44}, {0xbe, 0x3b},
 484         {0xbf, 0x3a}, {0xc0, 0xe2}, {0xc1, 0xc8}, {0xc2, 0x01},
 485         {0xc4, 0x00}, {0xc6, 0x85}, {0xc7, 0x81}, {0xc9, 0xe0},
 486         {0xca, 0xe8}, {0xcc, 0xd8}, {0xcd, 0x93}, {0x12, 0x61},
 487         {0x36, 0xfa}, {0x8c, 0x8d}, {0xc0, 0xaa}, {0x69, 0x0a},
 488         {0x03, 0x12}, {0x17, 0x14}, {0x18, 0x00}, {0x19, 0x01},
 489         {0x1a, 0x3d}, {0x32, 0xbf}, {0x11, 0x80}, {0x2a, 0x10},
 490         {0x2b, 0x0a}, {0x92, 0x00}, {0x93, 0x00}, {0x1e, 0x04},
 491         {0x1e, 0x04}, {0x10, 0x7c}, {0x04, 0x03}, {0xa1, 0x00},
 492         {0x2d, 0x00}, {0x2e, 0x00}, {0x00, 0x00}, {0x01, 0x80},
 493         {0x02, 0x80}, {0x12, 0x61}, {0x36, 0xfa}, {0x8c, 0x8d},
 494         {0xc0, 0xaa}, {0x69, 0x0a}, {0x03, 0x12}, {0x17, 0x14},
 495         {0x18, 0x00}, {0x19, 0x01}, {0x1a, 0x3d}, {0x32, 0xbf},
 496         {0x11, 0x80}, {0x2a, 0x10}, {0x2b, 0x0a}, {0x92, 0x00},
 497         {0x93, 0x00}, {0x04, 0x01}, {0x10, 0x1f}, {0xa1, 0x00},
 498         {0x00, 0x0a}, {0xa1, 0x00}, {0x10, 0x5d}, {0x04, 0x03},
 499         {0x00, 0x01}, {0xa1, 0x00}, {0x10, 0x7c}, {0x04, 0x03},
 500         {0x00, 0x03}, {0x00, 0x0a}, {0x00, 0x10}, {0x00, 0x13},
 501         {0xff, 0xff},
 502 };
 503
 504 /**
 505  * @brief OV7670 Auto-Flip
 506  *
 507  * @param dev Pointer to the device
 508  * @param vflip Flag to indicate whether or not Camera is currently flipped
 509  *
 510  * @return Zero (success) or negative (USB-error value)
 511  *
 512  */
 513 int ov7670_auto_flip(struct usb_sn9c20x *dev, __u8 vflip)
 514 {
 515         int ret;
 516         __u8 buf[2];
 517
 518         ret = sn9c20x_read_i2c_data(dev, 1,
 519                         OV7670_CTL_MVFP, buf);
 520         if (ret < 0)
 521                 return ret;
 522
 523         if (vflip == 0)
 524                 buf[0] = buf[0] & (0xff ^ OV7670_VFLIP_BIT);
 525         else
 526                 buf[0] = buf[0] | OV7670_VFLIP_BIT;
 527         ret = sn9c20x_write_i2c_data(dev, 1,
 528                         OV7670_CTL_MVFP, buf);
 529
 530         return ret;
 531 }
 532
 533 /**
 534  * @brief Set hflip and vflip in ov965x sensors
 535  *
 536  * @param dev Pointer to device structure
 537  *
 538  * @returns 0 or negative error code
 539  *
 540  */
 541 int ov965x_set_hvflip(struct usb_sn9c20x *dev)
 542 {
 543         int ret;
 544         __u8 value;
 545         __u8 tslb;
 546         ret = sn9c20x_read_i2c_data(dev, 1, OV965X_CTL_MVFP, &value);
 547         if (ret < 0)
 548                 return ret;
 549
 550         if (dev->vsettings.hflip)
 551                 value |= OV965X_MVFP_MIRROR;
 552         else
 553                 value &= ~OV965X_MVFP_MIRROR;
 554
 555         if (dev->vsettings.vflip) {
 556                 value |= OV965X_MVFP_VFLIP;
 557                 tslb = 0x49;
 558         } else {
 559                 value &= ~OV965X_MVFP_VFLIP;
 560                 tslb = 0x01;
 561         }
 562
 563         ret = sn9c20x_write_i2c_data(dev, 1, OV965X_CTL_MVFP, &value);
 564         ret = sn9c20x_write_i2c_data(dev, 1, OV965X_CTL_TSLB, &tslb);
 565
 566         return ret;
 567 }
 568
 569 /**
 570  * @brief Set exposure for omnivision sensors
 571  *
 572  * @param dev
 573  *
 574  * @returns 0 or negative error value
 575  *
 576  * The used registers do not show up the datasheets.
 577  *
 578  */
 579 int ov_set_exposure(struct usb_sn9c20x *dev)
 580 {
 581         int ret = 0;
 582         __u8 val[2] = {(dev->vsettings.exposure & 0x0F) << 4,
 583                 dev->vsettings.exposure >> 4};
 584
 585         ret = sn9c20x_write_i2c_data_ext(dev, 2, 0x2d, val, 0x1e);
 586
 587         return ret;
 588 }
 589
 590 /**
 591  * @brief Set autoexposure for omnivision sensors
 592  *
 593  * @param dev
 594  *
 595  * @returns 0 or negative error value
 596  *
 597  * @author GWater
 598  *
 599  * For SOI968 sensor.
 600  */
 601 int soi968_set_autoexposure(struct usb_sn9c20x *dev)
 602 {
 603         __u8 buf[1];
 604         int ret = 0;
 605
 606         ret = sn9c20x_read_i2c_data(dev, 1, 0x13, buf);
 607         if (ret < 0)
 608                 return ret;
 609
 610         switch (dev->vsettings.auto_exposure) {
 611         case V4L2_EXPOSURE_AUTO:
 612                 buf[0] |= 0x01;
 613         break;
 614         case V4L2_EXPOSURE_MANUAL:
 615                 buf[0] &= ~0x01;
 616         break;
 617         case V4L2_EXPOSURE_SHUTTER_PRIORITY:
 618                 buf[0] &= ~0x01;
 619         break;
 620         case V4L2_EXPOSURE_APERTURE_PRIORITY:
 621                 buf[0] |= 0x01;
 622         break;
 623         default:
 624                 return -EINVAL;
 625         }
 626
 627         ret = sn9c20x_write_i2c_data(dev, 1, 0x13, buf);
 628
 629         return ret;
 630 }
 631
 632 /**
 633  * @brief Set autogain for omnivision sensors
 634  *
 635  * @param dev
 636  *
 637  * @returns 0 or negative error value
 638  *
 639  * @author GWater
 640  *
 641  * For all Omnivision sensors and SOI968.
 642  */
 643 int ov_set_autogain(struct usb_sn9c20x *dev)
 644 {
 645         __u8 buf[1];
 646         int ret = 0;
 647
 648         ret = sn9c20x_read_i2c_data(dev, 1, 0x13, buf);
 649         if (ret < 0)
 650                 return ret;
 651
 652         if (dev->vsettings.auto_gain == 1)
 653                 buf[0] |= 0x04;
 654         else if (dev->vsettings.auto_gain == 0)
 655                 buf[0] &= ~0x04;
 656         else
 657                 return -EINVAL;
 658
 659         ret = sn9c20x_write_i2c_data(dev, 1, 0x13, buf);
 660
 661         return ret;
 662 }
 663
 664 /**
 665  * @brief Set exposure for SOI968 sensors
 666  *
 667  * @param dev
 668  *
 669  * @returns 0 or negative error value
 670  *
 671  * @author GWater
 672  *
 673  * For SOI968 sensors.
 674  */
 675 int soi968_set_exposure(struct usb_sn9c20x *dev)
 676 {
 677         int value, ret;
 678         int exposure = dev->vsettings.exposure;
 679         __u8 buf1, buf2, buf3;
 680
 681         /* Read current value of the I2C-register
 682          * containing exposure LSB:
 683          */
 684         ret = sn9c20x_read_i2c_data(dev, 1, 0x04, &buf1);
 685         if (ret < 0) {
 686                 UDIA_ERROR("Error: setting exposure failed: "
 687                         "error while reading from I2C-register 0x04\n");
 688                 return ret;
 689         }
 690
 691         value = (exposure  * 0x08) & 0x7ff;
 692         buf2 = ((__u8) (value & 0x07)) | (buf1 & ~0x07);
 693         buf3 = (__u8) (value >> 3) & 0xff;
 694
 695         /* Write new value to I2C-register 0x04: */
 696         ret = sn9c20x_write_i2c_data(dev, 1, 0x04, &buf2);
 697         if (ret < 0) {
 698                 UDIA_ERROR("Error: setting exposure failed: "
 699                         "error while writing to I2C-register 0x04\n");
 700                 return ret;
 701         }
 702
 703         /* Write new value to I2C-register 0x10: */
 704         ret = sn9c20x_write_i2c_data(dev, 1, 0x10, &buf3);
 705         if (ret < 0) {
 706                 UDIA_ERROR("Error: setting exposure failed: "
 707                         "error while writing to I2C-register 0x10\n");
 708                 return ret;
 709         }
 710
 711         return 0;
 712 }
 713
 714 int soi968_set_gain(struct usb_sn9c20x *dev)
 715 {
 716         int ret;
 717         __u8 buf = dev->vsettings.gain & 0x3f;
 718
 719         ret = sn9c20x_write_i2c_data(dev, 1, 0x00, &buf);
 720
 721         return ret;
 722 }
 723
 724
 725 /**
 726  * @brief Detect whether the image for 6260 has to be flipped
 727  *
 728  * @param dev Pointer to device structure
 729  *
 730  * @returns 0 or negative error code
 731  *
 732  */
 733 int ov7670_flip_detect(struct usb_sn9c20x *dev)
 734 {
 735         const __u8 flip_bit = 0x01;
 736         int ret = 0;
 737         __u8 val;
 738         static __u8 flip_reg = flip_bit;
 739         __u8 vflip;
 740
 741         ret = usb_sn9c20x_control_read(dev, 0x1009, &val, 1);
 742         if (ret < 0)
 743                 return -EAGAIN;
 744         if (flip_reg != (val & flip_bit)) {
 745                 if (val & flip_bit)
 746                         vflip = 0;
 747                 else
 748                         vflip = 1;
 749                 ret = ov7670_auto_flip(dev, vflip);
 750                 flip_reg = (val & flip_bit);
 751         }
 752
 753         return ret;
 754 }
 755
 756 /**
 757  * @brief Detect whether the image for 624f has to be flipped
 758  *
 759  * @param dev Pointer to device structure
 760  *
 761  * @returns 0 or negative error code
 762  *
 763  */
 764 int ov965x_flip_detect(struct usb_sn9c20x *dev)
 765 {
 766         int ret = 0;
 767         __u8 val;
 768
 769         ret = usb_sn9c20x_control_read(dev, 0x1009, &val, 1);
 770         if (ret < 0)
 771                 return -EAGAIN;
 772         if (val & 0x01)
 773                 dev->vsettings.vflip = 1;
 774         else
 775                 dev->vsettings.vflip = 0;
 776         return ret;
 777 }
 778
 779 int soi968_button_detect(struct usb_sn9c20x *dev)
 780 {
 781         __u8 buf;
 782
 783         usb_sn9c20x_control_read(dev, 0x1005, &buf, 1);
 784
 785         if (buf & 0x10) {
 786                 /* button pushed */
 787                 if (dev->vsettings.auto_gain == 0)
 788                         dev->vsettings.auto_gain = 1;
 789                 else
 790                         dev->vsettings.auto_gain = 0;
 791                 ov_set_autogain(dev);
 792         }
 793
 794         return 0;
 795 }