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4 <TITLE>80386 Programmer's Reference Manual -- Section
14.5</TITLE>
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8 Chapter
14 --
80386 Real-Address Mode
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14 <H1>14.5 Switching Back to Real-Address Mode
</H1>
15 The processor reenters real-address mode if software clears the PE bit in
17 <A HREF=
"MOVRS.htm">MOV
</A> to CR0 instruction.
18 A procedure that attempts to do this,
19 however, should proceed as follows:
21 <LI> If paging is enabled, perform the following sequence:
23 <LI> Transfer control to linear addresses that have an identity mapping;
24 i.e., linear addresses equal physical addresses.
25 <LI> Clear the PG bit in CR0.
26 <LI> Move zeros to CR3 to clear out the paging cache.
28 <LI> Transfer control to a segment that has a limit of
64K (FFFFH). This
29 loads the CS register with the limit it needs to have in real mode.
30 <LI> Load segment registers SS, DS, ES, FS, and GS with a selector that
31 points to a descriptor containing the following values, which are
32 appropriate to real mode:
34 <LI> Limit =
64K (FFFFH)
35 <LI> Byte granular (G =
0)
36 <LI> Expand up (E =
0)
41 <LI> Disable interrupts. A
42 <A HREF=
"CLI.htm">CLI
</A> instruction disables INTR interrupts. NMIs
43 can be disabled with external circuitry.
44 <LI> Clear the PE bit.
45 <LI> Jump to the real mode code to be executed using a far
46 <A HREF=
"JMP.htm">JMP
</A>. This
47 action flushes the instruction queue and puts appropriate values in
48 the access rights of the CS register.
50 <A HREF=
"LGDT.htm">LIDT
</A>
51 instruction to load the base and limit of the real-mode
52 interrupt vector table.
53 <LI> Enable interrupts.
54 <LI> Load the segment registers as needed by the real-mode code.
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60 Chapter
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80386 Real-Address Mode
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61 <B>prev:
</B> <A HREF=
"s14_04.htm">14.4 Entering and Leaving Real-Address Mode
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62 <B>next:
</B> <A HREF=
"s14_06.htm">14.6 Real-Address Mode Exceptions
</A>