i386/i386.reference/s15_03.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 15.3</TITLE>
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   7 <B>up:</B> <A HREF="c15.htm">
   8 Chapter 15 -- Virtual 8086 Mode</A><BR>
   9 <B>prev:</B> <A HREF="s15_02.htm">15.2  Structure of a V86 Task</A><BR>
  10 <B>next:</B> <A HREF="s15_04.htm">15.4  Additional Sensitive Instructions</A>
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  13 <P>
  14 <H1>15.3  Entering and Leaving V86 Mode</H1>
  15
  16 <A HREF="#fig15-2">Figure 15-2</A>
  17   summarizes the ways that the processor can enter and leave an
  18 8086 program. The processor can enter V86 by either of two means:
  19 <OL>
  20 <LI> A task switch to an 80386 task loads the image of EFLAGS from the new
  21 TSS. The TSS of the new task must be an 80386 TSS, not an 80286 TSS,
  22 because the 80286 TSS does not store the high-order word of EFLAGS,
  23 which contains the VM flag. A value of one in the VM bit of the new
  24 EFLAGS indicates that the new task is executing 8086 instructions;
  25 therefore, while loading the segment registers from the TSS, the
  26 processor forms base addresses as the 8086 would.
  27 <LI> An <A HREF="IRET.htm">IRET</A> from a procedure of an 80386 task loads the image of EFLAGS
  28 from the stack. A value of one in VM in this case indicates that the
  29 procedure to which control is being returned is an 8086 procedure. The
  30 CPL at the time the <A HREF="IRET.htm">IRET</A> is executed must be zero, else the processor
  31 does not change VM.
  32 </OL>
  33 The processor leaves V86 mode when an interrupt or exception occurs. There
  34 are two cases:
  35 <OL>
  36 <LI> The interrupt or exception causes a task switch. A task switch from a
  37 V86 task to any other task loads EFLAGS from the TSS of the new task.
  38 If the new TSS is an 80386 TSS and the VM bit in the EFLAGS image is
  39 zero or if the new TSS is an 80286 TSS, then the processor clears the
  40 VM bit of EFLAGS, loads the segment registers from the new TSS using
  41 80386-style address formation, and begins executing the instructions
  42 of the new task according to 80386 protected-mode semantics.
  43 <LI> The interrupt or exception vectors to a privilege-level zero
  44 procedure. The processor stores the current setting of EFLAGS on the
  45 stack, then clears the VM bit. The interrupt or exception handler,
  46 therefore, executes as "native" 80386 protected-mode code. If an
  47 interrupt or exception vectors to a conforming segment or to a
  48 privilege level other than three, the processor causes a
  49 general-protection exception; the error code is the selector of the
  50 executable segment to which transfer was attempted.
  51 </OL>
  52 Systems software does not manipulate the VM flag directly, but rather
  53 manipulates the image of the EFLAGS register that is stored on the stack or
  54 in the TSS. The V86 monitor sets the VM flag in the EFLAGS image on the
  55 stack or in the TSS when first creating a V86 task. Exception and interrupt
  56 handlers can examine the VM flag on the stack. If the interrupted procedure
  57 was executing in V86 mode, the handler may need to invoke the V86 monitor.
  58 <P>
  59 <A NAME="fig15-2">
  60 <IMG align=center SRC="fig15-2.gif" border=0>
  61
  62 <H2>15.3.1  Transitions Through Task Switches</H2>
  63 A task switch to or from a V86 task may be due to any of three causes:
  64 <OL>
  65 <LI> An interrupt that vectors to a task gate.
  66 <LI> An action of the scheduler of the 80386 operating system.
  67 <LI> An <A HREF="IRET.htm">IRET</A> when the NT flag is set.
  68 </OL>
  69 In any of these cases, the processor changes the VM bit in EFLAGS according
  70 to the image of EFLAGS in the new TSS. If the new TSS is an 80286 TSS, the
  71 high-order word of EFLAGS is not in the TSS; the processor clears VM in this
  72 case. The processor updates VM prior to loading the segment registers from
  73 the images in the new TSS. The new setting of VM determines whether the
  74 processor interprets the new segment-register images as 8086 selectors or
  75 80386/80286 selectors.
  76
  77 <H2>15.3.2  Transitions Through Trap Gates and Interrupt Gates</H2>
  78 The processor leaves V86 mode as the result of an exception or interrupt
  79 that vectors via a trap or interrupt gate to a privilege-level zero
  80 procedure. The exception or interrupt handler returns to the 8086 code by
  81 executing an <A HREF="IRET.htm">IRET</A>.
  82 <P>
  83 Because it was designed for execution by an 8086 processor, an 8086 program
  84 in a V86 task will have an 8086-style interrupt table starting at linear
  85 address zero. However, the 80386 does not use this table directly. For all
  86 exceptions and interrupts that occur in V86 mode, the processor vectors
  87 through the IDT. The IDT entry for an interrupt or exception that occurs in
  88 a V86 task must contain either:
  89 <UL>
  90 <LI> A task gate.
  91 <LI> An 80386 trap gate (type 14) or an 80386 interrupt gate (type 15),
  92 which must point to a nonconforming, privilege-level zero, code
  93 segment.
  94 </UL>
  95 Interrupts and exceptions that have 80386 trap or interrupt gates in the
  96 IDT vector to the appropriate handler procedure at privilege-level zero. The
  97 contents of all the 8086 segment registers are stored on the PL 0 stack.
  98
  99 <A HREF="#fig15-3">Figure 15-3</A>
 100   shows the format of the PL 0 stack after an exception or
 101 interrupt that occurs while a V86 task is executing an 8086 program.
 102 <P>
 103 After the processor stores all the 8086 segment registers on the PL 0
 104 stack, it loads all the segment registers with zeros before starting to
 105 execute the handler procedure. This permits the interrupt handler to safely
 106 save and restore the DS, ES, FS, and GS registers as 80386 selectors.
 107 Interrupt handlers that may be invoked in the context of either a regular
 108 task or a V86 task, can use the same prolog and epilog code for register
 109 saving regardless of the kind of task. Restoring zeros to these registers
 110 before execution of the <A HREF="IRET.htm">IRET</A> does not cause a trap in the interrupt handler.
 111 Interrupt procedures that expect values in the segment registers or that
 112 return values via segment registers have to use the register images stored
 113 on the PL 0 stack. Interrupt handlers that need to know whether the
 114 interrupt occurred in V86 mode can examine the VM bit in the stored EFLAGS
 115 image.
 116 <P>
 117 An interrupt handler passes control to the V86 monitor if the VM bit is set
 118 in the EFLAGS image stored on the stack and the interrupt or exception is
 119 one that the monitor needs to handle. The V86 monitor may either:
 120 <UL>
 121 <LI> Handle the interrupt completely within the V86 monitor.
 122 <LI> Invoke the 8086 program's interrupt handler.
 123 </UL>
 124 <P>
 125 Reflecting an interrupt or exception back to the 8086 code involves the
 126 following steps:
 127 <OL>
 128 <LI> Refer to the 8086 interrupt vector to locate the appropriate handler
 129 procedure.
 130 <LI> Store the state of the 8086 program on the privilege-level three
 131 stack.
 132 <LI> Change the return link on the privilege-level zero stack to point to
 133 the privilege-level three handler procedure.
 134 <LI> Execute an <A HREF="IRET.htm">IRET</A> so as to pass control to the handler.
 135 <LI> When the <A HREF="IRET.htm">IRET</A> by the privilege-level three handler again traps to the
 136 V86 monitor, restore the return link on the privilege-level zero stack
 137 to point to the originally interrupted, privilege-level three
 138 procedure.
 139 <LI> Execute an <A HREF="IRET.htm">IRET</A> so as to pass control back to the interrupted
 140 procedure.
 141 </OL>
 142
 143 <A NAME="fig15-3">
 144 <IMG align=center SRC="fig15-3.gif" border=0>
 145
 146 <P>
 147 <HR>
 148 <P>
 149 <B>up:</B> <A HREF="c15.htm">
 150 Chapter 15 -- Virtual 8086 Mode</A><BR>
 151 <B>prev:</B> <A HREF="s15_02.htm">15.2  Structure of a V86 Task</A><BR>
 152 <B>next:</B> <A HREF="s15_04.htm">15.4  Additional Sensitive Instructions</A>
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