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3 <HEAD>
4 <TITLE>80386 Programmer's Reference Manual -- Section 14.8</TITLE>
5 </HEAD>
6 <BODY>
7 <B>up:</B> <A HREF="c14.htm">
8 Chapter 14 -- 80386 Real-Address Mode</A><BR>
9 <B>prev:</B> <A HREF="s14_07.htm">14.7 Differences From 8086</A><BR>
10 <B>next:</B> <A HREF="c15.htm">Chapter 15 -- Virtual 8086 Mode</A>
11 <P>
12 <HR>
13 <P>
14 <H1>14.8 Differences From 80286 Real-Address Mode</H1>
15 The few differences that exist between 80386 real-address mode and 80286
16 real-address mode are not likely to affect any existing 80286 programs
17 except possibly the system initialization procedures.
19 <H2>14.8.1 Bus Lock</H2>
20 The 80286 processor implements the bus lock function differently than the
21 80386. Programs that use forms of memory locking specific to the 80286 may
22 not execute properly if transported to a specific application of the 80386.
23 <P>
24 The
25 <A HREF="LOCK.htm">LOCK</A>
26 prefix and its corresponding output signal should only be used to
27 prevent other bus masters from interrupting a data movement operation.
28 <A HREF="LOCK.htm">LOCK</A>
29 may only be used with the following 80386 instructions when they modify
30 memory. An undefined-opcode exception results from using
31 <A HREF="LOCK.htm">LOCK</A> before any
32 other instruction.
33 <UL>
34 <LI> Bit test and change:
35 <A HREF="BTS.htm">BTS</A>,
36 <A HREF="BTR.htm">BTR</A>,
37 <A HREF="BTC.htm">BTC</A>.
38 <LI> Exchange:
39 <A HREF="XCHG.htm">XCHG</A>.
40 <LI> One-operand arithmetic and logical:
41 <A HREF="INC.htm">INC</A>,
42 <A HREF="DEC.htm">DEC</A>,
43 <A HREF="NOT.htm">NOT</A>, and
44 <A HREF="NEG.htm">NEG</A>.
45 <LI> Two-operand arithmetic and logical:
46 <A HREF="ADD.htm">ADD</A>,
47 <A HREF="ADC.htm">ADC</A>,
48 <A HREF="SUB.htm">SUB</A>,
49 <A HREF="SBB.htm">SBB</A>,
50 <A HREF="AND.htm">AND</A>,
51 <A HREF="OR.htm">OR</A>,
52 <A HREF="XOR.htm">XOR</A>.
53 </UL>
54 A locked instruction is guaranteed to lock only the area of memory defined
55 by the destination operand, but may lock a larger memory area. For example,
56 typical 8086 and 80286 configurations lock the entire physical memory space.
57 With the 80386, the defined area of memory is guranteed to be locked against
58 access by a processor executing a locked instruction on exactly the same
59 memory area, i.e., an operand with identical starting address and identical
60 length.
62 <H2>14.8.2 Location of First Instruction</H2>
63 The starting location is 0FFFFFFF0H (sixteen bytes from end of 32-bit
64 address space) on the 80386 rather than 0FFFFF0H (sixteen bytes from end of
65 24-bit address space) as on the 80286. Many 80286 ROM initialization
66 programs will work correctly in this new environment. Others can be made to
67 work correctly with external hardware that redefines the signals on
68 A{31-20}.
70 <H2>14.8.3 Initial Values of General Registers</H2>
71 On the 80386, certain general registers may contain different values after
72 RESET than on the 80286. This should not cause compatibility problems,
73 because the content of 8086 registers after RESET is undefined. If
74 self-test is requested during the reset sequence and errors are detected in
75 the 80386 unit, EAX will contain a nonzero value. EDX contains the component
76 and revision identifier . Refer to
77 <A HREF="c10.htm">Chapter 10</A>
78 for more information .
80 <H2>14.8.4 MSW Initialization</H2>
81 The 80286 initializes the MSW register to FFF0H, but the 80386 initializes
82 this register to 0000H. This difference should have no effect, because the
83 bits that are different are undefined on the 80286. Programs that read the
84 value of the MSW will behave differently on the 80386 only if they depend on
85 the setting of the undefined, high-order bits.
86 <P>
87 <HR>
88 <P>
89 <B>up:</B> <A HREF="c14.htm">
90 Chapter 14 -- 80386 Real-Address Mode</A><BR>
91 <B>prev:</B> <A HREF="s14_07.htm">14.7 Differences From 8086</A><BR>
92 <B>next:</B> <A HREF="c15.htm">Chapter 15 -- Virtual 8086 Mode</A>
93 </BODY>