i386/i386.reference/s12_02.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 12.2</TITLE>
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   7 <B>up:</B> <A HREF="c12.htm">
   8 Chapter 12 -- Debugging</A><BR>
   9 <B>prev:</B> <A HREF="s12_01.htm">12.1  Debugging Features of the Architecture</A><BR>
  10 <B>next:</B> <A HREF="s12_03.htm">12.3  Debug Exceptions</A>
  11 <P>
  12 <HR>
  13 <P>
  14 <H1>12.2  Debug Registers</H1>
  15 Six 80386 registers are used to control debug features. These registers are
  16 accessed by variants of the <A HREF="MOVRS.htm">MOV</A> instruction. A debug register may be either
  17 the source operand or destination operand. The debug registers are
  18 privileged resources; the <A HREF="MOVRS.htm">MOV</A> instructions that access them can only be
  19 executed at privilege level zero. An attempt to read or write the debug
  20 registers when executing at any other privilege level causes a general
  21 protection exception.
  22 <A HREF="#fig12-1">Figure 12-1</A>
  23   shows the format of the debug registers.
  24 <P>
  25 <A NAME="fig12-1">
  26 <IMG align=center SRC="fig12-1.gif" border=0>
  27
  28 <H2>12.2.1  Debug Address Registers (DR0-DR3)</H2>
  29 Each of these registers contains the linear address associated with one of
  30 four breakpoint conditions. Each breakpoint condition is further defined by
  31 bits in DR7.
  32 <P>
  33 The debug address registers are effective whether or not paging is enabled.
  34 The addresses in these registers are linear addresses. If paging is enabled,
  35 the linear addresses are translated into physical addresses by the
  36 processor's paging mechanism (as explained in
  37 <A HREF="c05.htm">Chapter 5</A>
  38    ) . If paging is not
  39 enabled, these linear addresses are the same as physical addresses.
  40 <P>
  41 Note that when paging is enabled, different tasks may have different
  42 linear-to-physical address mappings. When this is the case, an address in a
  43 debug address register may be relevant to one task but not to another. For
  44 this reason the 80386  has both global and local enable bits in DR7. These
  45 bits indicate whether a given debug address has a global (all tasks) or
  46 local (current task only) relevance.
  47
  48 <H2>12.2.2  Debug Control Register (DR7)</H2>
  49 The debug control register shown in
  50 <A HREF="#fig12-1">Figure 12-1</A>
  51   both helps to define the
  52 debug conditions and selectively enables and disables those conditions.
  53 <P>
  54 For each address in registers DR0-DR3, the corresponding fields R/W0
  55 through R/W3 specify the type of action that should cause a breakpoint. The
  56 processor interprets these bits as follows:
  57 <UL>
  58 <LI>00 -- Break on instruction execution only
  59 <LI>01 -- Break on data writes only
  60 <LI>10 -- undefined
  61 <LI>11 -- Break on data reads or writes but not instruction fetches
  62 </UL>
  63 Fields LEN0 through LEN3 specify the length of data item to be monitored. A
  64 length of 1, 2, or 4 bytes may be specified. The values of the length fields
  65 are interpreted as follows:
  66 <UL>
  67 <LI>00 -- one-byte length
  68 <LI>01 -- two-byte length
  69 <LI>10 -- undefined
  70 <LI>11 -- four-byte length
  71 </UL>
  72 If RWn is 00 (instruction execution), then LENn should also be 00. Any other
  73 length is undefined.
  74 <P>
  75 The low-order eight bits of DR7 (L0 through L3 and G0 through G3)
  76 selectively enable the four address breakpoint conditions. There are two
  77 levels of enabling: the local (L0 through L3) and global (G0 through G3)
  78 levels. The local enable bits are automatically reset by the processor at
  79 every task switch to avoid unwanted breakpoint conditions in the new task.
  80 The global enable bits are not reset by a task switch; therefore, they can
  81 be used for conditions that are global to all tasks.
  82 <P>
  83 The LE and GE bits control the "exact data breakpoint match" feature of the
  84 processor. If either LE or GE is set, the processor slows execution so that
  85 data breakpoints are reported on the instruction that causes them. It is
  86 recommended that one of these bits be set whenever data breakpoints are
  87 armed. The processor clears LE at a task switch but does not clear GE.
  88
  89 <H2>12.2.3  Debug Status Register (DR6)</H2>
  90 The debug status register shown in
  91 <A HREF="#fig12-1">Figure 12-1</A>
  92   permits the debugger to
  93 determine which debug conditions have occurred.
  94 <P>
  95 When the processor detects an enabled debug exception, it sets the
  96 low-order bits of this register (B0 thru B3) before entering the debug
  97 exception handler. Bn is set if the condition described by DRn, LENn, and
  98 R/Wn occurs. (Note that the processor sets Bn regardless of whether Gn or
  99 Ln is set. If more than one breakpoint condition occurs at one time and if
 100 the breakpoint trap occurs due to an enabled condition other than n, Bn may
 101 be set, even though neither Gn nor Ln is set.)
 102 <P>
 103 The BT bit is associated with the T-bit (debug trap bit) of the TSS (refer
 104 to 7 for the location of the T-bit). The processor sets the BT bit before
 105 entering the debug handler if a task switch has occurred and the T-bit of
 106 the new TSS is set. There is no corresponding bit in DR7 that enables and
 107 disables this trap; the T-bit of the TSS is the sole enabling bit.
 108 <P>
 109 The BS bit is associated with the TF (trap flag) bit of the EFLAGS
 110 register. The BS bit is set if the debug handler is entered due to the
 111 occurrence of a single-step exception. The single-step trap is the
 112 highest-priority debug exception; therefore, when BS is set, any of the
 113 other debug status bits may also be set.
 114 <P>
 115 The BD bit is set if the next instruction will read or write one of the
 116 eight debug registers and ICE-386 is also using the debug registers at the
 117 same time.
 118 <P>
 119 Note that the bits of DR6 are never cleared by the processor. To avoid any
 120 confusion in identifying the next debug exception, the debug handler should
 121 move zeros to DR6 immediately before returning.
 122
 123 <H2>12.2.4  Breakpoint Field Recognition</H2>
 124 The linear address and LEN field for each of the four breakpoint conditions
 125 define a range of sequential byte addresses for a data breakpoint. The LEN
 126 field permits specification of a one-, two-, or four-byte field. Two-byte
 127 fields must be aligned on word boundaries (addresses that are multiples of
 128 two) and four-byte fields must be aligned on doubleword boundaries
 129 (addresses that are multiples of four). These requirements are enforced by
 130 the processor; it uses the LEN bits to mask the low-order bits of the
 131 addresses in the debug address registers. Improperly aligned code or data
 132 breakpoint addresses will not yield the expected results.
 133 <P>
 134 A data read or write breakpoint is triggered if any of the bytes
 135 participating in a memory access is within the field defined by a breakpoint
 136 address register and the corresponding LEN field.
 137 <A HREF="#Table 12-1">Table 12-1</A> gives some
 138 examples of breakpoint fields with memory references that both do and do not
 139 cause traps.
 140 <P>
 141 To set a data breakpoint for a misaligned field longer than one byte, it
 142 may be desirable to put two sets of entries in the breakpoint register such
 143 that each entry is properly aligned and the two entries together span the
 144 length of the field.
 145 <P>
 146 Instruction breakpoint addresses must have a length specification of one
 147 byte (LEN = 00); other values are undefined. The processor recognizes an
 148 instruction breakpoint address only when it points to the first byte of an
 149 instruction. If the instruction has any prefixes, the breakpoint address
 150 must point to the first prefix.
 151
 152 <PRE>
 153 <A NAME="Table 12-1">Table 12-1. Breakpoint Field Recognition Examples
 154
 155 Address (hex)          Length
 156
 157 DR0             0A0001          1 (LEN0 = 00)
 158 Register Contents      DR1             0A0002          1 (LEN1 = 00)
 159 DR2             0B0002          2 (LEN2 = 01)
 160 DR3             0C0000          4 (LEN3 = 11)
 161
 162 Some Examples of Memory                0A0001          1
 163 References That Cause Traps            0A0002          1
 164 0A0001          2
 165 0A0002          2
 166 0B0002          2
 167 0B0001          4
 168 0C0000          4
 169 0C0001          2
 170 0C0003          1
 171
 172 Some Examples of Memory                0A0000          1
 173 References That Don't Cause Traps      0A0003          4
 174 0B0000          2
 175 0C0004          4
 176 </A>
 177 </PRE>
 178 <P>
 179 <HR>
 180 <P>
 181 <B>up:</B> <A HREF="c12.htm">
 182 Chapter 12 -- Debugging</A><BR>
 183 <B>prev:</B> <A HREF="s12_01.htm">12.1  Debugging Features of the Architecture</A><BR>
 184 <B>next:</B> <A HREF="s12_03.htm">12.3  Debug Exceptions</A>
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