i386/i386.reference/s10_06.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 10.6</TITLE>
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   7 <B>up:</B> <A HREF="c10.htm">
   8 Chapter 10 -- Initialization</A><BR>
   9 <B>prev:</B> <A HREF="s10_05.htm">10.5  Initialization Example</A><BR>
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  11 <A HREF="c11.htm">Chapter 11 -- Coprocessing and Multiprocessing</A>
  12 <P>
  13 <HR>
  14 <P>
  15 <H1>10.6  TLB Testing</H1>
  16 The 80386 provides a mechanism for testing the Translation Lookaside Buffer
  17 (TLB), the cache used for translating linear addresses to physical
  18 addresses. Although failure of the TLB hardware is extremely unlikely, users
  19 may wish to include TLB confidence tests among other power-up confidence
  20 tests for the 80386.
  21 <P>
  22 <HR>
  23 <P>
  24 <EM>
  25 <H3>Note</H3>
  26 This TLB testing mechanism is unique to the 80386 and may not be
  27 continued in the same way in future processors. Sortware that uses
  28 this mechanism may be incompatible with future processors.
  29 </EM>
  30 <P>
  31 <HR>
  32 <P>
  33 When testing the TLB it is recommended that paging be turned off (PG=0 in
  34 CR0) to avoid interference with the test data being written to the TLB.
  35
  36 <H2>10.6.1  Structure of the TLB</H2>
  37 The TLB is a four-way set-associative memory.
  38 <A HREF="#fig10-3">Figure 10-3</A>
  39   illustrates the
  40 structure of the TLB. There are four sets of eight entries each. Each entry
  41 consists of a tag and data. Tags are 24-bits wide. They contain the
  42 high-order 20 bits of the linear address, the valid bit, and three attribute
  43 bits. The data portion of each entry contains the high-order 20 bits of the
  44 physical address.
  45
  46 <H2>10.6.2  Test Registers</H2>
  47 Two test registers, shown in
  48 <A HREF="#fig10-4">Figure 10-4</A>, are provided for the purpose of
  49 testing. TR6 is the test command register, and TR7 is the test data
  50 register. These registers are accessed by variants of the
  51 <A HREF="MOVRS.htm">MOV</A>
  52 instruction. A test register may be either the source operand or destination
  53 operand. The
  54 <A HREF="MOVRS.htm">MOV</A> instructions are defined in both
  55 real-address mode and
  56 protected mode. The test registers are privileged resources; in protected
  57 mode, the
  58 <A HREF="MOVRS.htm">MOV</A> instructions that access them can only
  59 be executed at
  60 privilege level 0. An attempt to read or write the test registers when
  61 executing at any other privilege level causes a general
  62 protection exception.
  63 <P>
  64 The test command register (TR6) contains a command and an address tag to
  65 use in performing the command:
  66 <DL>
  67 <DT>
  68 C
  69 <DD>
  70 This is the command bit. There are two TLB testing commands:
  71 write entries into the TLB, and perform TLB lookups. To cause an
  72 immediate write into the TLB entry, move a doubleword into TR6
  73 that contains a 0 in this bit. To cause an immediate TLB lookup,
  74 move a doubleword into TR6 that contains a 1 in this bit.
  75 <DT>
  76 Linear Address
  77 <DD>
  78 On a TLB write, a TLB entry is allocated to this linear address;
  79 the rest of that TLB entry is set per the value of TR7 and the
  80 value just written into TR6. On a TLB lookup, the TLB is
  81 interrogated per this value; if one and only one TLB entry
  82 matches, the rest of the fields of TR6 and TR7 are set from the
  83 matching TLB entry.
  84 <DT>
  85 V
  86 <DD>
  87 The valid bit for this TLB entry. The TLB uses the valid bit to
  88 identify entries that contain valid data. Entries of the TLB
  89 that have not been assigned values have zero in the valid bit.
  90 All valid bits can be cleared by writing to CR3.
  91 <DT>
  92 D, D#
  93 <DD>
  94 The dirty bit (and its complement) for/from the TLB entry.
  95 <DT>
  96 U, U#
  97 <DD>
  98 The U/S bit (and its complement) for/from the TLB entry.
  99 <DT>
 100 W, W#
 101 <DD>
 102 The R/W bit (and its complement) for/from the TLB entry.
 103 <P>
 104 The meaning of these pairs of bits is given by Table 10-1,
 105 where X represents D, U, or W.
 106 </DL>
 107 The test data register (TR7) holds data read from or data to be written to
 108 the TLB.
 109 <DL>
 110 <DT>
 111 Physical Address
 112 <DD>
 113 This is the data field of the TLB. On a write to the TLB, the
 114 TLB entry allocated to the linear address in TR6 is set to this
 115 value. On a TLB lookup, if HT is set, the data field (physical
 116 address) from the TLB is read out to this field. If HT is not
 117 set, this field is undefined.
 118 <DT>
 119 HT
 120 <DD>
 121 For a TLB lookup, the HT bit indicates whether the lookup was a
 122 hit (HT := 1) or a miss (HT := 0). For a TLB write, HT must be set
 123 to 1.
 124 <DT>
 125 <A HREF="REP.htm">REP</A>
 126 <DD>
 127 For a TLB write, selects which of four associative blocks of the
 128 TLB is to be written. For a TLB read, if HT is set,
 129 <A HREF="REP.htm">REP</A> reports
 130 in which of the four associative blocks the tag was found; if HT
 131 is not set, <A HREF="REP.htm">REP</A> is undefined.
 132 </DL>
 133 <PRE>
 134 Table 10-1. Meaning of D, U, and W Bit Pairs
 135
 136 X     X#      Effect during        Value of bit X
 137 TLB Lookup           after TLB Write
 138
 139 0     0       (undefined)          (undefined)
 140 0     1       Match if X=0         Bit X becomes 0
 141 1     0       Match if X=1         Bit X becomes 1
 142 1     1       (undefined)          (undefined)
 143 </PRE>
 144 <P>
 145 <A NAME="fig10-3">
 146 <IMG align=center SRC="fig10-3.gif" border=0>
 147 <HR>
 148 <A NAME="fig10-4">
 149 <IMG align=center SRC="fig10-4.gif" border=0>
 150
 151 <H2>10.6.3  Test Operations</H2>
 152 To write a TLB entry:
 153 <OL>
 154 <LI> Move a doubleword to TR7 that contains the desired physical address,
 155 HT, and <A HREF="REP.htm">REP</A> values. HT must contain 1.
 156 <A HREF="REP.htm">REP</A> must point to the
 157 associative block in which to place the entry.
 158 <LI> Move a doubleword to TR6 that contains the appropriate linear
 159 address, and values for V, D, U, and W. Be sure C=0 for "write"
 160 command.
 161 </OL>
 162 Be careful not to write duplicate tags; the results of doing so are
 163 undefined.
 164 To look up (read) a TLB entry:
 165 <OL>
 166 <LI> Move a doubleword to TR6 that contains the appropriate linear address
 167 and attributes. Be sure C=1 for "lookup" command.
 168 <LI> Store TR7. If the HT bit in TR7 indicates a hit, then the other
 169 values reveal the TLB contents. If HT indicates a miss, then the other
 170 values in TR7 are indeterminate.
 171 </OL>
 172 For the purposes of testing, the V bit functions as another bit of
 173 addresss.  The V bit for a lookup request should usually be set, so that
 174 uninitialized tags do not match. Lookups with V=0 are unpredictable if any
 175 tags are uninitialized.
 176 <P>
 177 <HR>
 178 <P>
 179 <B>up:</B> <A HREF="c10.htm">
 180 Chapter 10 -- Initialization</A><BR>
 181 <B>prev:</B> <A HREF="s10_05.htm">10.5  Initialization Example</A><BR>
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 183 <A HREF="c11.htm">Chapter 11 -- Coprocessing and Multiprocessing</A>
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