i386/i386.reference/s10_04.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 10.4</TITLE>
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   7 <B>up:</B> <A HREF="c10.htm">
   8 Chapter 10 -- Initialization</A><BR>
   9 <B>prev:</B> <A HREF="s10_03.htm">10.3  Switching to Protected Mode</A><BR>
  10 <B>next:</B> <A HREF="s10_05.htm">10.5  Initialization Example</A>
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  12 <HR>
  13 <P>
  14 <H1>10.4  Software Initialization for Protected Mode</H1>
  15 Most of the initialization needed for protected mode can be done either
  16 before or after switching to protected mode. If done in protected mode,
  17 however, the initialization procedures must not use protected-mode features
  18 that are not yet initialized.
  19
  20 <H2>10.4.1  Interrupt Descriptor Table</H2>
  21 The IDTR may be loaded in either real-address or protected mode. However,
  22 the format of the interrupt table for protected mode is different than that
  23 for real-address mode. It is not possible to change to protected mode and
  24 change interrupt table formats at the same time; therefore, it is inevitable
  25 that, if IDTR selects an interrupt table, it will have the wrong format at
  26 some time. An interrupt or exception that occurs at this time will have
  27 unpredictable results. To avoid this unpredictability, interrupts should
  28 remain disabled until interrupt handlers are in place and a valid IDT has
  29 been created in protected mode.
  30
  31 <H2>10.4.2  Stack</H2>
  32 The SS register may be loaded in either real-address mode or protected
  33 mode. If loaded in real-address mode, SS continues to point to the same
  34 linear base-address after the switch to protected mode.
  35
  36 <H2>10.4.3  Global Descriptor Table</H2>
  37 Before any segment register is changed in protected mode, the GDT register
  38 must point to a valid GDT. Initialization of the GDT and GDTR may be done in
  39 real-address mode. The GDT (as well as LDTs) should reside in RAM, because
  40 the processor modifies the accessed bit of descriptors.
  41
  42 <H2>10.4.4  Page Tables</H2>
  43 Page tables and the PDBR in CR3 can be initialized in either real-address
  44 mode or in protected mode; however, the paging enabled (PG) bit of CR0
  45 cannot be set until the processor is in protected mode. PG may be set
  46 simultaneously with PE, or later. When PG is set, the PDBR in CR3 should
  47 already be initialized with a physical address that points to a valid page
  48 directory. The initialization procedure should adopt one of the following
  49 strategies to ensure consistent addressing before and after paging is
  50 enabled:
  51 <UL>
  52 <LI> The page that is currently being executed should map to the same
  53 physical addresses both before and after PG is set.
  54 <LI> A
  55 <A HREF="JMP.htm">JMP</A> instruction should immediately follow the setting of PG.
  56 </UL>
  57
  58 <H2>10.4.5  First Task</H2>
  59 The initialization procedure can run awhile in protected mode without
  60 initializing the task register; however, before the first task switch, the
  61 following conditions must prevail:
  62 <UL>
  63 <LI> There must be a valid task state segment (TSS) for the new task. The
  64 stack pointers in the TSS for privilege levels numerically less than or
  65 equal to the initial CPL must point to valid stack segments.
  66 <LI> The task register must point to an area in which to save the current
  67 task state. After the first task switch, the information dumped in this
  68 area is not needed, and the area can be used for other purposes.
  69 </UL>
  70 <P>
  71 <HR>
  72 <P>
  73 <B>up:</B> <A HREF="c10.htm">
  74 Chapter 10 -- Initialization</A><BR>
  75 <B>prev:</B> <A HREF="s10_03.htm">10.3  Switching to Protected Mode</A><BR>
  76 <B>next:</B> <A HREF="s10_05.htm">10.5  Initialization Example</A>
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