i386/i386.reference/s03_08.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 3.8</TITLE>
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   7 <B>up:</B> <A HREF="c03.htm">
   8 Chapter 3 -- Applications Instruction Set</A><BR>
   9 <B>prev:</B> <A HREF="s03_07.htm">3.7  Instructions for Block-Structured Languages</A><BR>
  10 <B>next:</B> <A HREF="s03_09.htm">3.9  Coprocessor Interface Instructions</A>
  11 <P>
  12 <HR>
  13 <P>
  14 <H1>3.8  Flag Control Instructions</H1>
  15 The flag control instructions provide a method for directly changing the
  16 state of bits in the flag register.
  17
  18 <H2>3.8.1  Carry and Direction Flag Control Instructions</H2>
  19 The carry flag instructions are useful in conjunction with
  20 rotate-with-carry instructions <A HREF="RCL.htm">RCL</A> and
  21 <A HREF="RCL.htm">RCR</A>. They can initialize the carry
  22 flag, CF, to a known state before execution of a rotate that moves the carry
  23 bit into one end of the rotated operand.
  24 <P>
  25 The direction flag control instructions are specifically included to set or
  26 clear the direction flag, DF, which controls the left-to-right or
  27 right-to-left direction of string processing. If DF=0, the processor
  28 automatically increments the string index registers, ESI and EDI, after each
  29 execution of a string primitive. If DF=1, the processor decrements these
  30 index registers. Programmers should use one of these instructions before any
  31 procedure that uses string instructions to insure that DF is set properly.
  32 <PRE>
  33 Flag Control Instruction                  Effect
  34 <A HREF="STC.htm">STC</A> (Set Carry Flag)                      CF := 1
  35 <A HREF="CLC.htm">CLC</A> (Clear Carry Flag)                    CF := 0
  36 <A HREF="CMC.htm">CMC</A> (Complement Carry Flag)               CF := NOT (CF)
  37 <A HREF="CLD.htm">CLD</A> (Clear Direction Flag)                DF := 0
  38 <A HREF="STD.htm">STD</A> (Set Direction Flag)                  DF := 1
  39 </PRE>
  40
  41 <H2>3.8.2  Flag Transfer Instructions</H2>
  42 Though specific instructions exist to alter CF and DF, there is no direct
  43 method of altering the other applications-oriented flags. The flag transfer
  44 instructions allow a program to alter the other flag bits with the bit
  45 manipulation instructions after transferring these flags to the stack or the
  46 AH register.
  47 <P>
  48 The instructions
  49 <A HREF="LAHF.htm">LAHF</A> and
  50 <A HREF="SAHF.htm">SAHF</A> deal with five of the status flags, which
  51 are used primarily by the arithmetic and logical instructions.
  52 <P>
  53 <A HREF="LAHF.htm">LAHF</A> (Load AH from Flags)
  54 copies SF, ZF, AF, PF, and CF to AH bits 7, 6, 4,
  55 2, and 0, respectively (see
  56 <A HREF="#fig3-22">Figure 3-22</A>).
  57 The contents of the remaining bits
  58 (5, 3, and 1) are undefined. The flags remain unaffected.
  59 <P>
  60 <A HREF="SAHF.htm">SAHF</A> (Store AH into Flags)
  61 transfers bits 7, 6, 4, 2, and 0 from AH into
  62 SF, ZF, AF, PF, and CF, respectively (see
  63 <A HREF="#fig3-22">Figure 3-22</A>).
  64 <P>
  65 The
  66 <A HREF="PUSHF.htm">PUSHF</A> and
  67 <A HREF="POPF.htm">POPF</A> instructions are not only useful for
  68 storing the flags
  69 in memory where they can be examined and modified but are also useful for
  70 preserving the state of the flags register while executing a procedure.
  71 <P>
  72 <A HREF="PUSHF.htm">PUSHF</A> (Push Flags)
  73 decrements ESP by two and then transfers the low-order
  74 word of the flags register to the word at the top of stack pointed to by ESP
  75 (see
  76 <A HREF="s03_09.htm#fig3-23">Figure 3-23</A>).
  77 The variant <A HREF="PUSHF.htm">PUSHFD</A> decrements ESP by four, then
  78 transfers both words of the extended flags register to the top of the stack
  79 pointed to by ESP (the VM and RF flags are not moved, however).
  80 <P>
  81 <A HREF="POPF.htm">POPF</A> (Pop Flags)
  82 transfers specific bits from the word at the top of stack
  83 into the low-order byte of the flag register (see
  84 <A HREF="s03_09.htm#fig3-23">Figure 3-23</A>), then
  85 increments ESP by two. The variant
  86 <A HREF="POPF.htm">POPFD</A> transfers specific bits from the
  87 doubleword at the top of the stack into the extended flags register (the RF
  88 and VM flags are not changed, however), then increments ESP by four.
  89 <P>
  90 <A NAME="fig3-22">
  91 <IMG align=center SRC="fig3-22.gif" border=0>
  92 <P>
  93 <HR>
  94 <P>
  95 <B>up:</B> <A HREF="c03.htm">
  96 Chapter 3 -- Applications Instruction Set</A><BR>
  97 <B>prev:</B> <A HREF="s03_07.htm">3.7  Instructions for Block-Structured Languages</A><BR>
  98 <B>next:</B> <A HREF="s03_09.htm">3.9  Coprocessor Interface Instructions</A>
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