i386/i386.reference/s03_04.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Section 3.4</TITLE>
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   7 <B>up:</B> <A HREF="c03.htm">
   8 Chapter 3 -- Applications Instruction Set</A><BR>
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  11 <P>
  12 <HR>
  13 <P>
  14 <H1>3.4  Logical Instructions</H1>
  15 The group of logical instructions includes:
  16 <UL>
  17 <LI> The Boolean operation instructions
  18 <LI> Bit test and modify instructions
  19 <LI> Bit scan instructions
  20 <LI> Rotate and shift instructions
  21 <LI> Byte set on condition
  22 </UL>
  23 <H2>3.4.1  Boolean Operation Instructions</H2>
  24 The logical operations are <A HREF="AND.htm">AND</A>,
  25 <A HREF="OR.htm">OR</A>,
  26 <A HREF="XOR.htm">XOR</A>, and
  27 <A HREF="NOT.htm">NOT</A>.
  28 <P>
  29 <A HREF="NOT.htm">NOT</A> (Not)
  30 inverts the bits in the specified operand to form a one's
  31 complement of the operand. The
  32 <A HREF="NOT.htm">NOT</A> instruction is a unary operation that
  33 uses a single operand in a register or memory.
  34 <A HREF="NOT.htm">NOT</A> has no effect on the
  35 flags.
  36 <P>
  37 The
  38 <A HREF="AND.htm">AND</A>,
  39 <A HREF="OR.htm">OR</A>, and
  40 <A HREF="XOR.htm">XOR</A> instructions perform the standard logical operations
  41 "and", "(inclusive) or", and "exclusive or". These instructions can use the
  42 following combinations of operands:
  43 <UL>
  44 <LI> Two register operands
  45 <LI> A general register operand with a memory operand
  46 <LI> An immediate operand with either a general register operand or a
  47 memory operand.
  48 </UL>
  49 <A HREF="AND.htm">AND</A>,
  50 <A HREF="OR.htm">OR</A>, and
  51 <A HREF="XOR.htm">XOR</A> clear OF and CF, leave AF undefined,
  52 and update SF, ZF, and PF.
  53
  54 <H2>3.4.2  Bit Test and Modify Instructions</H2>
  55 This group of instructions operates on a single bit which can be in memory
  56 or in a general register. The location of the bit is specified as an offset
  57 from the low-order end of the operand. The value of the offset either may be
  58 given by an immediate byte in the instruction or may be contained in a
  59 general register.
  60 <P>
  61 These instructions first assign the value of the selected bit to CF, the
  62 carry flag. Then a new value is assigned to the selected bit, as determined
  63 by the operation. OF, SF, ZF, AF, PF are left in an undefined state. Table
  64 3-1 defines these instructions.
  65 <PRE>
  66 Table 3-1. Bit Test and Modify Instructions
  67
  68 Instruction                      Effect on CF            Effect on
  69                                                          Selected Bit
  70
  71 Bit (Bit Test)                   CF := BIT                (none)
  72 BTS (Bit Test and Set)           CF := BIT                BIT := 1
  73 BTR (Bit Test and Reset)         CF := BIT                BIT := 0
  74 BTC (Bit Test and Complement)    CF := BIT                BIT := NOT(BIT)
  75 </PRE>
  76
  77 <H2>3.4.3  Bit Scan Instructions</H2>
  78 These instructions scan a word or doubleword for a one-bit and store the
  79 index of the first set bit into a register.  The bit string being scanned
  80 may be either in a register or in memory. The ZF flag is set if the entire
  81 word is zero (no set bits are found); ZF is cleared if a one-bit is found.
  82 If no set bit is found, the value of the destination register is undefined.
  83 <P>
  84 <A HREF="BSF.htm">BSF</A> (Bit Scan Forward)
  85 scans from low-order to high-order (starting from bit index zero).
  86 <P>
  87 <A HREF="BSR.htm">BSR</A> (Bit Scan Reverse)
  88 scans from high-order to low-order (starting from
  89 bit index 15 of a word or index 31 of a doubleword).
  90
  91 <H2>3.4.4  Shift and Rotate Instructions</H2>
  92 The shift and rotate instructions reposition the bits within the specified
  93 operand.
  94 <P>
  95 These instructions fall into the following classes:
  96 <UL>
  97 <LI> Shift instructions
  98 <LI> Double shift instructions
  99 <LI> Rotate instructions
 100 </UL>
 101
 102 <H3>3.4.4.1  Shift Instructions</H3>
 103 The bits in bytes, words, and doublewords may be shifted arithmetically or
 104 logically. Depending on the value of a specified count, bits can be shifted
 105 up to 31 places.
 106 <P>
 107 A shift instruction can specify the count in one of three ways. One form of
 108 shift instruction implicitly specifies the count as a single shift. The
 109 second form specifies the count as an immediate value. The third form
 110 specifies the count as the value contained in CL. This last form allows the
 111 shift count to be a variable that the program supplies during execution.
 112 Only the low order 5 bits of CL are used.
 113 <P>
 114 CF always contains the value of the last bit shifted out of the destination
 115 operand. In a single-bit shift, OF is set if the value of the high-order
 116 (sign) bit was changed by the operation. Otherwise, OF is cleared. Following
 117 a multibit shift, however, the content of OF is always undefined.
 118 <P>
 119 The shift instructions provide a convenient way to accomplish division or
 120 multiplication by binary power. Note however that division of signed numbers
 121 by shifting right is not the same kind of division performed by the
 122 <A HREF="IDIV.htm">IDIV</A> instruction.
 123 <P>
 124 <A HREF="SAL.htm">SAL</A> (Shift Arithmetic Left)
 125 shifts the destination byte, word, or
 126 doubleword operand left by one or by the number of bits specified in the
 127 count operand (an immediate value or the value contained in CL). The
 128 processor shifts zeros in from the right (low-order) side of the operand as
 129 bits exit from the left (high-order) side. See
 130 <A HREF="#fig3-6">Figure 3-6</A>.
 131 <P>
 132 <A HREF="SAL.htm">SHL</A> (Shift Logical Left)
 133 is a synonym for <A HREF="SAL.htm">SAL</A> (refer to <A HREF="SAL.htm">SAL</A>).
 134 <P>
 135 <A HREF="SAL.htm">SHR</A> (Shift Logical Right) shifts the destination byte,
 136 word, or doubleword
 137 operand right by one or by the number of bits specified in the count operand
 138 (an immediate value or the value contained in CL). The processor shifts
 139 zeros in from the left side of the operand as bits exit from the right side.
 140 See
 141 <A HREF="#fig3-7">Figure 3-7</A>.
 142 <P>
 143 <A HREF="SAL.htm">SAR</A> (Shift Arithmetic Right)
 144 shifts the destination byte, word, or
 145 doubleword operand to the right by one or by the number of bits specified in
 146 the count operand (an immediate value or the value contained in CL). The
 147 processor preserves the sign of the operand by shifting in zeros on the left
 148 (high-order) side if the value is positive or by shifting by ones if the
 149 value is negative. See
 150 <A HREF="#fig3-8">Figure 3-8</A>.
 151 <P>
 152 Even though this instruction can be used to divide integers by a power of
 153 two, the type of division is not the same as that produced by the
 154 <A HREF="IDIV.htm">IDIV</A>
 155 instruction. The quotient of
 156 <A HREF="IDIV.htm">IDIV</A> is rounded toward zero, whereas the
 157 "quotient" of
 158 <A HREF="SAL.htm">SAR</A> is rounded toward negative infinity.
 159 This difference is
 160 apparent only for negative numbers. For example, when
 161 <A HREF="IDIV.htm">IDIV</A> is used to divide
 162 -9 by 4, the result is -2 with a remainder of -1. If
 163 <A HREF="SAL.htm">SAR</A> is used to shift
 164 -9 right by two bits, the result is -3. The "remainder" of this kind of
 165 division is +3; however, the
 166 <A HREF="SAL.htm">SAR</A> instruction stores only the high-order bit
 167 of the remainder (in CF).
 168 <P>
 169 The code sequence in
 170 <A HREF="#fig3-9">Figure 3-9</A>
 171   produces the same result as
 172 <A HREF="IDIV.htm">IDIV</A> for any M = 2^(N), where 0 < N < 32.
 173 This sequence takes about 12 to 18 clocks,
 174 depending on whether the jump is taken; if ECX contains M, the corresponding
 175 <A HREF="IDIV.htm">IDIV</A> ECX instruction will take about 43 clocks.
 176 <P>
 177 <A NAME="fig3-6">
 178 <IMG align=center SRC="fig3-6.gif" border=0>
 179 <P>
 180 <HR>
 181 <P>
 182 <A NAME="fig3-7">
 183 <IMG align=center SRC="fig3-7.gif" border=0>
 184 <P>
 185 <HR>
 186 <P>
 187 <A NAME="fig3-8">
 188 <IMG align=center SRC="fig3-8.gif" border=0>
 189 <P>
 190 <HR>
 191 <P>
 192 <A NAME="fig3-9">
 193 <IMG align=center SRC="fig3-9.gif" border=0>
 194 <P>
 195 <H3>3.4.4.2  Double-Shift Instructions</H3>
 196 These instructions provide the basic operations needed to implement
 197 operations on long unaligned bit strings. The double shifts operate either
 198 on word or doubleword operands, as follows:
 199 <OL>
 200 <LI>Taking two word operands as input and producing a one-word output.
 201 <LI>Taking two doubleword operands as input and producing a doubleword
 202 output.
 203 </OL>
 204 Of the two input operands, one may either be in a general register or in
 205 memory, while the other may only be in a general register. The results
 206 replace the memory or register operand. The number of bits to be shifted is
 207 specified either in the CL register or in an immediate byte of the
 208 instruction.
 209 <P>
 210 Bits are shifted from the register operand into the memory or register
 211 operand. CF is set to the value of the last bit shifted out of the
 212 destination operand. SF, ZF, and PF are set according to the value of the
 213 result. OF and AF are left undefined.
 214 <P>
 215 <A HREF="SHLD.htm">SHLD</A> (Shift Left Double)
 216 shifts bits of the R/M field to the left, while
 217 shifting high-order bits from the Reg field into the R/M field on the right
 218 (see
 219 <A HREF="#fig3-10">Figure 3-10</A>).
 220 The result is stored back into the R/M operand. The Reg
 221 field is not modified.
 222 <P>
 223 <A HREF="SHRD.htm">SHRD</A> (Shift Right Double)
 224 shifts bits of the R/M field to the right, while
 225 shifting low-order bits from the Reg field into the R/M field on the left
 226 (see
 227 <A HREF="#fig3-11">Figure 3-11</A>).
 228 The result is stored back into the R/M operand. The Reg
 229 field is not modified.
 230
 231 <H3>3.4.4.3  Rotate Instructions</H3>
 232 Rotate instructions allow bits in bytes, words, and doublewords to be
 233 rotated. Bits rotated out of an operand are not lost as in a shift, but are
 234 "circled" back into the other "end" of the operand.
 235 <P>
 236 Rotates affect only the carry and overflow flags. CF may act as an
 237 extension of the operand in two of the rotate instructions, allowing a bit
 238 to be isolated and then tested by a conditional jump instruction (<A HREF="Jcc.htm">JC</A> or
 239 <A HREF="Jcc.htm">JNC</A>).
 240 CF always contains the value of the last bit rotated out, even if the
 241 instruction does not use this bit as an extension of the rotated operand.
 242 <P>
 243 In single-bit rotates, OF is set if the operation changes the high-order
 244 (sign) bit of the destination operand. If the sign bit retains its original
 245 value, OF is cleared. On multibit rotates, the value of OF is always
 246 undefined.
 247 <P>
 248 <A HREF="RCL.htm">ROL</A> (Rotate Left)
 249 rotates the byte, word, or doubleword destination operand
 250 left by one or by the number of bits specified in the count operand (an
 251 immediate value or the value contained in CL). For each rotation specified,
 252 the high-order bit that exits from the left of the operand returns at the
 253 right to become the new low-order bit of the operand. See
 254 <A HREF="#fig3-12">Figure 3-12</A>.
 255 <P>
 256 <A HREF="RCL.htm">ROR</A> (Rotate Right)
 257 rotates the byte, word, or doubleword destination
 258 operand right by one or by the number of bits specified in the count operand
 259 (an immediate value or the value contained in CL). For each rotation
 260 specified, the low-order bit that exits from the right of the operand
 261 returns at the left to become the new high-order bit of the operand.
 262 See
 263 <A HREF="#fig3-13">Figure 3-13</A>.
 264 <P>
 265 <A HREF="RCL.htm">RCL</A> (Rotate Through Carry Left)
 266 rotates bits in the byte, word, or
 267 doubleword destination operand left by one or by the number of bits
 268 specified in the count operand (an immediate value or the value contained in
 269 CL).
 270 <P>
 271 This instruction differs from
 272 <A HREF="RCL.htm">ROL</A> in that it treats CF as a high-order
 273 one-bit extension of the destination operand. Each high-order bit that exits
 274 from the left side of the operand moves to CF before it returns to the
 275 operand as the low-order bit on the next rotation cycle. See
 276 <A HREF="#fig3-14">Figure 3-14</A>
 277   .
 278 <P>
 279 <A HREF="RCL.htm">RCR</A> (Rotate Through Carry Right)
 280 rotates bits in the byte, word, or
 281 doubleword destination operand right by one or by the number of bits
 282 specified in the count operand (an immediate value or the value contained in
 283 CL).
 284 <P>
 285 This instruction differs from <A HREF="RCL.htm">ROR</A> in that it treats CF as a low-order
 286 one-bit extension of the destination operand. Each low-order bit that exits
 287 from the right side of the operand moves to CF before it returns to the
 288 operand as the high-order bit on the next rotation cycle. See
 289 <A HREF="#fig3-15">Figure 3-15</A>
 290   .
 291 <P>
 292 <A NAME="fig3-10">
 293 <IMG align=center SRC="fig3-10.gif" border=0>
 294 <P>
 295 <HR>
 296 <P>
 297 <A NAME="fig3-11">
 298 <IMG align=center SRC="fig3-11.gif" border=0>
 299 <P>
 300 <HR>
 301 <P>
 302 <A NAME="fig3-12">
 303 <IMG align=center SRC="fig3-12.gif" border=0>
 304 <P>
 305 <HR>
 306 <P>
 307 <A NAME="fig3-13">
 308 <IMG align=center SRC="fig3-13.gif" border=0>
 309 <P>
 310 <HR>
 311 <P>
 312 <A NAME="fig3-14">
 313 <IMG align=center SRC="fig3-14.gif" border=0>
 314 <P>
 315 <HR>
 316 <P>
 317 <A NAME="fig3-15">
 318 <IMG align=center SRC="fig3-15.gif" border=0>
 319 <P>
 320 <H3>3.4.4.4  Fast "BIT BLT" Using Double Shift Instructions</H3>
 321 One purpose of the double shifts is to implement a bit string move, with
 322 arbitrary misalignment of the bit strings.  This is called a "bit blt" (BIT
 323 BLock Transfer.)  A simple example is to move a bit string from an arbitrary
 324 offset into a doubleword-aligned byte string.  A left-to-right string is
 325 moved 32 bits at a time if a double shift is used inside the move loop.
 326 <PRE>
 327 MOV   ESI,ScrAddr
 328 MOV   EDI,DestAddr
 329 MOV   EBX,WordCnt
 330 MOV   CL,RelOffset      ; relative offset Dest-Src
 331 MOV   EDX,[ESI]         ; load first word of source
 332 ADD   ESI,4             ; bump source address
 333 BltLoop:
 334 LODS                    ; new low order part
 335 SHLD  EDX,EAX,CL        ; EDX overwritten with aligned stuff
 336 XCHG  EDX,EAS           ; Swap high/low order parts
 337 STOS                    ; Write out next aligned chunk
 338 DEC   EBX
 339 JA    BltLoop
 340 </PRE>
 341 This loop is simple yet allows the data to be moved in 32-bit pieces for
 342 the highest possible performance. Without a double shift, the best that can
 343 be achieved is 16 bits per loop iteration by using a 32-bit shift and
 344 replacing the
 345 <A HREF="XCHG.htm">XCHG</A> with a
 346 <A HREF="RCL.htm">ROR</A> by 16 to swap high and low order parts of
 347 registers. A more general loop than shown above would require some extra
 348 masking on the first doubleword moved (before the main loop), and on the
 349 last doubleword moved (after the main loop), but would have the same basic
 350 32-bits per loop iteration as the code above.
 351
 352 <H3>3.4.4.5  Fast Bit-String Insert and Extract</H3>
 353 The double shift instructions also enable:
 354 <UL>
 355 <LI> Fast insertion of a bit string from a register into an arbitrary bit
 356 location in a larger bit string in memory without disturbing the bits
 357 on either side of the inserted bits.
 358 <LI> Fast extraction of a bits string into a register from an arbitrary bit
 359 location in a larger bit string in memory without disturbing the bits
 360 on either side of the extracted bits.
 361 </UL>
 362 The following coded examples illustrate bit insertion and extraction under
 363 variousconditions:
 364 <OL>
 365 <LI>Bit String Insert into Memory (when bit string is 1-25 bits long,
 366 i.e., spans four bytes or less):
 367 <PRE>
 368 ; Insert a right-justified bit string from register into
 369 ; memory bit string.
 370 ;
 371 ; Assumptions:
 372 ; 1) The base of the string array is dword aligned, and
 373 ; 2) the length of the bit string is an immediate value
 374 ;    but the bit offset is held in a register.
 375 ;
 376 ; Register ESI holds the right-justified bit string
 377 ; to be inserted.
 378 ; Register EDI holds the bit offset of the start of the
 379 ; substring.
 380 ; Registers EAX and ECX are also used by this
 381 ; "insert" operation.
 382 ;
 383 MOV   ECX,EDI      ; preserve original offset for later use
 384 SHR   EDI,3        ; signed divide offset by 8 (byte address)
 385 AND   CL,7H        ; isolate low three bits of offset in CL
 386 MOV   EAX,[EDI]strg_base      ; move string dword into EAX
 387 ROR   EAX,CL       ; right justify old bit field
 388 SHRD  EAX,ESI,length          ; bring in new bits
 389 ROL   EAX,length   ; right justify new bit field
 390 ROL   EAX,CL       ; bring to final position
 391 MOV   [EDI]strg_base,EAX      ; replace dword in memory
 392 </PRE>
 393 <LI>Bit String Insert into Memory (when bit string is 1-31 bits long, i.e.
 394 spans five bytes or less):
 395 <PRE>
 396 ; Insert a right-justified bit string from register into
 397 ; memory bit string.
 398 ;
 399 ; Assumptions:
 400 ; 1) The base of the string array is dword aligned, and
 401 ; 2) the length of the bit string is an immediate value
 402 ;    but the bit offset is held in a register.
 403 ;
 404 ; Register ESI holds the right-justified bit string
 405 ; to be inserted.
 406 ; Register EDI holds the bit offset of the start of the
 407 ; substring.
 408 ; Registers EAX, EBX, ECX, and EDI are also used by
 409 ; this "insert" operation.
 410 ;
 411 MOV   ECX,EDI     ; temp storage for offset
 412 SHR   EDI,5       ; signed divide offset by 32 (dword address)
 413 SHL   EDI,2       ; multiply by 4 (in byte address format)
 414 AND   CL,1FH      ; isolate low five bits of offset in CL
 415 MOV   EAX,[EDI]strg_base      ; move low string dword into EAX
 416 MOV   EDX,[EDI]strg_base+4    ; other string dword into EDX
 417 MOV   EBX,EAX     ; temp storage for part of string     + rotate
 418 SHRD  EAX,EDX,CL  ; double shift by offset within dword + EDX:EAX
 419 SHRD  EAX,EBX,CL  ; double shift by offset within dword + right
 420 SHRD  EAX,ESI,length          ; bring in new bits
 421 ROL   EAX,length  ; right justify new bit field
 422 MOV   EBX,EAX     ; temp storage for part of string         + rotate
 423 SHLD  EAX,EDX,CL  ; double shift back by offset within word + EDX:EAX
 424 SHLD  EDX,EBX,CL  ; double shift back by offset within word + left
 425 MOV   [EDI]strg_base,EAX      ; replace dword in memory
 426 MOV   [EDI]strg_base+4,EDX    ; replace dword in memory
 427 </PRE>
 428 <LI>Bit String Insert into Memory (when bit string is exactly 32 bits
 429 long, i.e., spans five or four types of memory):
 430 <PRE>
 431 ; Insert right-justified bit string from register into
 432 ; memory bit string.
 433 ;
 434 ; Assumptions:
 435 ; 1) The base of the string array is dword aligned, and
 436 ; 2) the length of the bit string is 32
 437 ;    but the bit offset is held in a register.
 438 ;
 439 ; Register ESI holds the 32-bit string to be inserted.
 440 ; Register EDI holds the bit offset of the start of the
 441 ; substring.
 442 ; Registers EAX, EBX, ECX, and EDI are also used by
 443 ; this "insert" operation.
 444 ;
 445 MOV   EDX,EDI     ; preserve original offset for later use
 446 SHR   EDI,5       ; signed divide offset by 32 (dword address)
 447 SHL   EDI,2       ; multiply by 4 (in byte address format)
 448 AND   CL,1FH      ; isolate low five bits of offset in CL
 449 MOV   EAX,[EDI]strg_base      ; move low string dword into EAX
 450 MOV   EDX,[EDI]strg_base+4    ; other string dword into EDX
 451 MOV   EBX,EAX     ; temp storage for part of string     + rotate
 452 SHRD  EAX,EDX     ; double shift by offset within dword + EDX:EAX
 453 SHRD  EDX,EBX     ; double shift by offset within dword + right
 454 MOV   EAX,ESI     ; move 32-bit bit field into position
 455 MOV   EBX,EAX     ; temp storage for part of string         + rotate
 456 SHLD  EAX,EDX     ; double shift back by offset within word + EDX:EAX
 457 SHLD  EDX,EBX     ; double shift back by offset within word + left
 458 MOV   [EDI]strg_base,EAX      ; replace dword in memory
 459 MOV   [EDI]strg_base,+4,EDX   ; replace dword in memory
 460 </PRE>
 461 <LI>Bit String Extract from Memory (when bit string is 1-25 bits long,
 462 i.e., spans four bytes or less):
 463 <PRE>
 464 ; Extract a right-justified bit string from memory bit
 465 ; string into register
 466 ;
 467 ; Assumptions:
 468 ; 1) The base of the string array is dword aligned, and
 469 ; 2) the length of the bit string is an immediate value
 470 ;    but the bit offset is held in a register.
 471 ;
 472 ; Register EAX holds the right-justified, zero-padded
 473 ; bit string that was extracted.
 474 ; Register EDI holds the bit offset of the start of the
 475 ; substring.
 476 ; Registers EDI, and ECX are also used by this "extract."
 477 ;
 478 MOV  ECX,EDI      ; temp storage for offset
 479 SHR  EDI,3        ; signed divide offset by 8 (byte address)
 480 AND  CL,7H        ; isolate low three bits of offset
 481 MOV  EAX,[EDI]strg_base       ; move string dword into EAX
 482 SHR  EAX,CL       ; shift by offset within dword
 483 AND  EAX,mask     ; extracted bit field in EAX
 484 </PRE>
 485 <LI>Bit String Extract from Memory (when bit string is 1-32 bits long,
 486 i.e., spans five bytes or less):
 487 <PRE>
 488 ; Extract a right-justified bit string from memory bit
 489 ; string into register.
 490 ;
 491 ; Assumptions:
 492 ; 1) The base of the string array is dword aligned, and
 493 ; 2) the length of the bit string is an immediate
 494 ;    value but the bit offset is held in a register.
 495 ;
 496 ; Register EAX holds the right-justified, zero-padded
 497 ; bit string that was extracted.
 498 ; Register EDI holds the bit offset of the start of the
 499 ; substring.
 500 ; Registers EAX, EBX, and ECX are also used by this "extract."
 501 MOV   ECX,EDI     ; temp storage for offset
 502 SHR   EDI,5       ; signed divide offset by 32 (dword address)
 503 SHL   EDI,2       ; multiply by 4 (in byte address format)
 504 AND   CL,1FH      ; isolate low five bits of offset in CL
 505 MOV   EAX,[EDI]strg_base      ; move low string dword into EAX
 506 MOV   EDX,[EDI]strg_base+4    ; other string dword into EDX
 507 SHRD  EAX,EDX,CL  ; double shift right by offset within dword
 508 AND   EAX,mask    ; extracted bit field in EAX
 509 </PRE>
 510 </OL>
 511
 512 <H2>3.4.5  Byte-Set-On-Condition Instructions</H2>
 513 This group of instructions sets a byte to zero or one depending on any of
 514 the 16 conditions defined by the status flags. The byte may be in memory or
 515 may be a one-byte general register. These instructions are especially useful
 516 for implementing Boolean expressions in high-level languages such as Pascal.
 517 <P>
 518 <A HREF="SETcc.htm">SETcc</A> (Set Byte on Condition cc)
 519 set a byte to one if condition cc is true;
 520 sets the byte to zero otherwise. Refer to Appendix D for a definition of
 521 the possible conditions.
 522
 523 <H2>3.4.6  Test Instruction</H2>
 524 <A HREF="TEST.htm">TEST</A> (Test)
 525 performs the logical "and" of the two operands, clears OF and
 526 CF, leaves AF undefined, and updates SF, ZF, and PF. The flags can be tested
 527 by conditional control transfer instructions or by the byte-set-on-condition
 528 instructions. The operands may be doublewords, words, or bytes.
 529 <P>
 530 The difference between
 531 <A HREF="TEST.htm">TEST</A> and
 532 <A HREF="AND.htm">AND</A> is that <A HREF="TEST.htm">TEST</A>
 533 does not alter the destination operand.
 534 <A HREF="TEST.htm">TEST</A> differs from <A HREF="BT.htm">BT</A> in that
 535 <A HREF="TEST.htm">TEST</A> is useful for testing
 536 the value of multiple bits in one operations, whereas
 537 <A HREF="BT.htm">BT</A> tests a single bit.
 538 <P>
 539 <HR>
 540 <P>
 541 <B>up:</B> <A HREF="c03.htm">
 542 Chapter 3 -- Applications Instruction Set</A><BR>
 543 <B>prev:</B> <A HREF="s03_03.htm">3.3  Decimal Arithmetic Instructions</A><BR>
 544 <B>next:</B> <A HREF="s03_05.htm">3.5  Control Transfer Instructions</A>
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