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15 The 80386 contains a total of sixteen registers that are of interest to the
16 applications programmer. As
18 shows, these registers may be
19 grouped into these basic categories:
20 <OL>
22 used primarily to contain operands for arithmetic and logical
23 operations.
24 <LI>Segment registers. These special-purpose registers permit systems
25 software designers to choose either a flat or segmented model of
26 memory organization. These six registers determine, at any given time,
27 which segments of memory are currently addressable.
28 <LI>Status and instruction registers. These special-purpose registers are
29 used to record and alter certain aspects of the 80386 processor state.
30 </OL>
34 EDX, EBP, ESP, ESI, and EDI. These registers are used interchangeably to
35 contain the operands of logical and arithmetic operations. They may also be
36 used interchangeably for operands of address computations (except that ESP
37 cannot be used as an index operand).
38 <P>
39 As
41 shows, the low-order word of each of these eight registers
42 has a separate name and can be treated as a unit. This feature is useful for
44 processors. The word registers are named AX, BX, CX, DX, BP, SP, SI, and DI.
45 <P>
48 also illustrates that each byte of the 16-bit registers AX, BX,
49 CX, and DX has a separate name and can be treated as a unit. This feature is
50 useful for handling characters and other 8-bit data items. The byte
51 registers are named AH, BH, CH, and DH (high bytes); and AL, BL, CL, and DL
52 (low bytes).
53 <P>
54 All of the general-purpose registers are available for addressing
55 calculations and for the results of most arithmetic and logical
56 calculations; however, a few functions are dedicated to certain registers.
57 By implicitly choosing registers for these functions, the 80386 architecture
58 can encode instructions more compactly. The instructions that use specific
59 registers include: double-precision multiply and divide, I/O, string
60 instructions, translate, loop, variable shift and rotate, and stack
61 operations.
64 The segment registers of the 80386 give systems software designers the
65 flexibility to choose among various models of memory organization.
66 Implementation of memory models is the subject of Part II -- Systems
67 Programming. Designers may choose a model in which applications programs do
68 not need to modify segment registers, in which case applications programmers
69 may skip this section.
70 <P>
71 Complete programs generally consist of many different modules, each
72 consisting of instructions and data. However, at any given time during
73 program execution, only a small subset of a program's modules are actually
74 in use. The 80386 architecture takes advantage of this by providing
75 mechanisms to support direct access to the instructions and data of the
76 current module's environment, with access to additional segments on demand.
77 <P>
78 At any given instant, six segments of memory may be immediately accessible
79 to an executing 80386 program. The segment registers CS, DS, SS, ES, FS, and
80 GS are used to identify these six current segments. Each of these registers
81 specifies a particular kind of segment, as characterized by the associated
84 . Each register
85 uniquely determines one particular segment, from among the segments that
86 make up the program, that is to be immediately accessible at highest speed.
87 <P>
88 The segment containing the currently executing sequence of instructions is
89 known as the current code segment; it is specified by means of the CS
90 register. The 80386 fetches all instructions from this code segment, using
91 as an offset the contents of the instruction pointer. CS is changed
92 implicitly as the result of intersegment control-transfer instructions (for
95 <P>
96 Subroutine calls, parameters, and procedure activation records usually
97 require that a region of memory be allocated for a stack. All stack
98 operations use the SS register to locate the stack. Unlike CS, the SS
99 register can be loaded explicitly, thereby permitting programmers to define
100 stacks dynamically.
101 <P>
102 The DS, ES, FS, and GS registers allow the specification of four data
103 segments, each addressable by the currently executing program. Accessibility
104 to four separate data areas helps programs efficiently access different
105 types of data structures; for example, one data segment register can point
106 to the data structures of the current module, another to the exported data
107 of a higher-level module, another to a dynamically created data structure,
108 and another to data shared with another task. An operand within a data
109 segment is addressed by specifying its offset either directly in an
110 instruction or indirectly via general registers.
111 <P>
112 Depending on the structure of data (e.g., the way data is parceled into one
113 or more segments), a program may require access to more than four data
114 segments. To access additional segments, the DS, ES, FS, and GS registers
115 can be changed under program control during the course of a program's
116 execution. This simply requires that the program execute an instruction to
117 load the appropriate segment register prior to executing instructions that
118 access the data.
119 <P>
120 The processor associates a base address with each segment selected by a
121 segment register. To address an element within a segment, a 32-bit offset is
122 added to the segment's base address. Once a segment is selected (by loading
123 the segment selector into a segment register), a data manipulation
124 instruction only needs to specify the offset. Simple rules define which
125 segment register is used to form an address when only an offset is
126 specified.
127 <P>
130 <P>
131 <HR>
132 <P>
135 <P>
137 Stack operations are facilitated by three registers:
138 <OL>
139 <LI>The stack segment (SS) register. Stacks are implemented in memory. A
140 system may have a number of stacks that is limited only by the maximum
141 number of segments. A stack may be up to 4 gigabytes long, the maximum
142 length of a segment. One stack is directly addressable at a --
143 one located by SS. This is the current stack, often referred to simply
144 as "the" stack. SS is used automatically by the processor for all
145 stack operations.
147 <LI>The stack pointer (ESP) register. ESP points to the top of the
148 push-down stack (TOS). It is referenced implicitly by <A HREF="PUSH.htm">PUSH</A> and <A HREF="POP.html">POP</A>
149 operations, subroutine calls and returns, and interrupt operations.
150 When an item is pushed onto the stack (see
152 ), the processor
153 decrements ESP, then writes the item at the new TOS. When an item is
154 popped off the stack, the processor copies it from TOS, then
155 increments ESP. In other words, the stack grows down in memory toward
156 lesser addresses.
158 <LI>The stack-frame base pointer (EBP) register. The EBP is the best
159 choice of register for accessing data structures, variables and
160 dynamically allocated work space within the stack. EBP is often used
161 to access elements on the stack relative to a fixed point on the stack
162 rather than relative to the current TOS. It typically identifies the
163 base address of the current stack frame established for the current
164 procedure. When EBP is used as the base register in an offset
165 calculation, the offset is calculated automatically in the current
166 stack segment (i.e., the segment currently selected by SS). Because
167 SS does not have to be explicitly specified, instruction encoding in
168 such cases is more efficient. EBP can also be used to index into
169 segments addressable via other segment registers.
170 </OL>
171 <P>
174 <P>
176 The flags register is a 32-bit register named EFLAGS.
178 defines
179 the bits within this register. The flags control certain operations and
180 indicate the status of the 80386.
181 <P>
182 The low-order 16 bits of EFLAGS is named FLAGS and can be treated as a
184 this part of EFLAGS is identical to the FLAGS register of the 8086 and the
185 80286.
186 <P>
187 The flags may be considered in three groups: the status flags, the control
188 flags, and the systems flags. Discussion of the systems flags is delayed
189 until Part II.
190 <P>
193 <P>
195 The status flags of the EFLAGS register allow the results of one
196 instruction to influence later instructions. The arithmetic instructions use
197 OF, SF, ZF, AF, PF, and CF. The SCAS (Scan String), <A HREF="CMPS.htm">CMPS</A> (Compare String),
198 and <A HREF="LOOP.htm">LOOP</A> instructions use ZF to signal that their operations are complete.
199 There are instructions to set, clear, and complement CF before execution of
201 status flag.
204 The control flag DF of the EFLAGS register controls string instructions.
206 DF (Direction Flag, bit 10)
208 Setting DF causes string instructions to auto-decrement; that is, to
209 process strings from high addresses to low addresses. Clearing DF causes
210 string instructions to auto-increment, or to process strings from low
211 addresses to high addresses.
214 The instruction pointer register (EIP) contains the offset address,
215 relative to the start of the current code segment, of the next sequential
216 instruction to be executed. The instruction pointer is not directly visible
217 to the programmer; it is controlled implicitly by control-transfer
218 instructions, interrupts, and exceptions.
219 <P>
220 As
222 shows, the low-order 16 bits of EIP is named IP and can be
223 used by the processor as a unit. This feature is useful when executing
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