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4 <TITLE>80386 Programmer's Reference Manual -- Opcode VERR</TITLE>
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6 <BODY>
7 <B>up:</B> <A HREF="c17.htm">
8 Chapter 17 -- 80386 Instruction Set</A><BR>
9 <B>prev:</B><A HREF="TEST.htm"> TEST Logical Compare</A><BR>
10 <B>next:</B><A HREF="WAIT.htm"> WAIT Wait until BUSY# Pin is Inactive (HIGH)</A>
11 <P>
12 <HR>
13 <P>
14 <H1>VERR, VERW -- Verify a Segment for Reading or Writing</H1>
16 <PRE>
17 Opcode Instruction Clocks Description
19 0F 00 /4 VERR r/m16 pm=10/11 Set ZF=1 if segment can be read,
20 selector in r/m16
21 0F 00 /5 VERW r/m16 pm=15/16 Set ZF=1 if segment can be written,
22 selector in r/m16
23 </PRE>
26 <H2>Operation</H2>
28 <PRE>
29 IF segment with selector at (r/m) is accessible
30 with current protection level
31 AND ((segment is readable for VERR) OR
32 (segment is writable for VERW))
33 THEN ZF := 0;
34 ELSE ZF := 1;
35 FI;
36 </PRE>
38 <H2>Description</H2>
40 The two-byte register or memory operand of VERR and VERW contains
41 the value of a selector. VERR and VERW determine whether the
42 segment denoted by the selector is reachable from the current privilege
43 level and whether the segment is readable (VERR) or writable (VERW).
44 If the segment is accessible, the zero flag is set to 1; if the segment is
45 not accessible, the zero flag is set to 0. To set ZF, the following
46 conditions must be met:
47 <UL>
48 <LI> The selector must denote a descriptor within the bounds of the table
49 (GDT or LDT); the selector must be "defined."
51 <LI> The selector must denote the descriptor of a code or data segment
52 (not that of a task state segment, LDT, or a gate).
54 <LI> For VERR, the segment must be readable. For VERW, the segment
55 must be a writable data segment.
57 <LI> If the code segment is readable and conforming, the descriptor
58 privilege level (DPL) can be any value for VERR. Otherwise, the
59 DPL must be greater than or equal to (have less or the same
60 privilege as) both the current privilege level and the selector's RPL.
61 </UL>
63 The validation performed is the same as if the segment were loaded into
64 DS, ES, FS, or GS, and the indicated access (read or write) were
65 performed. The zero flag receives the result of the validation. The
66 selector's value cannot result in a protection exception, enabling the
67 software to anticipate possible segment access problems.
69 <H2>Flags Affected</H2>
71 ZF as described above
73 <H2>Protected Mode Exceptions</H2>
75 Faults generated by illegal addressing of the memory operand that
76 contains the selector, the selector is not loaded into any segment
77 register, and no faults attributable to the selector operand are generated
78 <P>
79 #GP(0) for an illegal memory operand effective address in the CS, DS,
80 ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment;
81 #PF(fault-code) for a page fault
83 <H2>Real Address Mode Exceptions</H2>
85 Interrupt 6; VERR and VERW are not recognized in Real Address Mode
87 <H2>Virtual 8086 Mode Exceptions</H2>
89 Same exceptions as in Real Address Mode; #PF(fault-code) for a page
90 fault
93 <P>
94 <HR>
95 <P>
96 <B>up:</B> <A HREF="c17.htm">
97 Chapter 17 -- 80386 Instruction Set</A><BR>
98 <B>prev:</B><A HREF="TEST.htm"> TEST Logical Compare</A><BR>
99 <B>next:</B><A HREF="WAIT.htm"> WAIT Wait until BUSY# Pin is Inactive (HIGH)</A>
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