i386/i386.reference/LOCK.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Opcode LOCK</TITLE>
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   8 Chapter 17 -- 80386 Instruction Set</A><BR>
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  13 <P>
  14 <H1>LOCK -- Assert LOCK# Signal Prefix</H1>
  15
  16 <PRE>
  17 Opcode  Instruction  Clocks  Description
  18
  19 F0      LOCK         0       Assert LOCK# signal for the next instruction
  20 </PRE>
  21
  22 <H2>Description</H2>
  23
  24 The LOCK prefix causes the LOCK# signal of the 80386 to be asserted
  25 during execution of the instruction that follows it. In a multiprocessor
  26 environment, this signal can be used to ensure that the 80386 has
  27 exclusive use of any shared memory while LOCK# is asserted. The
  28 read-modify-write sequence typically used to implement test-and-set on the
  29 80386 is the
  30 <A HREF="BTS.htm">BTS</A> instruction.
  31 <P>
  32 The LOCK prefix functions only with the following instructions:
  33
  34 <PRE>
  35 <A HREF="BT.htm">BT</A>, <A HREF="BTS.htm">BTS</A>, <A HREF="BTR.htm">BTR</A>, <A HREF="BTC.htm">BTC</A>                   mem, reg/imm
  36 <A HREF="XCHG.htm">XCHG</A>                                reg, mem
  37 <A HREF="XCHG.htm">XCHG</A>                                mem, reg
  38 <A HREF="ADD.htm">ADD</A>, <A HREF="OR.htm">OR</A>, <A HREF="ADC.htm">ADC</A>, <A HREF="SBB.htm">SBB</A>, <A HREF="AND.htm">AND</A>, <A HREF="SUB.htm">SUB</A>, <A HREF="XOR.htm">XOR</A>    mem, reg/imm
  39 <A HREF="NOT.htm">NOT</A>, <A HREF="NEG.htm">NEG</A>, <A HREF="INC.htm">INC</A>, <A HREF="DEC.htm">DEC</A>                  mem
  40 </PRE>
  41
  42 An undefined opcode trap will be generated if a LOCK prefix is used
  43 with any instruction not listed above.
  44 <P>
  45 <A HREF="XCHG.htm">XCHG</A> always asserts LOCK# regardless of the presence or absence of
  46 the LOCK prefix.
  47 <P>
  48 The integrity of the LOCK is not affected by the alignment of the
  49 memory field. Memory locking is observed for arbitrarily misaligned
  50 fields.
  51 <P>
  52 Locked access is not assured if another 80386 processor is executing an
  53 instruction concurrently that has one of the following characteristics:
  54 <UL>
  55  <LI> Is not preceded by a LOCK prefix
  56
  57  <LI> Is not one of the instructions in the preceding list
  58
  59  <LI> Specifies a memory operand that does not exactly overlap the
  60      destination operand. Locking is not guaranteed for partial overlap,
  61      even if one memory operand is wholly contained within another.
  62 </UL>
  63
  64 <H2>Flags Affected</H2>
  65
  66 None
  67
  68 <H2>Protected Mode Exceptions</H2>
  69
  70 #UD if LOCK is used with an instruction not listed in the "Description"
  71 section above; other exceptions can be generated by the subsequent
  72 (locked) instruction
  73
  74 <H2>Real Address Mode Exceptions</H2>
  75
  76 Interrupt 6 if LOCK is used with an instruction not listed in the
  77 "Description" section above; exceptions can still be generated by the
  78 subsequent (locked) instruction
  79
  80 <H2>Virtual 8086 Mode Exceptions</H2>
  81
  82 #UD if LOCK is used with an instruction not listed in the "Description"
  83 section above; exceptions can still be generated by the subsequent (locked)
  84 instruction
  85 <P>
  86 <HR>
  87 <P>
  88 <B>up:</B> <A HREF="c17.htm">
  89 Chapter 17 -- 80386 Instruction Set</A><BR>
  90 <B>prev:</B><A HREF="LMSW.htm"> LMSW Load Machine Status Word</A><BR>
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