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4 <TITLE>80386 Programmer's Reference Manual -- Opcode IMUL</TITLE>
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6 <BODY>
7 <B>up:</B> <A HREF="c17.htm">
8 Chapter 17 -- 80386 Instruction Set</A><BR>
9 <B>prev:</B><A HREF="IDIV.htm"> IDIV Signed Divide</A><BR>
10 <B>next:</B><A HREF="IN.htm"> IN Input from Port</A>
11 <P>
12 <HR>
13 <P>
14 <H1>IMUL -- Signed Multiply</H1>
17 <PRE>
18 Opcode Instruction Clocks Description
20 F6 /5 IMUL r/m8 9-14/12-17 AX= AL * r/m byte
21 F7 /5 IMUL r/m16 9-22/12-25 DX:AX := AX * r/m word
22 F7 /5 IMUL r/m32 9-38/12-41 EDX:EAX := EAX * r/m dword
23 0F AF /r IMUL r16,r/m16 9-22/12-25 word register := word
24 register * r/m word
25 0F AF /r IMUL r32,r/m32 9-38/12-41 dword register := dword
26 register * r/m dword
27 6B /r ib IMUL r16,r/m16,imm8 9-14/12-17 word register := r/m16 *
28 sign-extended immediate byte
29 6B /r ib IMUL r32,r/m32,imm8 9-14/12-17 dword register := r/m32 *
30 sign-extended immediate byte
31 6B /r ib IMUL r16,imm8 9-14/12-17 word register := word
32 register * sign-extended
33 immediate byte
34 6B /r ib IMUL r32,imm8 9-14/12-17 dword register := dword
35 register * sign-extended
36 immediate byte
37 69 /r iw IMUL r16,r/m16,imm16 9-22/12-25 word register := r/m16 *
38 immediate word
39 69 /r id IMUL r32,r/m32,imm32 9-38/12-41 dword register := r/m32 *
40 immediate dword
41 69 /r iw IMUL r16,imm16 9-22/12-25 word register := r/m16 *
42 immediate word
43 69 /r id IMUL r32,imm32 9-38/12-41 dword register := r/m32 *
44 immediate dword
45 </PRE>
47 <EM>
48 <H3>Notes</H3>
49 The 80386 uses an early-out multiply algorithm. The actual number of
50 clocks depends on the position of the most significant bit in the
51 optimizing multiplier, shown underlined above. The optimization occurs for
52 positive and negative values. Because of the early-out algorithm, clock
53 counts given are minimum to maximum. To calculate the actual clocks, use
54 the following formula:
56 <PRE>
57 Actual clock = if m <> 0 then max(ceiling(log{2}(m)), 3) + 6 clocks
58 Actual clock = if m = 0 then 9 clocks
59 (where m is the multiplier)
60 </PRE>
62 Add three clocks if the multiplier is a memory operand.
63 </EM>
65 <H2>Operation</H2>
67 <PRE>
68 result := multiplicand * multiplier;
69 </PRE>
71 <H2>Description</H2>
73 IMUL performs signed multiplication. Some forms of the instruction
74 use implicit register operands. The operand combinations for all forms
75 of the instruction are shown in the "<H2>Description</H2>" column above.
76 <P>
77 IMUL clears the overflow and carry flags under the following conditions:
78 <PRE>
79 Instruction Form Condition for Clearing CF and OF
80 r/m8 AL := sign-extend of AL to 16 bits
81 r/m16 AX := sign-extend of AX to 32 bits
82 r/m32 EDX:EAX := sign-extend of EAX to 32 bits
83 r16,r/m16 Result exactly fits within r16
84 r/32,r/m32 Result exactly fits within r32
85 r16,r/m16,imm16 Result exactly fits within r16
86 r32,r/m32,imm32 Result exactly fits within r32
87 </PRE>
89 <H2>Flags Affected</H2>
91 OF and CF as described above; SF, ZF, AF, and PF are undefined
93 <H2>Protected Mode Exceptions</H2>
95 #GP(0) for an illegal memory operand effective address in the CS, DS,
96 ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment;
97 #PF(fault-code) for a page fault
99 <H2>Real Address Mode Exceptions</H2>
101 Interrupt 13 if any part of the operand would lie outside of the effective
102 address space from 0 to 0FFFFH
104 <H2>Virtual 8086 Mode Exceptions</H2>
106 Same exeptions as in Real Address Mode; #PF(fault-code) for a page
107 fault
109 <H2>Notes</H2>
111 When using the accumulator forms (IMUL r/m8, IMUL r/m16, or IMUL
112 r/m32), the result of the multiplication is available even if the overflow
113 flag is set because the result is two times the size of the multiplicand
114 and multiplier. This is large enough to handle any possible result.
118 <HR>
120 <B>up:</B> <A HREF="c17.htm">
121 Chapter 17 -- 80386 Instruction Set</A><BR>
122 <B>prev:</B><A HREF="IDIV.htm"> IDIV Signed Divide</A><BR>
123 <B>next:</B><A HREF="IN.htm"> IN Input from Port</A>
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