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1 <!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
2 <HTML>
3 <HEAD>
4 <TITLE>80386 Programmer's Reference Manual -- Section 17.2</TITLE>
5 </HEAD>
6 <BODY>
7 <B>up:</B> <A HREF="c17.htm">
8 Chapter 17 -- 80386 Instruction Set</A><BR>
9 <B>prev:</B> <A HREF="s17_01.htm">
10 17.1 Operand Size and Address-Size Attributes</A><BR>
11 <B>next:</B> <A HREF="AAA.htm"> AAA ASCII Adjust after Addition</A>
12 <P>
13 <HR>
14 <P>
15 <H1>17.2 Instruction Format</H1>
16
17 All instruction encodings are subsets of the general instruction format
18 shown in
19 <A HREF="#fig17-1">Figure 17-1</A>
20 . Instructions consist of optional instruction
21 prefixes, one or two primary opcode bytes, possibly an address specifier
22 consisting of the ModR/M byte and the SIB (Scale Index Base) byte, a
23 displacement, if required, and an immediate data field, if required.
24 <P>
25 Smaller encoding fields can be defined within the primary opcode or
26 opcodes. These fields define the direction of the operation, the size of the
27 displacements, the register encoding, or sign extension; encoding fields
28 vary depending on the class of operation.
29 <P>
30 Most instructions that can refer to an operand in memory have an addressing
31 form byte following the primary opcode byte(s). This byte, called the ModR/M
32 byte, specifies the address form to be used. Certain encodings of the ModR/M
33 byte indicate a second addressing byte, the SIB (Scale Index Base) byte,
34 which follows the ModR/M byte and is required to fully specify the
35 addressing form.
36 <P>
37 Addressing forms can include a displacement immediately following either
38 the ModR/M or SIB byte. If a displacement is present, it can be 8-, 16- or
39 32-bits.
40 <P>
41 If the instruction specifies an immediate operand, the immediate operand
42 always follows any displacement bytes. The immediate operand, if specified,
43 is always the last field of the instruction.
44 <P>
45 The following are the allowable instruction prefix codes:
46
47 <PRE>
48 F3H <A HREF="REP.htm">REP</A> prefix (used only with string instructions)
49 F3H <A HREF="REP.htm">REPE/REPZ</A> prefix (used only with string instructions
50 F2H <A HREF="REP.htm">REPNE/REPNZ</A> prefix (used only with string instructions)
51 F0H <A HREF="LOCK.htm">LOCK</A> prefix
52 </PRE>
53
54 The following are the segment override prefixes:
55
56 <PRE>
57 2EH CS segment override prefix
58 36H SS segment override prefix
59 3EH DS segment override prefix
60 26H ES segment override prefix
61 64H FS segment override prefix
62 65H GS segment override prefix
63 66H Operand-size override
64 67H Address-size override
65 </PRE>
66
67 <A NAME="fig17-1">
68 <IMG align=center SRC="fig17-1.gif" border=0>
69
70
71 <H2>17.2.1 ModR/M and SIB Bytes</H2>
72
73 The ModR/M and SIB bytes follow the opcode byte(s) in many of the 80386
74 instructions. They contain the following information:
75
76 <UL>
77 <LI> The indexing type or register number to be used in the instruction
78 <LI> The register to be used, or more information to select the instruction
79 <LI> The base, index, and scale information
80 </UL>
81
82 The ModR/M byte contains three fields of information:
83
84 <UL>
85 <LI> The mod field, which occupies the two most significant bits of the
86 byte, combines with the r/m field to form 32 possible values: eight
87 registers and 24 indexing modes
88
89 <LI> The reg field, which occupies the next three bits following the mod
90 field, specifies either a register number or three more bits of opcode
91 information. The meaning of the reg field is determined by the first
92 (opcode) byte of the instruction.
93
94 <LI> The r/m field, which occupies the three least significant bits of the
95 byte, can specify a register as the location of an operand, or can form
96 part of the addressing-mode encoding in combination with the field as
97 described above
98 </UL>
99
100 The based indexed and scaled indexed forms of 32-bit addressing require the
101 SIB byte. The presence of the SIB byte is indicated by certain encodings of
102 the ModR/M byte. The SIB byte then includes the following fields:
103
104 <UL>
105 <LI> The ss field, which occupies the two most significant bits of the
106 byte, specifies the scale factor
107
108 <LI> The index field, which occupies the next three bits following the ss
109 field and specifies the register number of the index register
110
111 <LI> The base field, which occupies the three least significant bits of the
112 byte, specifies the register number of the base register
113 </UL>
114
115
116 <A HREF="#fig17-2">Figure 17-2</A>
117 shows the formats of the ModR/M and SIB bytes.
118
119 The values and the corresponding addressing forms of the ModR/M and SIB
120 bytes are shown in Tables 17-2, 17-3, and 17-4. The 16-bit addressing
121 forms specified by the ModR/M byte are in Table 17-2. The 32-bit addressing
122 forms specified by ModR/M are in Table 17-3. Table 17-4 shows the 32-bit
123 addressing forms specified by the SIB byte
124 <P>
125 <A NAME="fig17-2">
126 <IMG align=center SRC="fig17-2.gif" border=0>
127
128 <PRE>
129 Table 17-2. 16-Bit Addressing Forms with the ModR/M Byte
130
131
132 r8(/r) AL CL DL BL AH CH DH BH
133 r16(/r) AX CX DX BX SP BP SI DI
134 r32(/r) EAX ECX EDX EBX ESP EBP ESI EDI
135 /digit (Opcode) 0 1 2 3 4 5 6 7
136 REG = 000 001 010 011 100 101 110 111
137
138 Effective
139 +---Address--+ +Mod R/M+ +--------ModR/M Values in Hexadecimal--------+
140
141 [BX + SI] 000 00 08 10 18 20 28 30 38
142 [BX + DI] 001 01 09 11 19 21 29 31 39
143 [BP + SI] 010 02 0A 12 1A 22 2A 32 3A
144 [BP + DI] 011 03 0B 13 1B 23 2B 33 3B
145 [SI] 00 100 04 0C 14 1C 24 2C 34 3C
146 [DI] 101 05 0D 15 1D 25 2D 35 3D
147 disp16 110 06 0E 16 1E 26 2E 36 3E
148 [BX] 111 07 0F 17 1F 27 2F 37 3F
149
150 [BX+SI]+disp8 000 40 48 50 58 60 68 70 78
151 [BX+DI]+disp8 001 41 49 51 59 61 69 71 79
152 [BP+SI]+disp8 010 42 4A 52 5A 62 6A 72 7A
153 [BP+DI]+disp8 011 43 4B 53 5B 63 6B 73 7B
154 [SI]+disp8 01 100 44 4C 54 5C 64 6C 74 7C
155 [DI]+disp8 101 45 4D 55 5D 65 6D 75 7D
156 [BP]+disp8 110 46 4E 56 5E 66 6E 76 7E
157 [BX]+disp8 111 47 4F 57 5F 67 6F 77 7F
158
159 [BX+SI]+disp16 000 80 88 90 98 A0 A8 B0 B8
160 [BX+DI]+disp16 001 81 89 91 99 A1 A9 B1 B9
161 [BX+SI]+disp16 010 82 8A 92 9A A2 AA B2 BA
162 [BX+DI]+disp16 011 83 8B 93 9B A3 AB B3 BB
163 [SI]+disp16 10 100 84 8C 94 9C A4 AC B4 BC
164 [DI]+disp16 101 85 8D 95 9D A5 AD B5 BD
165 [BP]+disp16 110 86 8E 96 9E A6 AE B6 BE
166 [BX]+disp16 111 87 8F 97 9F A7 AF B7 BF
167
168 EAX/AX/AL 000 C0 C8 D0 D8 E0 E8 F0 F8
169 ECX/CX/CL 001 C1 C9 D1 D9 E1 E9 F1 F9
170 EDX/DX/DL 010 C2 CA D2 DA E2 EA F2 FA
171 EBX/BX/BL 011 C3 CB D3 DB E3 EB F3 FB
172 ESP/SP/AH 11 100 C4 CC D4 DC E4 EC F4 FC
173 EBP/BP/CH 101 C5 CD D5 DD E5 ED F5 FD
174 ESI/SI/DH 110 C6 CE D6 DE E6 EE F6 FE
175 EDI/DI/BH 111 C7 CF D7 DF E7 EF F7 FF
176 </PRE>
177
178 <EM>
179 <H3>Notes</H3>
180 disp8 denotes an 8-bit displacement following the ModR/M byte, to be
181 sign-extended and added to the index. disp16 denotes a 16-bit displacement
182 following the ModR/M byte, to be added to the index. Default segment
183 register is SS for the effective addresses containing a BP index, DS for
184 other effective addresses.
185 </EM>
186
187 <PRE>
188 Table 17-3. 32-Bit Addressing Forms with the ModR/M Byte
189
190
191 r8(/r) AL CL DL BL AH CH DH BH
192 r16(/r) AX CX DX BX SP BP SI DI
193 r32(/r) EAX ECX EDX EBX ESP EBP ESI EDI
194 /digit (Opcode) 0 1 2 3 4 5 6 7
195 REG = 000 001 010 011 100 101 110 111
196
197 Effective
198 +---Address--+ +Mod R/M+ +---------ModR/M Values in Hexadecimal-------+
199
200 [EAX] 000 00 08 10 18 20 28 30 38
201 [ECX] 001 01 09 11 19 21 29 31 39
202 [EDX] 010 02 0A 12 1A 22 2A 32 3A
203 [EBX] 011 03 0B 13 1B 23 2B 33 3B
204 [--] [--] 00 100 04 0C 14 1C 24 2C 34 3C
205 disp32 101 05 0D 15 1D 25 2D 35 3D
206 [ESI] 110 06 0E 16 1E 26 2E 36 3E
207 [EDI] 111 07 0F 17 1F 27 2F 37 3F
208
209 disp8[EAX] 000 40 48 50 58 60 68 70 78
210 disp8[ECX] 001 41 49 51 59 61 69 71 79
211 disp8[EDX] 010 42 4A 52 5A 62 6A 72 7A
212 disp8[EPX]; 011 43 4B 53 5B 63 6B 73 7B
213 disp8[--] [--] 01 100 44 4C 54 5C 64 6C 74 7C
214 disp8[ebp] 101 45 4D 55 5D 65 6D 75 7D
215 disp8[ESI] 110 46 4E 56 5E 66 6E 76 7E
216 disp8[EDI] 111 47 4F 57 5F 67 6F 77 7F
217
218 disp32[EAX] 000 80 88 90 98 A0 A8 B0 B8
219 disp32[ECX] 001 81 89 91 99 A1 A9 B1 B9
220 disp32[EDX] 010 82 8A 92 9A A2 AA B2 BA
221 disp32[EBX] 011 83 8B 93 9B A3 AB B3 BB
222 disp32[--] [--] 10 100 84 8C 94 9C A4 AC B4 BC
223 disp32[EBP] 101 85 8D 95 9D A5 AD B5 BD
224 disp32[ESI] 110 86 8E 96 9E A6 AE B6 BE
225 disp32[EDI] 111 87 8F 97 9F A7 AF B7 BF
226
227 EAX/AX/AL 000 C0 C8 D0 D8 E0 E8 F0 F8
228 ECX/CX/CL 001 C1 C9 D1 D9 E1 E9 F1 F9
229 EDX/DX/DL 010 C2 CA D2 DA E2 EA F2 FA
230 EBX/BX/BL 011 C3 CB D3 DB E3 EB F3 FB
231 ESP/SP/AH 11 100 C4 CC D4 DC E4 EC F4 FC
232 EBP/BP/CH 101 C5 CD D5 DD E5 ED F5 FD
233 ESI/SI/DH 110 C6 CE D6 DE E6 EE F6 FE
234 EDI/DI/BH 111 C7 CF D7 DF E7 EF F7 FF
235 </PRE>
236
237 <EM>
238 <H3>Notes</H3>
239 [--] [--] means a SIB follows the ModR/M byte. disp8 denotes an 8-bit
240 displacement following the SIB byte, to be sign-extended and added to the
241 index. disp32 denotes a 32-bit displacement following the ModR/M byte, to
242 be added to the index.
243 </EM>
244
245 <PRE>
246 Table 17-4. 32-Bit Addressing Forms with the SIB Byte
247
248
249 r32 EAX ECX EDX EBX ESP [*]
250 Base = 0 1 2 3 4 5 6 7
251 Base = 000 001 010 011 100 101 110 111
252
253 +Scaled Index+ +SS Index+ +--------ModR/M Values in Hexadecimal--------+
254
255 [EAX] 000 00 01 02 03 04 05 06 07
256 [ECX] 001 08 09 0A 0B 0C 0D 0E 0F
257 [EDX] 010 10 11 12 13 14 15 16 17
258 [EBX] 011 18 19 1A 1B 1C 1D 1E 1F
259 none 00 100 20 21 22 23 24 25 26 27
260 [EBP] 101 28 29 2A 2B 2C 2D 2E 2F
261 [ESI] 110 30 31 32 33 34 35 36 37
262 [EDI] 111 38 39 3A 3B 3C 3D 3E 3F
263
264 [EAX*2] 000 40 41 42 43 44 45 46 47
265 [ECX*2] 001 48 49 4A 4B 4C 4D 4E 4F
266 [ECX*2] 010 50 51 52 53 54 55 56 57
267 [EBX*2] 011 58 59 5A 5B 5C 5D 5E 5F
268 none 01 100 60 61 62 63 64 65 66 67
269 [EBP*2] 101 68 69 6A 6B 6C 6D 6E 6F
270 [ESI*2] 110 70 71 72 73 74 75 76 77
271 [EDI*2] 111 78 79 7A 7B 7C 7D 7E 7F
272
273 [EAX*4] 000 80 81 82 83 84 85 86 87
274 [ECX*4] 001 88 89 8A 8B 8C 8D 8E 8F
275 [EDX*4] 010 90 91 92 93 94 95 96 97
276 [EBX*4] 011 98 89 9A 9B 9C 9D 9E 9F
277 none 10 100 A0 A1 A2 A3 A4 A5 A6 A7
278 [EBP*4] 101 A8 A9 AA AB AC AD AE AF
279 [ESI*4] 110 B0 B1 B2 B3 B4 B5 B6 B7
280 [EDI*4] 111 B8 B9 BA BB BC BD BE BF
281
282 [EAX*8] 000 C0 C1 C2 C3 C4 C5 C6 C7
283 [ECX*8] 001 C8 C9 CA CB CC CD CE CF
284 [EDX*8] 010 D0 D1 D2 D3 D4 D5 D6 D7
285 [EBX*8] 011 D8 D9 DA DB DC DD DE DF
286 none 11 100 E0 E1 E2 E3 E4 E5 E6 E7
287 [EBP*8] 101 E8 E9 EA EB EC ED EE EF
288 [ESI*8] 110 F0 F1 F2 F3 F4 F5 F6 F7
289 [EDI*8] 111 F8 F9 FA FB FC FD FE FF
290 </PRE>
291
292 <EM>
293 <H3>Notes</H3>
294 [*] means a disp32 with no base if MOD is 00, [ESP] otherwise. This
295 provides the following addressing modes:
296 <PRE>
297 disp32[index] (MOD=00)
298 disp8[EBP][index] (MOD=01)
299 disp32[EBP][index] (MOD=10)
300 </PRE>
301 </EM>
302
303 <H2>17.2.2 How to Read the Instruction Set Pages</H2>
304
305 The following is an example of the format used for each 80386 instruction
306 description in this chapter:
307
308 <EM>
309 <H3>CMC -- Complement Carry Flag</H3>
310
311 <PRE>
312 Opcode Instruction Clocks Description
313
314 F5 <A HREF="CMC.htm">CMC</A> 2 Complement carry flag
315 </PRE>
316 </EM>
317
318 The above table is followed by paragraphs labelled "Operation,"
319 "Description," "Flags Affected," "Protected Mode Exceptions," "Real
320 Address Mode Exceptions," and, optionally, "Notes." The following sections
321 explain the notational conventions and abbreviations used in these
322 paragraphs of the instruction descriptions.
323
324
325 <H3>17.2.2.1 Opcode</H3>
326
327 The "Opcode" column gives the complete object code produced for each form
328 of the instruction. When possible, the codes are given as hexadecimal bytes,
329 in the same order in which they appear in memory. Definitions of entries
330 other than hexadecimal bytes are as follows:
331
332 <DL>
333 <DT>
334 /digit:
335 <DD>(digit is between 0 and 7) indicates that the ModR/M byte of the
336 instruction uses only the r/m (register or memory) operand. The reg field
337 contains the digit that provides an extension to the instruction's opcode.
338
339 <DT>
340 /r:
341 <DD>indicates that the ModR/M byte of the instruction contains both a
342 register operand and an r/m operand.
343
344 <DT>
345 cb, cw, cd, cp:
346 <DD>a 1-byte (cb), 2-byte (cw), 4-byte (cd) or 6-byte (cp)
347 value following the opcode that is used to specify a code offset and
348 possibly a new value for the code segment register.
349
350 <DT>
351 ib, iw, id:
352 <DD>a 1-byte (ib), 2-byte (iw), or 4-byte (id) immediate operand to
353 the instruction that follows the opcode, ModR/M bytes or scale-indexing
354 bytes. The opcode determines if the operand is a signed value. All words and
355 doublewords are given with the low-order byte first.
356
357 <DT>
358 +rb, +rw, +rd:
359 <DD>a register code, from 0 through 7, added to the hexadecimal
360 byte given at the left of the plus sign to form a single opcode byte. The
361 codes are
362
363 <PRE>
364 rb rw rd
365 AL = 0 AX = 0 EAX = 0
366 CL = 1 CX = 1 ECX = 1
367 DL = 2 DX = 2 EDX = 2
368 BL = 3 BX = 3 EBX = 3
369 AH = 4 SP = 4 ESP = 4
370 CH = 5 BP = 5 EBP = 5
371 DH = 6 SI = 6 ESI = 6
372 BH = 7 DI = 7 EDI = 7
373 </PRE>
374 </DL>
375
376 <H3>17.2.2.2 Instruction</H3>
377
378 The "Instruction" column gives the syntax of the instruction statement as
379 it would appear in an ASM386 program. The following is a list of the symbols
380 used to represent operands in the instruction statements:
381
382 <DL>
383 <DT>
384 rel8:
385 <DD>a relative address in the range from 128 bytes before the end of the
386 instruction to 127 bytes after the end of the instruction.
387
388 <DT>
389 rel16, rel32:
390 <DD>a relative address within the same code segment as the
391 instruction assembled. rel16 applies to instructions with an operand-size
392 attribute of 16 bits; rel32 applies to instructions with an operand-size
393 attribute of 32 bits.
394
395 <DT>
396 ptr16:16, ptr16:32:
397 <DD>a FAR pointer, typically in a code segment different
398 from that of the instruction. The notation 16:16 indicates that the value of
399 the pointer has two parts. The value to the right of the colon is a 16-bit
400 selector or value destined for the code segment register. The value to the
401 left corresponds to the offset within the destination segment. ptr16:16 is
402 used when the instruction's operand-size attribute is 16 bits; ptr16:32 is
403 used with the 32-bit attribute.
404
405 <DT>
406 r8:
407 <DD>one of the byte registers AL, CL, DL, BL, AH, CH, DH, or BH.
408
409 <DT>
410 r16:
411 <DD>one of the word registers AX, CX, DX, BX, SP, BP, SI, or DI.
412
413 <DT>
414 r32:
415 <DD>one of the doubleword registers EAX, ECX, EDX, EBX, ESP, EBP, ESI, or
416 EDI.
417
418 <DT>
419 imm8:
420 <DD>an immediate byte value. imm8 is a signed number between -128 and
421 +127 inclusive. For instructions in which imm8 is combined with a word or
422 doubleword operand, the immediate value is sign-extended to form a word or
423 doubleword. The upper byte of the word is filled with the topmost bit of the
424 immediate value.
425
426 <DT>imm16:
427 <DD>an immediate word value used for instructions whose operand-size
428 attribute is 16 bits. This is a number between -32768 and +32767 inclusive.
429
430 <DT>
431 imm32:
432 <DD>an immediate doubleword value used for instructions whose
433 operand-size attribute is 32-bits. It allows the use of a number between
434 +2147483647 and -2147483648.
435
436 <DT>
437 r/m8:
438 <DD>a one-byte operand that is either the contents of a byte register
439 (AL, BL, CL, DL, AH, BH, CH, DH), or a byte from memory.
440
441 <DT>
442 r/m16:
443 <DD>a word register or memory operand used for instructions whose
444 operand-size attribute is 16 bits. The word registers are: AX, BX, CX, DX,
445 SP, BP, SI, DI. The contents of memory are found at the address provided by
446 the effective address computation.
447
448 <DT>
449 r/m32:
450 <DD>a doubleword register or memory operand used for instructions whose
451 operand-size attribute is 32-bits. The doubleword registers are: EAX, EBX,
452 ECX, EDX, ESP, EBP, ESI, EDI. The contents of memory are found at the
453 address provided by the effective address computation.
454
455 <DT>
456 m8:
457 <DD>a memory byte addressed by DS:SI or ES:DI (used only by string
458 instructions).
459
460 <DT>
461 m16:
462 <DD>a memory word addressed by DS:SI or ES:DI (used only by string
463 instructions).
464
465 <DT>
466 m32:
467 <DD>a memory doubleword addressed by DS:SI or ES:DI (used only by string
468 instructions).
469
470 <DT>
471 m16:16, M16:32:
472 <DD>a memory operand containing a far pointer composed of two
473 numbers. The number to the left of the colon corresponds to the pointer's
474 segment selector. The number to the right corresponds to its offset.
475
476 <DT>
477 m16 & 32, m16 & 16, m32 & 32:
478 <DD>a memory operand consisting of data item pairs
479 whose sizes are indicated on the left and the right side of the ampersand.
480 All memory addressing modes are allowed. m16 & 16 and m32 & 32 operands are
481 used by the <A HREF="BOUND.htm">BOUND</A> instruction to provide an operand containing an upper and
482 lower bounds for array indices. m16 & 32 is used by
483 <A HREF="LGDT.htm">LIDT</A> and <A HREF="LGDT.htm">LGDT</A> to
484 provide a word with which to load the limit field, and a doubleword with
485 which to load the base field of the corresponding Global and Interrupt
486 Descriptor Table Registers.
487
488 <DT>
489 moffs8, moffs16, moffs32:
490 <DD>(memory offset) a simple memory variable of type
491 BYTE, WORD, or DWORD used by some variants of the
492 <A HREF="MOV.htm">MOV</A> instruction. The
493 actual address is given by a simple offset relative to the segment base. No
494 ModR/M byte is used in the instruction. The number shown with moffs
495 indicates its size, which is determined by the address-size attribute of the
496 instruction.
497
498 <DT>
499 Sreg:
500 <DD>a segment register. The segment register bit assignments are ES=0,
501 CS=1, SS=2, DS=3, FS=4, and GS=5.
502 </DL>
503
504 <H3>17.2.2.3 Clocks</H3>
505
506 The "Clocks" column gives the number of clock cycles the instruction takes
507 to execute. The clock count calculations makes the following assumptions:
508
509 <UL>
510 <LI> The instruction has been prefetched and decoded and is ready for
511 execution.
512
513 <LI> Bus cycles do not require wait states.
514
515 <LI> There are no local bus HOLD requests delaying processor access to the
516 bus.
517
518 <LI> No exceptions are detected during instruction execution.
519
520 <LI> Memory operands are aligned.
521 </UL>
522
523 Clock counts for instructions that have an r/m (register or memory) operand
524 are separated by a slash. The count to the left is used for a register
525 operand; the count to the right is used for a memory operand.
526 <P>
527 The following symbols are used in the clock count specifications:
528
529 <UL>
530 <LI> n, which represents a number of repetitions.
531
532 <LI> m, which represents the number of components in the next instruction
533 executed, where the entire displacement (if any) counts as one
534 component, the entire immediate data (if any) counts as one component,
535 and every other byte of the instruction and prefix(es) each counts as
536 one component.
537
538 <LI> pm=, a clock count that applies when the instruction executes in
539 Protected Mode. pm= is not given when the clock counts are the same for
540 Protected and Real Address Modes.
541 </UL>
542
543 When an exception occurs during the execution of an instruction and the
544 exception handler is in another task, the instruction execution time is
545 increased by the number of clocks to effect a task switch. This parameter
546 depends on several factors:
547
548 <UL>
549 <LI>The type of TSS used to represent the current task (386 TSS or 286
550 TSS).
551
552 <LI>The type of TSS used to represent the new task.
553
554 <LI>Whether the current task is in V86 mode.
555
556 <LI>Whether the new task is in V86 mode.
557 </UL>
558
559 Table 17-5 summarizes the task switch times for exceptions.
560
561 <PRE>
562 Table 17-5. Task Switch Times for Exceptions
563
564 New Task
565
566 Old 386 TSS 286 TSS
567 Task VM = 0
568
569 386 VM = 0 309 282
570 TSS
571
572 386 VM = 1 314 231
573 TSS
574
575 286 307 282
576 TSS
577 </PRE>
578
579 <H3>17.2.2.4 Description</H3>
580
581 The "Description" column following the "Clocks" column briefly explains the
582 various forms of the instruction. The "Operation" and "Description" sections
583 contain more details of the instruction's operation.
584
585
586 <H3>17.2.2.5 Operation</H3>
587
588 The "Operation" section contains an algorithmic description of the
589 instruction which uses a notation similar to the Algol or Pascal language.
590 The algorithms are composed of the following elements:
591
592 <UL>
593 <LI> Comments are enclosed within the symbol pairs "(*" and "*)".
594
595 <LI> Compound statements are enclosed between the keywords of the "if" statement
596 (IF, THEN, ELSE, FI) or of the "do" statement (DO, OD), or of the "case"
597 statement (CASE ... OF, ESAC).
598
599 <LI> A register name implies the contents of the register. A register name
600 enclosed in brackets implies the contents of the location whose address is
601 contained in that register. For example, ES:[DI] indicates the contents of
602 the location whose ES segment relative address is in register DI. [SI]
603 indicates the contents of the address contained in register SI relative to
604 SI's default segment (DS) or overridden segment.
605
606 <LI> Brackets also used for memory operands, where they mean that the contents
607 of the memory location is a segment-relative offset. For example, [SRC]
608 indicates that the contents of the source operand is a segment-relative
609 offset.
610
611 <LI> A := B; indicates that the value of B is assigned to A.
612
613 <LI> The symbols =, <>, >=, and <= are relational operators used to compare two
614 values, meaning equal, not equal, greater or equal, less or equal,
615 respectively. A relational expression such as A = B is TRUE if the value of
616 A is equal to B; otherwise it is FALSE.
617 </UL>
618
619 The following identifiers are used in the algorithmic descriptions:
620 <UL>
621 <LI> OperandSize represents the operand-size attribute of the instruction,
622 which is either 16 or 32 bits. AddressSize represents the address-size
623 attribute, which is either 16 or 32 bits. For example,
624
625 <PRE>
626 IF instruction = CMPSW
627 THEN OperandSize \e 16;
628 ELSE
629 IF instruction = CMPSD
630 THEN OperandSize \e 32;
631 FI;
632 FI;
633 </PRE>
634
635 indicates that the operand-size attribute depends on the form of the CMPS
636 instruction used. Refer to the explanation of address-size and operand-size
637 attributes at the beginning of this chapter for general guidelines on how
638 these attributes are determined.
639
640 <LI> StackAddrSize represents the stack address-size attribute associated
641 with the instruction, which has a value of 16 or 32 bits, as explained
642 earlier in the chapter.
643
644 <LI> SRC represents the source operand. When there are two operands, SRC is
645 the one on the right.
646
647 <LI> DEST represents the destination operand. When there are two operands,
648 DEST is the one on the left.
649
650 <LI> LeftSRC, RightSRC distinguishes between two operands when both are
651 source operands.
652
653 <LI> eSP represents either the SP register or the ESP register depending on
654 the setting of the B-bit for the current stack segment.
655 </UL>
656
657 The following functions are used in the algorithmic descriptions:
658
659 <UL>
660 <LI> Truncate to 16 bits(value) reduces the size of the value to fit in 16
661 bits by discarding the uppermost bits as needed.
662
663 <LI> Addr(operand) returns the effective address of the operand (the result
664 of the effective address calculation prior to adding the segment base).
665
666 <LI> ZeroExtend(value) returns a value zero-extended to the operand-size
667 attribute of the instruction. For example, if OperandSize = 32,
668 ZeroExtend of a byte value of -10 converts the byte from F6H to
669 doubleword with hexadecimal value 000000F6H. If the value passed to
670 ZeroExtend and the operand-size attribute are the same size,
671 ZeroExtend returns the value unaltered.
672
673 <LI> SignExtend(value) returns a value sign-extended to the operand-size
674 attribute of the instruction. For example, if OperandSize = 32,
675 SignExtend of a byte containing the value -10 converts the byte from
676 F6H to a doubleword with hexadecimal value FFFFFFF6H. If the value
677 passed to SignExtend and the operand-size attribute are the same size,
678 SignExtend returns the value unaltered.
679
680 <LI> Push(value) pushes a value onto the stack. The number of bytes pushed
681 is determined by the operand-size attribute of the instruction. The
682 action of Push is as follows:
683
684 <PRE>
685 IF StackAddrSize = 16
686 THEN
687 IF OperandSize = 16
688 THEN
689 SP \e SP - 2;
690 SS:[SP] \e value; (* 2 bytes assigned starting at
691 byte address in SP *)
692 ELSE (* OperandSize = 32 *)
693 SP \e SP - 4;
694 SS:[SP] \e value; (* 4 bytes assigned starting at
695 byte address in SP *)
696 FI;
697 ELSE (* StackAddrSize = 32 *)
698 IF OperandSize = 16
699 THEN
700 ESP \e ESP - 2;
701 SS:[ESP] \e value; (* 2 bytes assigned starting at
702 byte address in ESP*)
703 ELSE (* OperandSize = 32 *)
704 ESP \e ESP - 4;
705 SS:[ESP] \e value; (* 4 bytes assigned starting at
706 byte address in ESP*)
707 FI;
708 FI;
709 </PRE>
710
711 <LI> Pop(value) removes the value from the top of the stack and returns it.
712 The statement EAX \e Pop( ); assigns to EAX the 32-bit value that Pop
713 took from the top of the stack. Pop will return either a word or a
714 doubleword depending on the operand-size attribute. The action of Pop
715 is as follows:
716
717 <PRE>
718 IF StackAddrSize = 16
719 THEN
720 IF OperandSize = 16
721 THEN
722 ret val \e SS:[SP]; (* 2-byte value *)
723 SP \e SP + 2;
724 ELSE (* OperandSize = 32 *)
725 ret val \e SS:[SP]; (* 4-byte value *)
726 SP \e SP + 4;
727 FI;
728 ELSE (* StackAddrSize = 32 *)
729 IF OperandSize = 16
730 THEN
731 ret val \e SS:[ESP]; (* 2 bytes value *)
732 ESP \e ESP + 2;
733 ELSE (* OperandSize = 32 *)
734 ret val \e SS:[ESP]; (* 4 bytes value *)
735 ESP \e ESP + 4;
736 FI;
737 FI;
738 RETURN(ret val); (*returns a word or doubleword*)
739 </PRE>
740
741 <LI> Bit[BitBase, BitOffset] returns the address of a bit within a bit
742 string, which is a sequence of bits in memory or a register. Bits are
743 numbered from low-order to high-order within registers and within
744 memory bytes. In memory, the two bytes of a word are stored with the
745 low-order byte at the lower address.
746 <P>
747 If the base operand is a register, the offset can be in the range 0..31.
748 This offset addresses a bit within the indicated register. An example,
749 "BIT[EAX, 21]," is illustrated in
750 <A HREF="#fig17-3">Figure 17-3</A>
751 .
752 <P>
753 If BitBase is a memory address, BitOffset can range from -2 gigabits to 2
754 gigabits. The addressed bit is numbered (Offset MOD 8) within the byte at
755 address (BitBase + (BitOffset DIV 8)), where DIV is signed division with
756 rounding towards negative infinity, and MOD returns a positive number.
757 This is illustrated in
758 <A HREF="#fig17-4">Figure 17-4</A>
759 .
760
761 <LI> I-O-Permission(I-O-Address, width) returns TRUE or FALSE depending on
762 the I/O permission bitmap and other factors. This function is defined as
763 follows:
764
765 <PRE>
766 IF TSS type is 286 THEN RETURN FALSE; FI;
767 Ptr \e [TSS + 66]; (* fetch bitmap pointer *)
768 BitStringAddr \e SHR (I-O-Address, 3) + Ptr;
769 MaskShift \e I-O-Address AND 7;
770 CASE width OF:
771 BYTE: nBitMask \e 1;
772 WORD: nBitMask \e 3;
773 DWORD: nBitMask \e 15;
774 ESAC;
775 mask \e SHL (nBitMask, MaskShift);
776 CheckString \e [BitStringAddr] AND mask;
777 IF CheckString = 0
778 THEN RETURN (TRUE);
779 ELSE RETURN (FALSE);
780 FI;
781 </PRE>
782
783 <LI> Switch-Tasks is the task switching function described in
784 <A HREF="c07.htm">Chapter 7</A>.
785
786
787 <H3>17.2.2.6 Description</H3>
788
789 The "Description" section contains further explanation of the instruction's
790 operation.
791 <P>
792 <A NAME="fig17-3">
793 <IMG align=center SRC="fig17-3.gif" border=0>
794 <P>
795 <A NAME="fig17-4">
796 <IMG align=center SRC="fig17-4.gif" border=0>
797
798 <H3>17.2.2.7 Flags Affected</H3>
799
800 The "Flags Affected" section lists the flags that are affected by the
801 instruction, as follows:
802 <UL>
803 <LI> If a flag is always cleared or always set by the instruction, the
804 value is given (0 or 1) after the flag name. Arithmetic and logical
805 instructions usually assign values to the status flags in the uniform
806 manner described in <A HREF="appc.htm">Appendix C</A>. Nonconventional assignments are
807 described in the "Operation" section.
808
809 <LI> The values of flags listed as "undefined" may be changed by the
810 instruction in an indeterminate manner.
811 </UL>
812
813 All flags not listed are unchanged by the instruction.
814
815
816 <H3>17.2.2.8 Protected Mode Exceptions</H3>
817
818 This section lists the exceptions that can occur when the instruction is
819 executed in 80386 Protected Mode. The exception names are a pound sign (#)
820 followed by two letters and an optional error code in parentheses. For
821 example, #GP(0) denotes a general protection exception with an error code of
822 0. Table 17-6 associates each two-letter name with the corresponding
823 interrupt number.
824 <P>
825
826 <A HREF="c09.htm">Chapter 9</A>
827 describes the exceptions and the 80386 state upon entry to the
828 exception.
829 <P>
830 Application programmers should consult the documentation provided with
831 their operating systems to determine the actions taken when exceptions
832 occur.
833
834 <PRE>
835 Table 17-6. 80386 Exceptions
836
837 Mnemonic Interrupt Description
838
839 #UD 6 Invalid opcode
840 #NM 7 Coprocessor not available
841 #DF 8 Double fault
842 #TS 10 Invalid TSS
843 #NP 11 Segment or gate not present
844 #SS 12 Stack fault
845 #GP 13 General protection fault
846 #PF 14 Page fault
847 #MF 16 Math (coprocessor) fault
848 </PRE>
849
850 <H3>17.2.2.9 Real Address Mode Exceptions</H3>
851
852 Because less error checking is performed by the 80386 in Real Address Mode,
853 this mode has fewer exception conditions . Refer to
854 <A HREF="c14.htm">Chapter 14</A>
855 for further
856 information on these exceptions.
857
858
859 <H3>17.2.2.10 Virtual-8086 Mode Exceptions</H3>
860
861 Virtual 8086 tasks provide the ability to simulate Virtual 8086 machines.
862 Virtual 8086 Mode exceptions are similar to those for the 8086 processor,
863 but there are some differences . Refer to
864 <A HREF="c15.htm">Chapter 15</A>
865 for details .
866 <P>
867 <HR>
868 <P>
869 <B>up:</B> <A HREF="c17.htm">
870 Chapter 17 -- 80386 Instruction Set</A><BR>
871 <B>prev:</B> <A HREF="s17_01.htm">
872 17.1 Operand Size and Address-Size Attributes</A><BR>
873 <B>next:</B> <A HREF="AAA.htm"> AAA ASCII Adjust after Addition</A>
874 </BODY>